Nanoelectronics: From Silicon to Graphene

Udo Schwalke, Juliane Wessely, Frank Wessely, Martin Keyn, Lorraine Rispal Institute for Semiconductor Technology and Nanoelectronics

Technische Universität Darmstadt Darmstadt, Germany

schwalke@iht.tu-darmstadt.de

Abstract— In the future of nanoelectronics, the use of pure silicon based devices will not be possible anymore since the limit of silicon are already reached. Carbon seems to be a great alternative to build high performance electronic devices. Carbon nanotube field-effect transistors can be used as active device in integrated circuits, as memory cell in numerous applications. More recently, graphene-based transistors are emerging as another potential candidate to extend and eventually replace the traditional planar MOSFET.

I. INTRODUCTION

Since the first integrated circuits in the late 1960’s, a

constant improvement of their performances could be reached by scaling down the metal oxide semiconductor field-effect transistors (MOSFETs). The down scaling is predicted by the well-known Moore’s law, which enunciates that the number of devices on a chip should double every 18 months. At the same time, the speed should increase whereas the cost should decrease. However, downscaling of MOS transistors has reached its physical limits: the gate oxide is only composed of a few atomic layers, leakage currents are increasing and the short channel effects degrade device properties. These are a few reasons why new integration concepts need to be developed to extend silicon based nanoelectronics. One of these concepts involves carbon nanotube field-effect transistors (CNTFETs) [1]. The active part of CNTFETs, i.e., the channel, is formed by a semiconducting single-walled carbon nanotube (SWNT), the growth of which represents one of the great challenges of CNT technology. Besides the use in field-effect transistors and memory cells, CNTs are also of interest to be used in sensor applications [2, 3]

II. HEXAGONAL CARBON FOR ELECTRONICS

Carbon nanotubes (see Fig. 1 middle left) are hollow

cylinders which length, in the micrometer range, is much larger than their diameter (a few nanometers), so that they can be considered as one-dimensional molecules. Their crystalline structure has to be imagined as the hexagonal honeycomb lattice of graphene which is rolled up (see Fig. 1 bottom left). This lattice is only composed of carbon atoms. Graphene is a two dimensional material which represents the special case of a piece of graphite (see Fig. 1 right) with only one layer. A last material has a structure which derives from graphene: the so-called buckminsterfullerene. They are stable football-like clusters of 60 carbon atoms, with 12 pentagons and 20

hexagons (see Fig. 1 top left). Harold W. Kroto, Richard E. Smalley, and Robert F. Curl received the Nobel prize in chemistry in 1996 for the discovery of the fullerenes. The diameter in the nanometer range made fullerenes to quasi zero dimensional structures.

Figure 1. Different forms of carbon with an hexagonal lattice.

In electronics, graphene and carbon nanotubes play a major role because they can both be used as active material to build the channel of field-effect transistors. Since carrier mobilities are much higher than in silicon, high performance devices with switching speeds up to the THz region are theoretically feasible [8].

III. CARBON NANOTUBES DEVICES

A. Carbon nanotube field-effect transistors

CNTFETs belong to the so-called molecular electronics.

The approach of molecular electronics differs from the conventional electronics manufacture. Indeed, the conventional technology is based on the top-down approach, i.e., macroscopic silicon wafers are structured to obtain billions of tiny devices, which are constantly miniaturized year after year. Molecular electronics use the bottom-up assembly principles, i.e., tiny molecules are taken as basis of the structure to build the device.

A candidate for replacing the MOSFET should not only have better performances but it should also be possible to produce it in large quantities to allow integration on a very large scale, i.e., millions of transistors on one wafer. Most of the CNTFETs have been described as being fabricated by

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manually placing the nanotubes on the wafer, either only by spin coating or by nanomanipulation, for instance via atomic force microscopy (AFM). Nanomanipulation is probably incompatible with large scale fabrication. We have demonstrated a novel fabrication process for Pd-contacted and PMMA passivated CNTFETs which only requires one lithography step, avoiding any misalignment problems (see Fig. 2 for schematic of a CNTFET) [1]. In situ growth makes the process suitable for large-scale manufacturing. “In situ” is a Latin expression which means “in the place”, so that “in situ growth of CNTs” means that the tubes are grown directly in their final place, within the device or circuit on the wafer. The controlled growth of SWNTs by catalytic chemical vapor deposition on oxidized silicon substrates covered by a catalytic layer composed of nickel on aluminum has been demonstrated. A thousand transistors have been fabricated on one wafer.

Figure 2. Schematic of a PMMA passivated CNTFET and electrical conections.

The functional devices have promising electrical parameters: on/off ratios over 2�107 and on-currents in the μA range at a drain source voltage of -400 mV, illustrating the potential of the CNTFET technology (see Fig. 3 for an example of CNTFET transfer characteristics).

Figure 3. Example of transfer characteristics measured on CNTFET with semiconducting SWNT as channel.

B. Carbon nanotube non-volatile memory

CNTFETs do not only work as conventional FETs, but may

also be used as non-volatile memory cells. In 2002, Fuhrer et al. reported on a high-mobility s-SWNT transistor used as a nonvolatile charge-storage memory element operating at room temperature [4]. The s-SWNT is directly used as the readout, based on the hysteresis in the transfer characteristics of the FET (see Fig. 3). The hysteresis is the horizontal shift between the two sweeps measured respectively at Vgs increasing and decreasing and is a typical phenomenon in CNTFETs.

At ISTN, the utilization of CNTFETs as non volatile memory cells has been found to be very promising [5]. As shown in Fig. 5, applying a gate voltage pulse of -5 V is sufficient to obtain nearly the on-current value of 0.1 μA at a reading voltage of 2 V. Accordingly, when applying a programming gate voltage pulse of 5 V and subsequently reading at 2 V, the measured current is equal to the off-current of 0.1 pA. The “0” and “1” current levels are seen to be temporally stable. The current ratio at the reading voltage between the logical “1” level (on-current) and the logical ”0” (off-current) is called the 1/0 ratio. To insure sufficient signal-to-noise properties this ratio should be as high as possible. The device in Fig. 5 exhibits a 1/0 ratio of 106. To the best of our knowledge, these are the CNT memory devices with the highest “1/0” ratio ever published at ultra low drain bias of -400 mV.

Figure 4. Cycling of CNTFET memory cell. Applied gate voltage and measured drain-source current plotted versus time.

IV. GRAPHENE DEVICES

For graphene to become a viable material for transistor

applications a reasonable band gap has to exist. It is possible to open up a gap in single layer graphene by constricting the lateral dimensions to produce zero-dimensional structures, or quantum dots, and one-dimensional structures such as grapheme nanoribbons (GNRs).

GNR field-effect transistors (FETs) have been reported in [6] and theoretically investigated in [7]. IBM announced in December 2008 the fabrication and characterization of graphene transistors operating at GHz frequencies [8].

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With a similar CVD process as for the growth of carbon nanotubes, it has been tried to fabricate graphene at ISTN. The result, shown in Fig. 6, is an ultra thin layer of a carbon material, with a thickness below 3 nm, which could correspond to a graphite layer with only three or four graphene flakes.

Figure 5. AFM scan of in-situ grown ultra thin carbon layer. The ultra reduced thickness of the layer could correpond to a graphite layer with only a few graphene flakes.

V. CONCLUSION

Carbon based devices show promising features, so that they are well-known as potential candidates to replace silicon-based MOSFETs in the future. However, only a few attempts have been made to test the feasibility to integrate these devices in a large scale. The work at ISTN has shown that in-situ growth of carbon nanotubes could be a solution to obtain the large scale fabrication of high quality CNT-based devices, which can also be used as memory cells. In a future work, we will investigate the possibility to use our devices in different sensor applications. The feasibility of growing graphene catalytically and integrate graphene nanoribbons into nanodevices in a similar way as carbon nanotubes also belong to our future prospect.

REFERENCES

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[4] M. S. Fuhrer, B. M. Kim, T. Dürkop, and T. Brintlinger, "High-Mobility Nanotube Transistor Memory," Nano Lett., vol. 2, pp. 755-759, 2002.

[5] L. Rispal and U. Schwalke, "Large-Scale In Situ Fabrication of Voltage-Programmable Dual-Layer High-k Dielectric Carbon Nanotube Memory Devices With High On/Off Ratio," IEEE Electron Device Lett., vol. 29, pp. 1349-1352, 2008.

[6] M. C. Lemme, T. J. Echtermeyer, M. Baus, and H. Kurz, "A Graphene Field-Effect Device," IEEE Electron Device Lett., vol. 28, pp. 282-284, 2007.

[7] G. Liang, N. Neophytou, M. S. Lundstrom, and D. E. Nikonov, "Ballistic graphene nanoribbon metal-oxide-semiconductor field-effect transistors: A full real-space quantum transport simulation," J. Appl. Phys., vol. 102, pp. 054307-7, 2007.

[8] Y.-M. Lin, K. A. Jenkins, A. Valdes-Garcia, J. P. Small, D. B. Farmer, and P. Avouris, "Operation of Graphene Transistors at Gigahertz Frequencies," Nano Lett., vol. 9, pp. 422-426, 2008.

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