ENCLOSED LAYOUT TRANSISTOR WITH ACTIVE REGION CUTOUT

Shuza Binzaid1, John O. Attia

1, Ron D. Schrimpf

2,

1 Department of Electrical and Computer Engineering, Prairie View A&M University,

Prairie View, TX 77446, USA

2Department of Electrical Engineering and Computer Science, Vanderbilt University,

Nashville, TN 37235, USA

ABSTRACT

An Enclosed-Layout-Transistor (ELT) is modified using the

active region cutout (ARC) technique. This transistor is called

ARCELT. 3-D simulations were performed to obtain the

leakage current with respect to radiation induced charge

density, while keeping the layout dimensions and process

parameters unchanged, for a standard nMOS transistor, the

ELT and the ARCELT. The aspect ratio W/L of ARCELT

was found to be smaller than ELT. It is shown that the

ARCELT has radiation tolerance similar to that of ELT. The

ARCELT can be configured as a triple electrode MOSFET

device that can be used to design compound transistors. Two

applications of ARCELT as a compound transistor are shown.

1. INTRODUCTION

Semiconductor devices at sub-micron and nano-meter

feature sizes suffer from radiation in harsh environments like

space. Approaches have been taken to make these devices

immuned to radiation by design. Many such successful

designs, generally called radiation-hardened-by-design

(RHBD) MOSFETS, have been are introduced over the years.

Two of these well known devices are enclosed-layout-

transistor (ELT) and H-GATE [1,2]. The latter two devices

take more space on the silicon than a standard MOSFET.

Figure 1 shows 2-D layout of the ELT and standard MOSFET.

Figure 1: An ELT (left) and a simple MOSFET (right).

Fabrication processes are evolving to newer technologies

that allow devices to be produced geometrically in smaller

sizes. Also, several investigators are doing research to find

techniques that can replace more than one transistor in a

circuit with a single one and maintain the circuit functionality.

An active-region-cutout (ARC) technique was developed to

overcome the short between the drain and the source, wherein

the poly gate does not have an extension beyond the active

region. ARC technique removes a small part of active short

area, and thus removing the short in the device. ARC

technique is shown in figure 2 [3]. The poly extension out of

the device was made through two electrodes, connected by a

metal, in the same active region. This technique makes the two

electrodes equipotential.

Figure 2: The ARCT showing ARC cut regions [3].

2. RADIATION EFFECTS ON MOSFETS

The Radiation-induced leakage mechanism is illustrated in

figure 3 for a standard MOSFET. In a standard MOSFET,

device operating threshold voltage can change due to

accumulation of charges. First, changes occur at the interface

corners. Channel inversion takes place at interface corners. If

strong enough, the accumulated charges affect STI edges

along the channel near the interface. The device turns and

leakage path is created [4]. The ARCT and ELT, in contrast to

the standard MOSFET, have shapes that considerably reduce

the edge leakage current corners.

The ELT is a very popular radiation hardened device

because it does not have a STI edge and corners. The inner

electrode does not have STI edges. So the STI interface

charge accumulation is not possible. Also the edges of the

gate of i.e. inner and outer edge of active regions do not

intersect. So there is no leakage path between source and

drain. On the other hand, the standard transistor has the edges

of source, drain and gate that meet against the same STI edge

interface, causing a leakage path.

ARC ARC

cutcut

978-1-4244-2077-3/08/$25.00 ©2008 IEEE.

Figure 3: Radiation effects at interface. Sketch of top and side

view of a standard MOSFET [4].

3. FEATURES OF THE ARCELT

Figure 4 shows the 2-D layout of the active region cutout

enclosed layout transistor (ARCELT). The latter transistor has

the combined features of an ELT and ARCT. ARCELT has

two active region cutouts and a pseudo-enclosed active area

that surrounds the gate like an ELT. There is an electrode at

the center of the device enclosed by the gate poly. There are

two electrodes outside of the gate poly separated by ARCs

shown in figure 4. By having this enhancement to the layout

of ELT, the ARCELT became truly a tri-electrode MOSFET.

With these three electrodes, ARCELT has enhanced the

ELT to make it a compound MOSFET. ARCELT’s source (S)

and drain (D) can be configured as SDS, DSD, SSD and DDS

for three-electrode type device. For example, figure 4 is

configured as SDS. Also it can be configured as a normal ELT

with only one source and one drain when outer electrodes are

connected with metal. This feature makes the ARCELT very

flexible in design.

The device aspect ratio, W/L is changed significantly for

ELT as compared to the ARCELT. The layouts of the ELT

and ARCELT with the same area were used in the

comparative study. The W/L values were compared when

both of these devices were configured as two-electrode

devices. The ELT was found to have W/L = 23. On the other

hand, the ARCELT had W/L = 10.3. Figure 5 shows the

layout of ELT used for this comparison. The area of silicon

acquired by these devices is same.

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charges at in terfac e c orn er

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equipotentia

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Figure 4: ARCELT configured as SDS, showing ARC

regions.

S

D

S

D

Figure 5: The ELT for W/L comparison with the ARCELT.

4. SIMULATIONS AND RESULTS COMPARISON

The ELT and the ARCELT transistors were designed. 3-D

simulations were performed. The devices had power applied

to active contacts. Also the gate contacts were left floating to

create the worst conditions under radiation effects. Total

current from source to drain was measured under the

condition of the increasing radiation induced accumulated

charges. This is the leakage current of the device. Figure 6

shows the induced leakage current of the ARCT with respect

to charge density at the interface. The leakage current is

2.23e-08 amps at 1E12 charge density. The leakage current of

a standard MOSFET is shown in figure 7. The plot shows that

the simple MOSFET has leakage current around 22e-05 amps

at 1E12 charge density. It can be seen that the ARCT has

much lower leakage current compared to that of the standard

MOSFET.

The leakage currents at different charge densities of N-type

standard MOSFET, ARCT, ELT and ARCELT are given in

table 1. From this table, it is found that a simple MOSFET has

8.5E3 times higher leakage current than ELT and 8.2E3 times

higher leakage current than ARCELT, thus making them

RHBD transistors.

Figure 6: Leakage Current vs. Interface charge density of the

ARCT.

Figure 7: Leakage Current vs. Interface charge density of a

standard MOSFET.

Simulations results indicate that ELT has leakage current

that is less when the device is configured as source at the

outside electrode. Larger leakage current is observed when

drain is at outside of the device. The ARCELT behaved very

similar to the ELT. The radiation-induced leakage current was

about 2.7e-8 amps when the drain was outside of the

ARCELT. This leakage current was reduced to around 2.3e-8

when source was placed outside of the device. Table 2 shows

the comparison of ELT and ARCELT with configurations

where source is outside in ‘c1’ and Drain in outside in ‘c2’.

Figure 4 shows the configuration for ‘c1’ from the table 2. So

the ‘c2’ is where Source is the inner active region of

ARCELT.

Radiation Charge Density

Cu

rren

t

Radiation Charge Density

Cu

rren

t

Table 1

Radiation-Induced Leakage Currents at Charge

Density for Transistors

Device Leakage Currents @ charge density

Name 1.00E+08 1.00E+09 1.00E+10 1.00E+11 1.00E+12

Standard

MOSFET 1.00E-05 1.05E-05 1.10E-05 2.20E-05 2.20E-04

ARCT 2.00E-08 2.10E+08 2.11E-08 2.14E-08 2.24E-08

ELT 2.26E-08 2.27E-08 2.27E-08 2.32E-08 2.61E-08

ARCELT 2.15E-08 2.15E-08 2.15E-08 2.18-08 2.70E-08

Table 2

Radiation-Induced Leakage Currents at Charge

Density for Transistors with Different Configurations

Radiation Charge Density

Cu

rren

t

Radiation Charge Density

Cu

rren

t

Device Leakage Currents @ charge density

Name 1.00E+08 1.00E+09 1.00E+10 1.00E+11 1.00E+12

ELT(c1) 2.25E-08 2.26E-08 2.27E-08 2.28E-08 2.30E-08

ELT(c2) 2.26E-08 2.27E-08 2.27E-08 2.32E-08 2.61E-08

ARCELT(c1) 2.10E-08 2.10E-08 2.15E-08 2.17E-08 2.32E-08

ARCELT(c2) 2.15E-08 2.15E-08 2.15E-08 2.18E-08 2.70E-08

5. ILLUSTRATIONS OF APPLICATION

OF THE ARCELT

The ARCELT can be configured as a compound transistor

in circuits wherein two or more transistor can be replaced by a

single ARCELT. The circuits replaced will also have very low

radiation induced leakage current. Figure 8 shows the sense

amplifier that can be replaced with a radiation-hardened

ARCELT. This figure shows in (a) the circuit diagram of first

stage of sense amplifier with memory, (b) the layout of the

first stage of amplifier and (c) the ARCELT that can replace

the part of the circuit.

In this circuit in figure 8(a), the pre-charge stage consists of

M1, M2 and M3 MOSFETs. They provide equalized potential

to the node. Figure (c) shows the compound ARCELT that

can replace these three MOSFETS in pre-charge stage. The

next circuit illustration in figure 9 shows an input sampling

network of a comparator. Two NMOS transistors are used for

output stage.

Figure 8: The first stage of a sense amplifier; (a) circuit, (b)

layout and (C) ARCELT. It has replaced the pre-

charge stage for radiation hardening [5].

These transistors have common gate for switching and a

common source for Vss. These two NMOS transistors are M4

and M5 consisting OUT1-H-Vss and OUT2-H-Vss to

represent as n-p-n. They can be replaced with an ARCELT,

providing radiation immunity to the circuit.

Many other types of circuits can be replaced with the

ARCELT. Applying this concept can increase the device

density and thus reduce the cost of the integrated circuits.

Circuits can be compact and also can reduced equivalent

circuit impedance by eliminating wires and contacts.

BLR

BLL

PRE

(a)

(b)

(c)

Figure 9: The input sampling network of a comparator [6].

ARCELT can replace the output stage.

6. CIRCUIT LAYOUT EXTRACTION, SPICE

SIMULATIONS AND RESULTS

A layout is first extracted to an intermediate script format

before it can be converted to a SPICE circuit description

format. A compound device cannot be extracted directly from

the layout. An equivalent layout of compound transistor can

be created where the tools can see it as separate transistors.

Figure 10 and 11 show the layout of ARCELT and the

equivalent ARCELT respectively.

M4

M5

OUT1

OUT2

H

M4

M5

OUT1

OUT2

H

M4

M5

OUT1

OUT2

H

M4

M5

OUT1

OUT2

H

Figure 10: The ARCELT with labels used for extraction.

Basically, the extraction tool looks for two gate edges that

separate two active regions. Thus the tool concludes a device

to be a transistor. The ELT has two poly edges with inner and

outer active regions. It extracts fine. But incase of ARCELT,

it finds more than two active edges with poly. As the tools

setup today as soon as it finds two poly edges with two active

regions it concludes a transistor and ignores the other active

region. Thus the tool misinterprets and fails to extract a

composite transistor.

Figure 10: The equivalent ARCELT with labels used for

extraction for SPICE.

After the layout is extracted, appropriate transistor model

parameters and also the signals were assigned in the SPICE

circuit definition file. After the simulation was run, the plot

with the probe data were produced. The plot of SPICE

simulation of the compound ARCELT in figure 11 is given

below. The plot corresponds to V(3) = Out1, V(4) = Out2 and

V(5) = H. Also V(1) = IN1 = 5V and V(2) = IN2 = 0.5V in

figure 9.

Figure 11: The plot of SPICE simulation of the compound

ARCELT.

7. CONCLUSIONS

ARCELT is compared with ELT. Simulation results show

that ARCELT behaves similar to ELT. Also ARCELT has

much less radiation-induced leakage current than a standard

MOSFET. ARCELT has another advantage over ELT in that

it can be configured as more than one transistor. The

compound ARCELT has been used in the design of sense

amplifier and CMOS comparator. Thus resulting circuit

occupies less silicon area and it is radiation tolerant with

respect to total ionizing dose radiation.

8. ACKNOWLEDGEMENTS

This work was supported by the National Science

Foundation, under award number 0531507. Any opinions,

findings, and conclusions or recommendations expressed in

this work are those of the authors and do not necessarily

reflect those of the National Science Foundation.

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