A New CMOS Current Reference with High Order

Temperature Compensation

Zhou Hao*, Zhang Bo, Li Zhao-ji, Luo PingSchool of Microelectronics and Solid-State Electronics

University of Electronic Science and Technology of ChinaChengdu China

E-mail: semi chip@163.com

Abstract-A new high order CMOS temperature compensatedcurrent reference is proposed in this paper, which isaccomplished by two first order temperature compensationcurrent references. The novel circuit exploits the temperaturecharacteristics of integrated-circuit resistors and gate-sourcevoltage of MOS transistors working in weak inversion. Theproposed circuit, designed with a 0.6 gm standard CMOStechnology, gives a good temperature coefficient of 31ppm/0C[-50A100 °C ] at a 1.8 V supply, and also achieves lineregulation of 0.01%/V and -120dB PSR at 1 MHz. Comparingwith other presented work, the proposed circuit shows bettertemperature coefficient and Line regulation.

I. INTRODUCTION

The current mode approach in circuit design is becomingmore common, because circuits designed using thisapproach will always work at higher speed than its voltagemode counterpart. However, the accuracy of current modecircuits strongly depends on temperature stability of currentreference. In voltage mode, we can use bandgap circuit orCMOS voltage reference to ensure correct standard over awide temperature range. But conventional currentreference is only addition of a PTAT (proportional toabsolute temperature) and IPTAT (inverse proportional toabsolute temperature) currentd1 4], which could not have goodtemperature coefficient only with first order temperaturecompensation. The principle of conventional compensationis showed in Fig. 1. A new high order temperaturecompensation method is described in this paper, which isshown in Fig.2. The basic principle is adding a properlyscaled curvatured-down first order temperaturecompensation current 'ref1 to a properly scaled curvatured-upfirst order temperature compensation current 'ref2, finally, thehigh order curvature correction current IREF is optimized bythe appropriated ratio of alb. Comparing with presentedworks, the proposed circuit shows a better temperaturestability with little penalty in the circuit complexity due tothe new compensation technique employed. Most ofimportant, in traditional current reference design, the

temperature coefficients (tempco) of integrated resistors areboring monsters, just the reverse, in the proposed circuitbased on MOS transistors working in weak inversion, thetempcos of resistors are well utilized.

U

I Storder temperature compensation%\"I

PTAT

Temperature

Fig. 1 Principle of conventional first order temperaturecompensation

=1(1)t.I.,u

Final IREF=aIJef1+ bIref21" order curvatured-up compensation I f2

1 storder curvatured-down compensation Irf

Temperature

Fig.2 Principle of proposed high order temperaturecompensation

II. VGS VERSUS TEMPERATURE IN WEAK INVERSION

For MOS transistors, the gate-source voltages less thanthe threshold voltage but high enough to create a depletionregion at the surface of the silicon, the device operates inweak inversion (subthreshold region)[5], the gate-sourcevoltage for MOS in weak inversion has been given by[6]:

0-7803-9584-0/06/$20.002006 IEEE.

I

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(1)nKT T(a +y/ 2)In0q I

where EG is the silicon bandgap energy, K is theboltzmann's constant, q is the charge of an electron, n issubthreshold slope factor, VFB is flat band voltage, y modelsthe temperature dependence of carriers' mobility and To isthe reference temperature, the drain current ID X T( . Forvalues of T near To, ln(To/T) (To -T)/T, Eq.(1) can beexpressed as follows

VGS (T) = A -BT (2)where

1<11T~~~~~~~~~~~~~~~~~F-

Fig.4~~~~oeainlamlife ici in th currntrferncC I44

Fig.4 operational amplifier circuit in the current reference

In the first sub-circuit, M1 and M2 operate in weakinversion, (WIL)21(WIL?l1, (WIL)41(W/L)3=N> 1, the voltageacross Ro is given by

A= VFB + EG -nO(a +y - 2)Toq

B -VGS (TO) + VFB + EG nK( 2(a+q y - 2

q

For typical values of parameters above, A>O, B>O, thevoltage VGS decreases with temperature

III. IMPLEMENTATION OF THE CURRENT REFERENCE

The proposed current reference shown in Fig.3 iscomposed of four sub-circuits. The first consists oftransistors M1-M4, resistors RO-R2 the op-amp OP1 andfrequency compensation capacitor to generate 'ref1 Thesecond includes transistors M8-M1l, resistors R3-R5 the op-amp OP2 and frequency compensation capacitor to give h,ef2tThe third is current superposition circuit consisting of M5-M7 to output IREF. The fourth is start-up circuit composed ofMS1-MS3, RS1-RS2. The OP1 and OP2 architectures are theP-channel input folded-cascode configuration shown inFig.4 to increase the common mode input range and toimprove the power supply rejection [7] (PSR = AIREF /AVDD)performance ofthe current reference.

VR = VT lnN (3)

For the OP1 forces the drains of M3 and M4 to be at thesame potentials and the resistance of R1 and R2 are nominalequal, 'refl can be given by

VGS3 (T) VT InNref 1(T) .+RI (T) R0(T)

(4)

In the design, R1 and R2 are implemented by negativetempco material such as high resistive poly resistor, R0 isimplemented by positive tempco material such as lowresistive poly resistor[8-9]. They can be written as

R1(T) = R1 (TO )[1 - A (T - TO)] (5)

(6)

where -2, and 2, are tempcos of resistors.

Now Eq.(4) can be expressed as

A-BT

RI (To ) [I1- / (T-ToA)VT InN

O(TO)[I + AO(T(7)

If Taylor expansions at T=To are performedon [1 - ) (T - TO)] , [1+20(T - TO)] and omit high orderterms, we obtain

ABl=A-BTV[1+(T-T°)]+ 1TnN) [ -i(T-T)] (8)

If the ratio of R1(To)IRO(TO) is m1 to make dlrefl/dT=O atT=TO, then the 1St order temperature compensation current isachieved, m1 should satisfies

B(1 +A0ITo) - AAml ~ K

(1- AOTO) InNq

Fig.3 the complete circuit of the proposed current reference

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(9)

VGs (T)= VFB +EG + -VGS (TO)-

VFB -EGlp

Ro (T) = Ro (To)[I +Ao (T To)]

Further insight is gained by differentiating Eq.(8) withrespect to T, and yields the coefficient of T2 in hefl: 2.05u

d2hf KdT2 Irfl=2(B.+mliA,nN) (10) 2u

For typical values ofB, A(,, A, and ml are positive, thus U 1.95u

d2refl2<0 1.9u

dT2 ___________________________

So the ISt order temperature compensation current 'refl is -50 0 50 100curvatured-down. Similarly, we have Temperature [linl [DEG Cl

Fig.5 The curvatured-down current AIh fl through M5Iref2 = RI(To ) [I-AO(T-TO) + hI (TO) [I + /g (T-To)] (I l) r

Making dJref2/dT=0, we get the ratio of R4(T0)1R3(To): 200n

(1I (12) 50n

(I+ ITo) InN\q

u 1 00n-Differentiating Eq.(9) with respect to T gives:

d1 K 50ne2 2(BAo +m2j1 InN) >0 (13) 50n_ _ _ _

dT q .-50 0 50 100

From Eq.(11), we can know that the Ist order temperature Temperature (lin] (DEIG_Qcompensation current 'rep2 is curvatured-up. eFig.6 The curvatured-up current Bhef2 through M6

The high order temperature compensation IREF flowingthrough M7 in Fig.3 is achieved by the superposition of anappropriated scaled curvatured- down 'ref1 and thecurvatured-uplref2, that is: 2.104u

IREF =AIf +BI (14) 2.102uwhere A and B are constants defined by mirror ratios of : 2.1 u(WL)5 (W/L)2and (W/L)6/(W/L)8 respectively, andA B m2 2.0!8u=

Acording to the analysis above, we find that the resistor 2.096utempco becomes a lovely thing, but not a boring monster.

.0

11 , .,I. i.. iIV. SIMULATION RESULTS AND COMPARISON -50 0 50 100

The circuit is simulated with HSPICE and 0.6 pim Temperature [lin] (DEG_]standard CMOS process model is used in the simulation. Fig.7 Simulated current IREF against temperature

Fig.5 and Fig.6 show the temperature dependence ofAlrefl through M5 and BJrefl through M6 at 1.8V supply,respectively. Fig.7 demonstrates the efficiency of the highorder temperature compensation scheme, the achievedtemperature coefficient of IREF is 31 ppm/ C in thetemperature range of (-50°C, 100°C)

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2u -

1.5u -

1u -

500n -

0O

1 1.2 1.4 1.6 1.8Voltage X (lin) (OLTS)

-110

-120

0 -130

u -140.

-150

-l 602 2.2 2.4

Fig.8 Simulated current IEF against power supply

From Fig.8, it is clear that the minimum supply voltageis about 1.8V, this is because the rail current source offolded-cascode goes to triode region as supply voltagebelow 1.8 V. Nevertheless, the current changes very littlewith supply voltage, thus showing superior supplyregulation, which is better than that achieved by thetraditional cascode connection or source degeneration.Further reduction on minimum supply voltage can beobtained by using processes with lower threshold voltage or

low voltage amplifier such as bulk-driven amplifier.

10 100 1k lOk lOOk lxFrequency (log) (HERTZ)

lOx 1 OOx

Fig.9 Simulated PSR ofthe proposed current reference

Fig.9 gives the simulated PSR at 1.8V supply without a

filtering capacitor. The PSR at I0 KHz is about -158 dB andincreases to -120 dB at 1 MHz. Thus the circuit showssuperior power supply rejection for adopting folded-cascodeamplifier. And at high frequencies, the PSR can be wellimproved by adding a filtering capacitor at the gate of M7.

The comparison in Tab.1 shows the proposed circuitachieves better tempco with extending temperatureoperating range and improved line regulation.

TABLE 1Comparison of Simulation Results Current References

Sansen['0] Lee[i"] Deval[41 Badillol3] Chen[21 Fabre 121 This workMln.VDD 3.5V -3V -IV _I.5V -IV -1.4V -I.8V

Tempco (ppm/°C) 375 226 53 368 50 65 31Line regulation (/V) 0.015% - 3% - 0.5% - -0.01%

PSR - - - - - - -158dB

Temperature range (°C) 0 80 0-75 -40 150 0-100 -50-100Process Bipolar CMOS Bipolar CMOS CMOS Bipolar CMOS

V. CONCLUSION

A new high order temperature compensated currentreference is presented in this paper. Its compensation principleis discussed and computer simulations verify the very lowtemperature drift. The layout of prototypes will be underprogress to acquire measured results, and then trimmingtechniques may be necessary to guarantee the good temperaturecharacteristic in practice for the corner of process.

REFERENCES

[1] Y. Deval, S.G. Ducouret, J.P. Dom, "Ratiometric temperature independentcurrent reference", Electronics Letters, Vol.29, No.14, pp.1284-1285, 1993.

[2] Chen J, Shi B, "1 V CMOS current reference with 50 ppmHspl deg/Ctemperature coefficient", Electronics Letters, 2003, Vol.39, No.2, pp.209-210, 2003.

[3] D.A. Badillo, "1.5V CMOS Current Reference with ExtendedTemperature Operating Range", ISCAS, Arizona, USA, Vol.3, pp: 197-200, 2002.

[4] Y. Deval, J. Tomas, J.B. Begueret, et al. "1-Volt Ratiometric TemperatureStable Current Reference", ISCAS, Hong Kong, pp. 1984-1987, 1997.

[5] E.A. Vittoz, 0. Neyroud, "A low-voltage CMOS bandgap reference",IEEE Journal of Solid-State Circuits,Vol. 14, No.3, pp.573-579, 1979.

[6] C. Popa, "DTMOST low-voltage reference circuit with logarithmiccurvature-correction", International Semiconductor Conference, Sinaia,Romania, Vol.2, pp.353-356, 2003.

[7] G. Giustolisi, G. Palumbo, "Detailed Frequency Analysis of Power SupplyRejection in Brokaw Bandgap", ISCAS, Sydney, Australia, Vol.1, pp.731-734, 2001.

[8] W.A. Lane, G.T. Wrixon, "The design of thin film polysilicon resistors foranalog IC applications", IEEE Transactions on Electron Devices, Vol.36,No4, pp.738-744, 1989.

[9] D.W. Lee, T.M. Roh, H.S.Park, et al. "Fabrication technology ofpolysilicon resistors using novel mixed process for analog CMOSapplications", Electronic Letters, Vol.35, No.7, pp.603-604, 1999.

[10] W.M. Sansen, "A CMOS temperature-compensated current reference",IEEE Journal of Solid-State Circuits, Vol.23, No.3, pp.821-824, 1988.

[ 11] C.H. Lee, "All-CMOS temperature independent current reference",Electronics Letters, Vol.32, No. 14, pp. 1280-1281, 1996.

[12] A. Fabre, M. Alami, B. Alaoui, "Two new temperature compensatedcurrent sources", IEEE Trans Cir&Syst, Vol.44, No.1 1,pp. 1071-107, 1997.

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