Low Power and High Speed Sample-and-Hold Circuit

Ronak TrivediDhirubhai Ambani Institute of Information and Communication Technology

Gandhinagar, INDIA.E-mail: ronak_trivedi gda-iict.org

Abstract-This paper describes the improved sample-and-hold architecture as a front-end block of low powerand high speed pipelined analog to digital converter. Thecircuit consists of bottom-plate sampling withdifferential architecture of OTA (OperationalTransconductance Amplifier). The sample-and-holdcircuit has been laid out in 0.18pm CMOS technologyand simulated using MOSIS CMOS BSIM3v3.1 SPICEparameters. The measurement result shows that theSFDR of 64.5dB is achieved up to the samplingfrequency of lOOMS/s for input signal amplitude of1.2Vpp.The sample-and-hold circuit consumes 6.5mWfrom a 1.8volt supply.

where the sample-and-hold circuit allows the voltagecomparison of the signal. At this point, the continuous-timesignal is converted to discrete time. The use of sample andhold circuit allows most dynamic errors of ADC's to bereduced especially those occurring with high frequency inputsignals. So the S/H must exhibit the better performance thanthe ADC in terms of accuracy, speed and power dissipation.

In this paper the design and implementation of modifiedswitch capacitor based sample and hold circuit has beendescribed. The main application of this sample-and-holdcircuit is in the low power and high speed pipelined ADCs.It has been designed in a 0. 18ptm CMOS process, whichallows only a maximum supply voltage of 1 .8volt.

I. INTRODUCTION

With the explosive growth of wireless communicationsystem and portable devices, the power reduction ofintegrated circuits has become a major problem. An examplefor low power application is a wireless communicationsystem. With the rapid growth of internet and information-on-demand, handheld wireless terminals are becomingincreasingly popular. (i.e. UPS and handheld pad for packagedelivery.) With limited energy in a reasonable size battery,minimum power dissipation in integrated circuit isnecessary. Many of the communication systems today utilizedigital signal processing (DSP) to resolve the transmittedinformation. Therefore, an analog-to-digital interface isnecessary, between the received analog signal and DSPsystem. This interface achieves the digitization of receivedwaveform subject to a sampling rate requirement of thesystem. Being a part of communication system as mentionedabove, the analog to digital interface also needs to adhere tothe low power constraint. Typically, pipelined analog todigital converters are used for the application requires highspeed and low power [1].

The sample and hold block is typically used as suchanalog to digital interface in front of ADC. The operationcycle of sample-and-hold block is divided into two phases:the sampling phase and the hold phase. In the samplingphase, the analog signal is sampled, where the sample-and-hold circuit works just as a buffer. In the holding phase, thesampled signal is kept fixed until the next sampling phase,

II. S/H ARCHITECTUREA simple close loop switch capacitor sample-and-hold

architecture [2] is shown in Fig. 1. Here 01 is delayedversion of 03, and 02 is the inverse of 03. Thus it consistsbottom-plate sampling [3] to eliminate the signal dependentclock-feed through effect and hence reduces the harmonicdistortion significantly. During the sample phase (01),capacitor Cs is connected between signal source and op-amp's input, which is connected to the corresponding output.Thus, Cs is charged to (V111-Vos), where Vos is the outputcommon-mode level. In the following hold phase (02) Cs isconnected to op-amp in feedback and output differentialvoltage becomes V11, eliminating any op-amp offset voltage.

S2

vout

Fig. 1 Switch-capacitor based sample-and-hold circuit.

1-4244-0173-9/06/$20.00 ©2006 IEEE.453

A disadvantage with the above architecture is that theoutput voltage varies considerably between sample and holdphases, since the differential output of op-amp is set to zeroin every sample phase. So for high-speed application the op-amp's slew-rate should be larger which increases the powerdissipation considerably. Also op-amp remains in closed-loop for both phases. To solve these problems, thearchitecture has been modified as shown in Fig. 2. In thisarchitecture the op-amp remains in open-loop configurationduring the sampling phase. So op-amp has not to settle downwhen switching from hold phase to sampling phase. Also thefalling edge of switch SI is delayed than S2 so that glitch atthe differential output can be significantly reduced whenswitching from sampling mode to hold mode.

Si S2

VI -0 -

Vref '

L2

VI-

(J)

Sil S;2

1)4:

Fig. 2. Switch-capacitor sample-and-hold circuit withmodified clock sequences.

The speed of S/H block mainly depends on the timeconstant in the sampling and hold phase. During thesampling phase the time constant is given by,

is = (Ronl + Ron2) * Cs (1)Where, ROnl and ROn2 are the equivalent resistances of

switch S1 and S2 respectively. During the hold mode settlingtime constant of feedback amplifier is given by,

CLCIN + CLCS + CSCINGmCH (2)

Where, Cs CsI, S2, CL = CLI, L2, Gm is thetransconductance of op-amp and Cm, is the op-amp's inputcapacitance. For 10-bit accuracy the required settling time isapproximately given by 7*,h.

Thus the sampling speed is limited by low value of Cs(Equation 1) and input signal bandwidth is limited by highvalue of Cs (Equation 2). Also the sampling noise (KT/C)depends on the size of sampling capacitor (Cs). Since this

design is to be implemented in 0.18ptm CMOS technologythe trade-off between signal-to-noise ratio and speed is verycrucial. The switch can be realized as simple MOStransistor, transmission gate or bootstrapped [3] type. Forlow distortion at given power consumption the switches oftransmission gate are used in this architecture. Since themaximum supply voltage is 1.8volt the maximum swing atsingle end is taken as 600mV[4]. With this output swing theminimum value of sampling capacitor (Cs) is approximatelyl.lpf for signal-to-noise ratio of greater than 65dB. Themaximum value of load capacitance (input of pipelinedADC) is assumed as 1.5pf.

III. OPAMP DESIGNThe design of fully differential op-amp is critical in the

above architecture since it should meet the requiredspecifications such as open loop gain, slew rate, unity gainfrequency, common mode gain, output differential swing andinput common mode range. Now for 10-bit of accuracy thegain error of op-amp should be less than +/- 1/2 LSB. If theinput capacitance of op-amp is assumed to be less than 0.5pfthen value of feedback factor (D) will not be less than 0.75.This requires the open loop gain (AO) of op-amp should begreater than 68dB.

Now for maximum sampling frequency of 100MS/s theavailable slewing time is 1.25ns and small signal settlingtime is 3.75ns according to the rule of thumb [5]. So therequired slew-rate (differential) is 240volt/s. For the linearsettling time of 3.75ns the transconductance (Gm) of op-ampshould be greater than 4.35mS. In the hold mode when op-amp undergoes linear settling the required unity gainfrequency is given by,

GBWhold = Gm/CL, total (3)

Where, CL, total = total load capacitance in hold mode= CL + (Cin 11 CS).

With above equations the minimum value of GBWhold is381MHz at lOOMS/s. The architecture of op-amp can be oftelescopic cascode, two-stage, regulated cascode or foldedcascode type. Two stage amplifier can give higher gain andoutput swing but at the cost of low speed and higher powerconsumption. Telescopic amplifier can give high gain andspeed at the cost of lower output swing. Regulated cascodecan have larger power consumption. So the final choice isfolded cascode amplifier, which can give larger swing thantelescopic amplifier for a given open-loop gain. Also thelinearity of folded cascode is better than that of other types.The topology of selected op-amp is shown in Fig.3. Thegain boosters have been added to enhance the overall gain.The gain-boosters are of simple common source type so thatthe unity gain bandwidth of op-amp should not be affected.The common-mode feedback used is very simple and fast.The simulation results of op-amp are summarized in table. 1

454

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I a'Z

(a)

It

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Fig. 3. Schematic of folded cascode amplifier with gainboosters and common-mode feedback.

TABLE 1Simulated results ofOTA

Parameter Hold phaseDC gain 70dBGain bandwidth 390MHzPhase margin 75degreeSlew rate (differential) 340volt/secOutput swing 0.6volt

(b)

Fig. 4. Spectrum of output signal from switch when(a) Wp/W1=3 and (b) Wp/W1= 6.

CL>YK - BUFFERS

IV. SWITCH AND CLOCK-GENERATOR DESIGN

The switches are of transmission gate type instead ofsimple MOS transistor type since SFDR (spurious freedynamic range) of transmission gate is larger than a singleMOS transistor. The size ofPMOS and NMOS is chosen soas to reduce the harmonic distortion. The large ratio ofwidth ofPMOS to NMOS can give high SFDR as shown inFig.4. But after a certain ratio the SFDR doesn't changesignificantly with increase in size of PMOS compared toNMOS [4].

A clock generator follows the clock driver as shown inFig.5. The clock driver contains the buffer chain to drive theinput capacitance of clock generator. The delay of OR gateis kept as the delay of two inverters so as to obtain theappropriate clock sequence as shown in Fig. 2. Since thefully differential structure is used the non-overlapping clocksignals are not required.

Fig. 5. Clock generator

V. SIMULATION RESULTSThe circuit for sample and hold is simulated with foundryBSIM 3v3. 1 SPICE parameters. The results are summarizedin table 2. The comparison with the previous work issummarized in table 3. The frequency response of sampleand hold circuit with input signal frequency of 2MHz andsampling frequency of 100MHz is shown in Fig.6.

TABLE 2Simulation results of sample and hold circuit

Supply Voltage 1 .8voltPower consumption 6.5mWSFDR (Fin = 2MHz, Fs = 100 MS/s) 64.5dBFull scale input range (peak-to-peak) 1.2voltENOB (effective number of bits) 10

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TABLE 3Comparison of different sample and hold architectures

Reference Sample Bits Swing Power Tech.Rate (volt) (mW) (pm)(MS/s)

[6] 103 10 2.84 16 0.8[7] 220 10 3.6 25 0.5[8] 1100 112 12 j33 10.25This work 100 110 11.2 16.5 [0.18

40dB`sFDR=645d

F9/- 50 MHz

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Fig. 6. Spectrum of output signalcircuit

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from sample-and-hold

REFERENCES[1] R. H. Walden, "Analog-to-Digital Converter Survey and

Analysis," IEEE Journal Selected Areas inCommunication, vol. 17, pp. 539--550, Apr. 1999.

[2] B. Razavi, "Design of Analog CMOS IntegratedCircuits," McGraw-Hill Higher Education, 2001, ISBN0-07-238032-2.

[3] Z. Tao, M. Keramat, "A Low-Voltage, High-PrecisionSample-and-circuit," Symposium on Microelectronicsand Optoelectronics, 2001.

[4] E. Sall, AB Acreo, "A 1.8 V 10-bit 80 MS/s low powertrack-and-hold circuit in a 0.18 /spl mu/m CMOSprocess," Proceedings of IEEE InternationalSymposium on Circuits and Systems, 2003.

[5] S. Brigati, F. Maloberti and G. Torelli, "A CMOSSample&Hold for High-speed ADC's," IEEE Circuitsand Systems, vol. I, pp. 163-166, 1996.

[6] K. Hadidi, et.al, "An Open-Loop Full CMOS 103-MHz41-dB THD S/H Circuit," in Proceedings of IEEECustom integrated Circuits Conference, pp.381-3, 1998.

[7] M. Waltari, K. Halonen, "10-bit 220-MSample/sCMOS sample-and-hold circuit," in Proceedings ofIEEE International. Symposium on Circuits & Systems,pp. 253 -256, 1998.

[8] C. Hsu, et.al, "33-mW 12-bit 100 MHz sample-and-hold amplifier," in Proceedings of IEEE Asia-PacificConference on ASIC, pp.169-112, 2002.

Typically, the figure ofmerit for sample and hold circuit isgiven by [1],

FOM = PowerN * f

(4)

Where, N is effective number of bits and fs is the samplingfrequency. This work achieves approximately twice theimprovement in the figure of merit as compared to otherarchitectures as shown in Table: 3.

VI. CONCLUSIONIn this paper the design of switch capacitor based

sample and hold circuit for pipelined ADC has beenreported. The design has been implemented in 0.18ptmCMOS technology with BSIM 3v3.1 SPICE parameters.This achieves the SFDR of 64.5dB at the samplingfrequency of lOOMS/s and consumes the power of 6.5mWfrom 1.8volt supply. Using bootstrapped switches andmodifying the op-amp architecture can further increase theinput dynamic range and SFDR.

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