Impact of Process Induced Variability in NWFETS

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Abstract—This paper examines the impact of fabrication process induced variability’s on the Nano-wire Field Effect transistors (NWFET). The continuous scaling of devices to get high speed high performance has reached the atomistic levels, where a slight variation in surface, thickness or defects in layers structure or lattice causes large variation in the device performance. The review assesses the recent techniques and models to account for these variability’s in NWFETs and short analysis of variation sources and variability impact on device performance is presented.

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I. INTRODUCTION

With the continuous scaling of the CMOS process, variability’s arising from process variations are becoming complex and dominating the device behavior. FinFET structure introduced for better scalability in comparison to planar and thin-body structure [1]-[3]. Gate controllability is improved in GAA structures. High performance Si GAA nanowire devices have been demonstrated and its operation is studied [4]-[9]. A novel top-down fabrication technology has been developed and sub-50nm InGaAs GAA nanowire MOSFETs has been demonstrated [11], [12]. Scaling nanowire devices further improves the device performance [13] but scaling beyond 10nm brings in new process dependent variations which limit the mobility and threshold voltage of the NWFETs thus limiting the performance of the NWFETs [14], [15], since the carrier transport is determined by the ballistic / semi ballistic transport and scattering is dominated by remote coulomb scattering and surface scattering.

In this paper, we will be discussing briefly about the top-down and bottom-up approaches for NWFET fabrication process followed by the different sources of variation due to the various process steps. We will be presenting the overview of various variability and change in their behavior as technology scales down. Later we will be discussing the impact of variability’s due to RDF, LER, nanowire dimensions and metal gate work function differences on the NWFET in terms on Vth and mobility and there trend with the technology scaling. In later, sections recent modeling techniques to model the

variability’s are discussed. Then, the recent proposals are reviewed and assessed in light of their approach to mitigate the variability impact. Finally, discussing the impact of variability’s on SNM of 6T SRAM cell is discussed..

II. FABRICATION

There are two main approaches for nanowire fabrication: top down approach and bottom up approach. The top down approach starts with bulk materials and perform reduction in material dimension using various techniques like cut, pattern, etch, and shape these materials to get desired geometry [16]. Fig. 1 shows the schematic representation of fabrication process of silicon nanowire arrays on SOI substrate [17]. The main source of variation lie in the nanowire channel formation, which mainly includes the initial fin patterning, etching and nanowire size reduction. Furthermore, to control the shape rounding as well as surface damage removal, sacrificial self-limiting oxidation and H2 annealing is carried out [18].

Fig. 1. Fabrication steps of SNW on SOI Substrate.

The bottom-up approach involves preparing of nanowire FET from molecular precursors, rather than starting with bulk material. Vapor-Liquid-Solid (VPS) is a mechanism which can be used for growth of one dimension structures like nanowire FET. It can produce high quality NWs but it suffers

from the drawback that the NWs grow with random orientation on the substrate. Also it has limitations such as i) complex integration, ii) requiring transfer to substrates, iii) difficulties in positioning individual nano structure, iv) making reliable ohmic contacts.

III. PROCESS INDUCED VARIABILITY’S

In previous section we discussed about the steps like lithography, etching and deposition which are the main sources of variation in the NWFETs. In this section we will discuss about the various variations caused by these steps namely LER, RDF, work function difference in detail.

A. LER

LER is described as a random variation in gate length of a MOS along the direction of gate width. LER does not significantly affect the MOS parameter up to 90nm technology because the dimensions of the MOSFET are larger in comparison with roughness (typically 5nm), but it is dominant when we go below 32nm technology [19], [20]. The major impacts of LER on device performance include Ion degradation, Ioff increment, Vth variation. The main sources of LER are photolithography and etching steps during fabrication of a device.

The LER mainly generates from the inescapable difference between designed line patterns and the geometries after the process of lithography and etching. So, in nanowire fabrication the impact of nanowire fin patterning process and the nanowire size reduction process is more in LER [18]. In Nanowire FET, the impact of LER on its performance is more complicated as both the nanowire diameter and its curvature is varied along the wire. So, LER can be divided in two types a) Type A In this, the centre of nanowire is aligned but the diameter is varied along the length and b) Type B It has fixed diameters but the centre of nanowire is varied as shown in Fig. 2.

Fig. 2. Type A and Type B LER.

The impact on the variability of the nanowire FET is more due to type A LER. As Vth of nanowire is more sensitive to nanowire diameter, therefore variation in Vth is more due to type A as compare to type B [18]. Fig. 3 shows the histogram of Vth of 400 samples which clearly indicate that the standard deviation in type A LER is almost seven times that of by type B. On the other hand, due to misaligned concentration centroids in type B, there is an irregular carrier distribution which resulted in a degradation of mean value of the drive current which is due to scattering of the carriers at the nanowire surface.

The impact on the variability of the nanowire FET is more due to type A LER. As Vth of nanowire is more sensitive to nanowire diameter, therefore variation in Vth is more due to type A as compare to type B [18]. Fig. 3 shows the histogram of Vth of 400 samples which clearly indicate that the standard deviation in type A LER is almost seven times that of by type B. On the other hand, due to misaligned concentration centroids in type B, there is an irregular carrier distribution which resulted in a degradation of mean value of the drive current which is due to scattering of the carriers at the nanowire surface.

Fig. 3. Distribution of the Vth of of SNWTs due to two types of LER under Λ/Lg

= 0.2 fit well with Gaussian distribution.

The main LER parameters are correlation length (^) and root mean square of edge (∆). Correlation length is the average distance between the adjacent peaks or valleys on the same side of edge. It indicate the spatial frequency characteristics of the LER i.e. high frequency LER is indicated by low ^ value. The root mean square of edge indicates the amplitude of the LER i.e. the performance of nanowire FET is proportional to the ∆. The impact of LER on the performance variation and the mean value degradation in nanowire FET can be investigated using these two LER parameters. The Fig. 4 (a) and (b) shows the impact of ^ and ∆ variation on Ion current. As it can be seen from the Fig. 4 that the Ion degrades up to 5% in both type A and type B as ^ reduces while it is almost constant in the case of ^ > Lg. So, it can be concluded that correlation length has negligible impact on the performance variation in case ^ > Lg. But in case of ∆ reduction Ion is almost constant in both types of LER. As shown in Fig. 3 (c) the Vth variation is increased as the value of ∆ increases for ^/Lg<1. So, it can be concluded from above analysis that with decrease in ^, the performance degradation occur however it does not affect the performance parameter variation when it becomes larger than the gate length. On the other hand ∆ induced the parameter variation whereas the performance degradation is insensitive to ∆.

B. RDF

As we are moving towards smaller dimensions we are facing challenges to control increased leakage in devices. This increase in leakage can be countered by reducing bulk concentration. Decrease in number of dopants leads to another source of variation, RDF [21], [22]. As the number of dopants is now very few, any variation in dopant concentration will impact device properties. During the fabrication processes like ion implantation or even before that the defect in the substrate itself changes the dopant profile. This undesired impurity causes the variation in device characteristic which are critical at smaller dimensions.

Fig. 4. Mean value of Ion as function of (a) ^ (b) ∆ (c) Box plot of V th

distribution as a function of ∆

Fig. 5. Source-Drain Extension region [21]

3In case of nanowires the channel is completely undoped and there is no RDF effects expected in gate channel region. But in nanowires, due to variation of S/D implants and annealing there can be variation in doping of S/D. The impurities from source/drain diffuses to channel region forming the source drain extension region (SDE) shown in Fig. 5, due to this region being formed there are introduction of extra parasitic [23].

IV. IMPACT OF VARIATION IN DEVICE PARAMETERS

The device parameters can be sub divided in following categories: i) Nano wire diameter, ii) Gate oxide thickness (EOT), iii) Gate/ Nano wire length, iv) Doping levels and v) Junction abruptness.

The cause and impact of variations of these parameters on device performance will be analyzed in following section.The 2D structure of a NWFET is given by Fig. 7, the nano-wire is surrounded by oxide on all sides. The effective oxide thickness is represented as EOT. Fig. 8 captures the various variations that can arise due to process variation like non-uniform nano-wire diameter, spacing between nano-wires and non-perpendicular nano-wires structures with respect to S/D. Some of these effects can be seen in TEM micrographs in Fig. 9 [24].

Fig. 6. Impact of variation in (a) Lg on Vth and (b) Lg on Ids

.

Fig. 7. 2D structure of NWFET

With the decrease in the dimension, the surface effects are becoming dominant than the bulk effects. Slight variation in the surface of NW causes scattering which in turn degrades the mobility of charges in NW [14]. While with the decrease in oxide thickness causes the traps captured in oxide to come close to channel and causes remote coulomb scattering (RCS) [15].

(1)

A. Impact of nanowire diameter

In NWFET’s, channel is covered by gate on all sides, thus giving a better gate control. Thus, as the NW diameter decreases Ion increases due to volume inversion. But as the NW diameter decreases beyond 10nm, Ion decreases due to increased impact of surface roughness on the mobility of the NWFET. Since, electrons are more likely to scatter at surface thus degrading the mobility [14]. The Fig. 10 presents the variation of Vth and Ion with respect to the nano-wire diameter scaling [24].

Fig. 8. Sources of variations in NWFET [13].

Fig. 9. TEM micrographs of the channel cross-section showing 3 to 6 nm thick SiNW surrounded by 4 nm oxide followed by poly silicon. TEM is done after full process. (a) 3 nm, (b) 4 nm, (c) 5 nm, and (d) 6 nm [24].

B. Impact of EOT

Keeping drain and gate biases constant Ion is directly proportional to Cox (gate oxide capacitance), while Cox is inversely proportional to tox (gate oxide thickness). Thus, as tox

decreases Ion should increase, but if EOT (tox) decreases below 2nm Ion starts decreasing due to increased remote coulomb scattering.

(2)

where SS sub threshold slope and Dit is interface trap charge density .The above equation gives that impact of EOT scaling on SS. It’s clear that as EOT decreases, Cox increases thus reducing the impact of interface trap charges on sub threshold slope. Fig 11 shows the impact of EOT scaling on the Ion and sub-threshold slope [15].

Fig. 10. Effect of diameter on Vth and Ion for NMOS. ∆Vth/∆D = 35 mV/nm. Ion is insensitive to diameter

Fig. 11. Impact of EOT scaling on Ion and SS [15].

C. Impact of channel length scaling

Ion is inversely proportional to channel length. Scaling down channel length helps to increase the Ion of the device, but beyond sub-100nm [14] the Ion increases very slowly due to the velocity saturation at high electric fields. Below 10nm the device Ion is dominated by the ballistic behavior and Ion is decided by the contact resistances of the device. Fig. 12 shows

the impact on SS and Ion with respect to EOT and channel length [14].

Fig. 12. Impact of channel length scaling on Vth and SS [14]

D. Impact on mobility

The effective relaxation time including the scattering mechanisms can be defined as below:-

(3)Where ph is phonon scattering, SR is Surface roughness, RCS is remote coulomb scattering due to the non-perfect quality of process which traps charges in the gate oxide [15].Fig. 13 captures the mobility variation with electron density for different nanowire diameters.

Fig. 13. Electron mobility versus the electron density for different nanowire diameters [15]

V. METAL GATE WORK FUNCTION VARIABILITY

Metal – gate work function variability is one of the major sources of variability in Nano-scale devices.

To control high gate leakage HKMG (high K metal gates) were introduced, which have various advantages over the poly-Si gate i) Low gate resistance, ii) Reduced gate depletion, iii) Prevention of Boron penetration from gate into channel, iv) Reduced gate leakage. But it has its drawbacks too. As metal gate has granular nature with different variety of grains, these grains vary in there orientation and size which depends on grow th processes and temperature of growth [26]. This variation in orientation leads to variation in the work function. For example: Titanium Nitride (TiN) present in different orientations like <111><200><220> with the work functions varying between 3.7eV-4.3eV, this lead to variation in threshold voltage of the device [25]. Fig. 14 shows some of the possible orientations of grains.

Fig. 14. Possible grain orientations [25]

Fig. 15. Graph shows varying drain current with gate voltage at different grain orientations.

With the above possibilities the characteristics of device at different grain orientation is shown in Fig. 15.

VI. IMPACT OF VARIABILITY’S ON NWFETS

In last section we discussed about the various process variability’s. In this section we will be discussing briefly about their impact on the NWFET performance. The NWFET because of their inherent design, prove a lot useful in controlling the second order effects of the planar CMOS devices. The volume inversion in NWFET’s providing much better control of gate on channel. With several advantages the scaling continues further. But for technologies below 20nm NWFETs also encounters process variability’s which limits their performance. The LER, EOT and reduced nanowire diameter brings the impurities close to the channel, which increases the scattering mechanism. The mobility is not only limited by phonon scattering, but surface scattering and remote coulomb scattering also starts dominating, there impact will dominate and further decrease the mobility as we go below 10nm.The RDF and nanowire length scaling impacts the Vth of the nanowire devices thus limiting the NWFET performance. The channel is fully depleted in case of NWFET therefore it should be independent of RDF, but due to diffusion of charges from source and drain regions (SDE) causes the RDF whose impact increases as the channel length is further scaled down. The LER and nanowire diameter also impacts the V th of the NWFETs due to the fluctuations caused by them in the channel diameter because of process variations, this impact further worsens as the technology is scaled down. Metal gate work function difference impacts the Vth of the NWFETs, the metal gate has granular nature with different variety of grains, which vary in there orientation and size depending on growth processes and temperatures. These variation in orientation leads to variation in work-function which causes variations in Vth of the device. The NWFET gave better performance than conventional MOSFETs with technology scaling, but beyond 20nm the mobility of the devices gets limited by the ballistic transport effect. The behavior of the device becomes more statistical.

VII. SHORT DISCUSSION ON RECENT TECHNIQUES AND MODELS

The NWFET have proved a good alternative to counter the exponentially increasing second order effects of CMOS devices, but beyond a point the NWFETs are affected by the increasing variability’s due to the subatomic dimensions of the nano-wire devices. These variability’s and their impact on NWFET were discussed briefly. So, there comes the need to understand the physics behind these variability’s and model them in the device models. In this section we will be discussing about some of the recent studies on modeling of these variability’s. With device size the various available modeling techniques is shown in Table 1. There are different works available which have modeled RCS, LER and RDF through different models like NEGF, monte-carlo simulation. The Fig. 16 shows the statistical

behavior of NWFETs drain current with different nanowire diameter.

TABLE 1 Showing transportation phenomenon at different nodes

Fig. 16. Id behavior with nanowire diameter of 10nm and 45nm [23].

The Fig. 17 shows the impact of various sources of variability’s on NWFET Ion and Vth.

RCS is modeled using the Kubo-Greenwood approach to solve the poission's equation, considering local charge in the oxide [15].

Drift-diffusion and Monte-carlo (quasi classical) models loose the predictive capability at sub 10nm channel length

because of the high degree of ballisticity and onset of source to drain tunneling. As a result fully three dimensional (3D) quantum transport simulations should be carried out when dealing with variability in nanowire transistors due to discrete charges and interface roughness. But these simulations are very computationally expensive when using.

Fig. 17. Impact of various sources of variability’s on NWFET Ion and Vth [23].

Fig. 18. Impact of RCS on mobility [15].

Non-Equilibrium Green's function (NEGF) algorithm which is favored when considering scattering mechanism in simulation [28].

VIII. TECHNIQUES OR METHODS TO REDUCE VARIABILITY IN NANOWIRE FINFET

Variability is an increasing perturbing problem as the size of the device continues to scale. The effect of variability causes a significant deviation from the prescribed performance specifications in nanometer-scale integrated circuits. So in continuing to scale down the technology, it becomes necessary to deal with this variability impact. Some of the methods or

techniques that are being used to reduce the impact of variability are:

A. Patterning Techniques

Advanced lithography techniques can be used to reduce the roughness of line edges. Double-patterning and double-etching (2P2E) technique is used to reduce the random variation (especially the LER) of multigate Mosfet. As, already explained earlier LER-induced Vth variation in multigate devices would increase with decreasing correlation length [29]. Hence, 2P2E giving longer correlation length would be beneficial to suppress the LER-induced Vth variation. It was reported that the LER-induced Vth variation by the 2P2E technique was suppressed by ∼ 20% in terms of σ(Vth) as compared to 1P1E technique [30].

B. III-V materials

As it is known, that III–V multigate MOSFETs due to higher mobility with better control of gate on channel are promising candidates for the 14-nm technology node and beyond [31]. Moreover, it was reported recently that III–V non-planar transistors may be potentially more resilient to variability than the corresponding Si devices for the 22-nm technology node [32]. Due to the lower effective mass system of In0.53Ga0.47 than Si, it has higher quantum confinement effect. The electron density is much better confined in the channel of InGaAs FinFET than in Si devices which reduce the impact of variability. Also, it was reported that variability due to the RDF and LER is comparable or smaller for the 14-nm technology node in InGaAs FinFETs as compare to corresponding Si devices [33].

C. Passivation techniques

The remote coulomb scattering affecting mobility in NWFETs is due to the presence of the interface trapped charges in the oxide. The charges act as traps and can get either positively or negatively charged by either trapping a hole or electron. The traps are due to some type of incompletely oxidized silicon atom with unsatisfied or dangling bonds located in the oxide, they lie very close to the interface [34]. These charges have been found to get passivized by the hydrogen annealing at the low temperatures (300-500C). Passivation means bonding the incompletely oxidized silicon atoms with

hydrogen atoms, so that they are no longer electrically active and traps carriers. Since the step is done at low temperature, which can be sustained by the metal layers, therefore this step is normally done at the end of chip fabrication process. Polysilicon gates prevent the out-diffusion of hydrogen atoms therefore can sustain larger temperatures.

The Aluminum can be used to passivate the surfaces without the need of external hydrogen. The cleaning process leaves behind traces of water which provides the OH ions which react with Al to generate hydrogen atoms [34].

The fixed charges are normally passivated by high temperature annealing at high temperatures in nitrogen or argon ambient. Argon provides better passivation but is expensive [34]. The impact of Al2O3 passivation has been studied for InGaAs NWFET to improve the interface and variability [35].

IX. IMPACT OF PROCESS VARIABILITY’S ON SRAM PERFORMANCE

SNWT are extensively investigated as the substitute in SRAM memories for low voltage operations. There are other devices like planar Finfets and Omega FinFETs which are extensively used in SRAM memories for below 20nm node. In this section we will focus on nanowire SRAMs and will emphasize on the performance impact due to variation in nanowires. We will present a comparative study of how the impact of variation in case of nanowires stands with respect to planar SRAMs [37].

We will first look at major figure of merit for a 6T SRAM as shown in Fig. 19. So for accurate read/write operations we will consider SNM (read & write) as a comparative study parameter. We will look at how the process variation impact SNM of the cell.

Fig. 19. SRAM 6T Cell [37].

Fig. 20. Noise Margin Comparison among different devices [37].

From the butterfly curve, Fig. 20 shows that among the three the FinFETs performs best in terms on SNM. Now we will look at how the SNM for read and write varies with reducing supply in all three variants.

The Fig. 21 shows that nanowires performs best in both read and write operation as we scale down in supply. It is considered as a good alternative in low voltage operations. As we scale down in length the variations in SRAM are more impacting as in case of FinFETs. Fig. 22 presents a graph between length and SNM sigma shows that FinFETs are better in terms of variation immunity [37].

Fig. 21. SNM with varying supply.

Fig. 22. SNM Sigma variation comparison among different devices [37].

As discussed the change in device geometry, there are very evident impact on device performance below 10nm node. In case of nanowire SRAM the most impacting variability arise due to i) Diameter variation, ii) Wire LER.[38]. As diameter variation and LER impacts the device current and hence impacts the SNM of device and cell

Fig. 23 shows that how the diameter variation impacts the Id

of the device taking 200 samples on the scale of gate voltage at fixed Vd. Again due to variation in Id the static noise margin of a 6T cell will also be impacted and there can be some outliers which will fail. Fig. 24 shows that the variation due to diameter

of wire will make some outliers samples to fail i.e. there is no noise margin for them , the graph shown has VTC curve at Vdd=300mV.

Fig. 23. Wire LER impact on Id [38].

Fig. 24. VTC curve for 6T SRAM cell showing impact of diameter variation.

Fig. 25. VTC curve for 6T SRAM cell showing impact of Wire LER [38].

Fig. 25 shows how wire LER impact the SNM at 300mv Vdd for a 10nm nanowire; it shows the impact of LER variability’s are not that severe as of diameter variability in this case. In general, the variability in nanowire geometry impacts

the noise margins, Vth and on currents which in turn impacts the SRAM memory cell performance and reliability.

I. REFERENCES

[1] Y. Lee, "Modeling and Simulation of Nanowire MOSFETs.," PhD thesis, TOKYO INSTITUTE OF TECHNOLOGY, 2012.

[2] A. Martinez, A. Brown, A. Asenov, and N. Seoane, "A comparison between a fully-3D real-space versus coupled mode-space NEGF in the study of variability in gate-all-around Si nanowire MOSFET," in Proc. SISPAD, San Jose, CA, 2009, pp. 194-197.

[3] K. Patel, T.-J. King, and C. J. Spanos, "Gate line edge roughness model for estimation of FinFET performance variability," IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 3055-3063, Dec. 2009..

[4] C. Shin and I. J. Park, "Impact of using double-patterning versus single-patterning on threshold voltage (VTH) variation in quasi-planar tri-gate bulk MOSFETs," IEEE Electron Device Lett., Vol 34, No. 5, pp. 578-580, May 2013.

[5] M. Bohr, "The evolution of scaling from the homogeneous era to the heterogeneous era," In IEDM Tech. Dig., Dec. 2011, pp. 1-6.

[6] N. Agrawal, Y. Kimura, R. Arghavani, and S. Datta, "Impact of transistor architecture (bulk planar, trigate on bulk, ultrathin-body planar SOI) and material (silicon or III--V semiconductor) on variation for logic and SRAM applications," IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3298-3304, Oct. 2013.

[7] N. Seoane, G. Indalecio, E. Comesaña, M. Aldegunde, A. J. García-Loureiro, and K. Kalna, "Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs FinFET," IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 466-472, Feb. 2013.

[8] J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology-Fundamentals Practice and Modeling. Englewood Cliffs, NJ: Prentice-Hall, 2000.

[9] J. J. Gu, X. Wang, H. Wu, R. G. Gordon, and P. D. Ye, "Variability improvement by interface passivation and EOT scaling of InGaAs nanowire MOSFETs," IEEE Electron Device Lett., vol. 34, no. 5, pp. 608-610, May 2013.

[10] Y. Li, and C. Lu, "Characteristic comparison of SRAM cells with 20 nm planar MOSFET, omega FinFET and nanowire FinFET," IEEE Nanotechnology, pp. 339-342, Jun 2006.

[11] J. Ou, R. Huang, Y. Liu, R. Wang, and Y. Wang, "Performance investigation of SRAM cells based on gate-all-around (GAA) Si nanowire transistor for ultra-low voltage applications," In Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on, pp. 1-3, 2012.

[12] M.-F. Tsai, B. K. Lu, M.-L. Fan, C.-H. Pao, Y.-N. Chen, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Impacts of wire-LER on Nanowire MOSFET devices, subthreshold SRAM and logic circuits," In VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on, pp. 1-2, 2012.

[13] Y. Q. Wu, R. S. Wang, T. Shen, J. J. Gu, and P. D. Ye, "First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching," in IEDM Tech. Dig., 2009, pp. 331-334.

[14] H.-C. Chin, X. Gong, L. Wang, H. K. Lee, L. Shi, and Y.-C. Yeo, "III–V multiple-gate field-effect transistors with high-mobility In0.7Ga0.3As channel and epi-controlled retrograde-doped fin," IEEE Electron Device Lett., vol. 32, pp. 146-148, 2011.

[15] M. Radosavljevic, G. Dewey, J. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, and R. Chau, "Non-planar, multi-gate InGaAs quantum

well field effect transistors with high-k gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications," in IEDM Tech. Dig., Dec. 2010, pp. 126-129.

[16] N. Singh, K. D. Buddharaju, S. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "Si, SiGe nanowire devices by top–down technology and their applications," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3107-3118, Nov. 2008.

[17] S. Bangsaruntip, G. M. Cohen, A. Majumdar, Y. Zhang, S. U. Engelmann, N. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. Guillom, T. Barwicz, L. Sekaric, M. M. Frank, and J. W. Sleight, "High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling," in IEDM Tech. Dig., Dec. 2009, pp. 297-300.

[18] P. Hashemi, L. Gomez, M. Canonico, and J. L. Hoyt, "Electron transport in gate-all-around uniaxial tensile strained-Si nanowire n-MOSFETs," in IEDM Tech. Dig.,2008, pp. 865-868.

[19] Z. Jing, R. Wang, R. Huang, Y. Tian, L. Zhang D. W. Kim, D. Park, and Y. Wang, "Investigation of low-frequency noise in silicon nanowire MOSFETs," IEEE Electron Device Lett., vol. 30, no. 1, pp. 57-60, Jan. 2009.

[20] S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D.-S. Shin, K.-H Lee, H. S. Park, J. N. Han, C. J. Park, J.-B. Park, and D.-W. Kim, "High performance 5nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability," in IEDM Tech. Dig., 2005, pp. 717-720.

[21] J. Chen, T. Saraya, K. K. M. Shimizu, and T. Hiramoto, "Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI," in VLSI Symp. Tech. Dig., 2008, pp. 32-33.

[22] J. J. Gu, X. W. Wang, H. Wu, J. Shao, A. T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye, "20-80nm channel length InGaAs gate-all-around nanowire MOSFETs with EOT= 1.2 nm and Lowest SS= 63mV/dec," in IEDM Tech. Dig., 2012, p. 633.

[23] M. Si, J. J. Gu, X. Wang, J. Shao, X. Li, M. J. Manfra, R. G. Gordon, and P. D. Ye, "Effects of forming gas anneal on ultrathin InGaAs nanowire metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 102, p. 093505, Mar. 2013.

[24] J. J. Gu, Y. Q. Liu, Y. Q. Wu, R. Colby, R. G. Gordon, and P. D. Ye, "First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach," in IEDM Tech. Dig., 2011, pp. 769-772.

[25] B. Paul, S. Fujita, M. Okajima, T. H. Lee, H.-S. P. Wong, and Y. Nishi, "Impact of a process variation on nanowire and nanotube device performance," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2369-2376, Sep. 2007.

[26] N. Conrad, S. H. Shin, J. J. Gu, M. Si, H. Wu, M. Masuduzzaman, M. A. Alam, and P. D. Ye, "Performance and variability studies of InGaAs gate-all-around nanowire MOSFETs," IEEE Transactions on Device and Material Reliability, vol. 13, no. 4, pp. 489-496, 2013.

[27] J. Dura, F. Triozon, D. Munteanu, S. Barraud, S. Martinie, and J. L. Autran, "Numerical study of variability of technological parameters on remote coulomb scattering in nanowire MOSFETs," in SISPAD, Denver, CO, Sept. 2012, pp. 141-144.

[28] M. Curreli, R. Zhang, F. N. Ishikawa, H. Chang, R. J. Cote, C. Zhou, and M. Thompson, "Real-time, label-free detection of biological entities using nanowire-based FETs," IEEE Trans. Nanotechnol., vol. 7, no. 6, pp. 651-667, Nov. 2008.

[29] Z. Gao, A. Agarwal, A. D. Trigg, N. Singh, C. Fang, C. H. Tung, and K. D. Buddharaju, "Silicon nanowire arrays for ultrasensitive label-free detection of DNA," Anal. Chem., vol. 79, no. 9, pp. 3291-3297, 2007.

[30] T. Yu, R. Wang, R. Huang, J. Chen, J. Zhuge, and Y. Wang, "Investigation of nanowire line-edge roughness in gate-all-

around silicon nanowire MOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2864-2871, Nov. 2010.

[31] A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness," IEEE Trans. Electron Devices, vol. 50, pp. 1254-1260, May 2003.

[32] J. A. Croon, G. Storms, S. Winkelmeier, I. Pollentier, M. Ercken, S. Decoutere, Q. Sansen, and H. E. Maes, "Line edge roughness: Characterization, modeling and impact on device behavior," in IEDM Tech. Dig., 2002, pp. 307-310.

[33] C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, "Microscopic study of random dopant fluctuation in silicon nanowire transistors using 3D simulation," in INEC, pp. 267-270, 2013.

[34] M. H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, "Random dopant fluctuation in limited-width FinFET technologies," IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 2055-2060, Aug. 2007.

[35] R. Wang, J. Zhuge, R. Huang, T. Yu, J. Zou, D.-W. Kim, D. Park, and Y. Wang, "Investigation on variability in metal-gate Si nanowire MOSFETs: analysis of variation sources and experimental characterization," IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2317-2325, Aug. 2011.

[36] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance," in IEDM Tech. Dig., 2006, pp. 1-4.

[37] N. M. Idris, A. R. Brown, J. R. Watling, and A. Asenov, "Simulation study of workfunction variability in MOSFETs with polycrystalline metal gates," in ULIS, pp. 165-168, Mar. 2010.

[38] H. Dadgour, V. De, and K. Banerjee, "Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design," in Proc. ICCAD, 2008, pp. 270-277.