© chandu visweswariah, 2004new challenges in ic design1 new challenges in ic design … with a...

© Chandu Visweswariah, 2004 New Challenges in IC Design 1

New Challenges in IC Design… with a focus on variability …

SBCCI 2004 Panel Discussion

Chandu VisweswariahResearch Staff Member

IBM Thomas J. Watson Research CenterYorktown Heights, NY


Where will performance come from?• Technology scaling

– will require ever-more exotic materials and tricks

– will yield diminishing performance enhancements

• Performance will come from– multiple processors/cores– packaging options (3D ICs, silicon carrier)– better memory hierarchies– better tools– better compilers


Outline

• Challenge #1: migrate from corner-based timing to statistical timing

• Challenge #2: adopt robust design methodologies and practices

• Challenge #3: simultaneous timing and (leakage) power sign-off

• Challenge #4: stop targeting worst-case design; rather, design adaptive circuits that can recover from low-probability problems


The march of technologyP

erfo

rman

ce

Technology generation

Is this worth a huge

investment?


1: Corner-based vs. statistical timing


Benefit of statistical timing• n = # independent sources of variation (say 9)

= total variability in critical path delay (say 5%)

• Fractional increase in frequency with a 3 sign-off instead of 3n sign-off

• Assumes sources of variation are roughly equally significant


Corner-based vs. statistical

0

10

20

30

40

50

60

70

80

1% 2% 3% 4% 5% 6% 7% 8% 9% 10%

Sigma as fraction of cycle time

% f

requ

ency

dif

fere

nce

7

8

9

10

11

12

13

14

15

16

17

18

19

20


2: Robustness

• Reduce sensitivity of performance to variations; examples:– N/P mistracking: avoid too many tall N or tall P

stacks in critical paths– Gate/wire mistracking: use equal fractions of

gates and wires in data and clock paths– ACLV/OCV: use compact layouts so that

capturing and launching paths are close by

– Vt mistracking: use equal fractions of low Vt transistors in critical data and clock paths


Q&A• Q: Where will the models come from?• A: IDMs have an advantage

• Q: What will the models look like?• A: Analytic forms are more conducive than table-based

delay modeling formats

• Q: Can timers handle the capacity?• A: Yes; 2.1M gate design timed in 69 minutes with 10.9

GB memory; 1.1M gate design timed in 110 minutes (dominated by load time) with 4.3 GB memory

• Q: How will it be phased in?• A: (a) true 3 sign-off (b) implicit robustness credit

(c) explicit robustness targeting(d) at-speed test for yield/speed tradeoffs


BEOL early-mode variability on ASIC part

0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

-230 -168 -105 -42

Slack (ps)

Prob

abili

ty

Pessimismreduction

-3

slac

k: -

162

ps

Exh

au

stiv

e c

orn

er a

nal

ysis

: -2

25 p

s

*Early mode; variability in 7 metal levels


Tooleaky

3: Simultaneous power/timing sign-off

Tooslow

Pro

babi

lity

Vt

Goodchips


4: Adaptive circuits• Key idea: we are penalizing performance by

covering low-probability problems• Instead, recover from the low-probability

problems adaptively– sensor circuits: to sense temperature, a late signal, a

wrong logical value, Vt, a mistracking situation– actuator circuits: to change back-gate bias, change Vdd,

repeat a computation, gate the clock, throttle instruction issue

• Adaptive circuits protect against static variability, dynamic variability and single-event upsets

• A wealth of design, CAD, methodology and verification problems suggest themselves!


Conclusion

• Variability is causing a number of problems– leakage power– timing closure– excessive pessimism– worst-case design kills scaling benefit

• Paradigm shifts are periods of opportunity: One person’s headache is another’s windfall!

© chandu visweswariah, 2004new challenges in ic design1 new challenges in ic design … with a...

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