ibis models: the first step towards high speed design kits · ibis models: the first step towards...
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IBIS Models: the first step towards High Speed Design Kits
Stephane RousseauCustomer Marketing ManagerSystem Design Division
IBIS Forum - DATE 20052
Copyright ©1999-2001, Mentor Graphics.
A Little History …
IBIS Forum - DATE 20053
Copyright ©1999-2001, Mentor Graphics.
In the Beginning … 1980s74xxx TTL
Standard I/O
Standard I/O
Stan
dard
I/O
Stan
dard
I/O74xxx TTL 74xxx TTL
74xxx TTL
IBIS Forum - DATE 20054
Copyright ©1999-2001, Mentor Graphics.
Then, speeds increased … 1990
SPIC
E/En
cryp
ted
SPIC
E m
odel
sSPICE/Encrypted
SPICE models
Standard I/O
Standard I/O
Stan
dard
I/O
Stan
dard
I/O
SPICE•Slow•Complex•Encrypted
SPICE/Encrypted SPICE models
SPICE Encrypted
SPICE models
IBIS Forum - DATE 20055
Copyright ©1999-2001, Mentor Graphics.
1993Then IBIS came to the rescue …IBIS Table Models
IBIS Table Models
Standard I/O
Standard I/O
Stan
dard
I/O
Stan
dard
I/O
IBIS
Tab
le m
odel
s
IBIS•Fast•Simple•Standard
IBIS Table
Models
IBIS Forum - DATE 20056
Copyright ©1999-2001, Mentor Graphics.
2002Then came High Speed Serial I/O …
IBIS Table
Models
IBIS Table Models
IBIS Table Models
Standard I/O
Standard I/O
Stan
dard
I/O
Hig
h Sp
eed
Seria
l
SPICE / Encrypted SPICE Models
SPICE•Slow•Complex•Encrypted
IBIS Forum - DATE 20057
Copyright ©1999-2001, Mentor Graphics.
IBIS 4.1 … 2003
IBIS Table
Models
IBIS Table Models
IBIS Table Models
Standard I/O
Standard I/O
Stan
dard
I/O
Hig
h Sp
eed
Seria
l
IBIS
4.1
W
rapp
ers
Examples & Documentation
SPIC
EEn
cryp
ted
SPIC
E M
odel
s
IBIS Forum - DATE 20058
Copyright ©1999-2001, Mentor Graphics.
IBIS 4.1 with SPICEIBIS
— Simple to use— Fast— Unencrypted— Standard
SPICE— Complex— Slow— Encrypted— Proprietary
IBIS 4.1/SPICE— Simple— Slow— Encrypted— Partially Proprietary
IBIS Forum - DATE 20059
Copyright ©1999-2001, Mentor Graphics.
IEEE-1076.1Analog Modeling
Languagelibrary IEEE;use IEEE.electrical_systems.all;use IEEE.std_logic_1164.all;
entity sgx_hssi_tx_icx_slow isgeneric (ui_real : real := 320.0e-12);
type time, internally)port (terminal a_drive, a_signal_pos,
a_signal_neg, pre_emphas2,pre_emphas1, pre_emphas0,drive_sel2, drive_sel1, drive_sel0,termsel1, termsel0 : electrical);end entity sgx_hssi_tx_icx_slow;
Transistor25 Minutes
VHDL-AMS25 Seconds
FusionConverter
FuelCell
Pheromone Bait Available in 100, 200 and 300*
GigaWatt modelsShown with optional convenient carry handle. *One 100g rodent required every 8 hours
inpu
t
outp
ut
Better Mousetraps
—Solves speed problem—Shields user from SPICE complexity— Double IP security—Industry Standard, Non Proprietary
IBIS Forum - DATE 200510
Copyright ©1999-2001, Mentor Graphics.
2003IBIS 4.1 with IEEE 1076.1 AMS …
IBIS Table
Models
IBIS Table Models
IBIS Table Models
Standard I/O
Standard I/O
Stan
dard
I/O
Hig
h Sp
eed
Seria
l
IBIS
4.1
Wra
pper
sExamples & Documentation
IEEE
107
6.1
AM
S M
odel
s
IBIS Forum - DATE 200511
Copyright ©1999-2001, Mentor Graphics.
IBIS 4.1 with IEEE 1076.1 AMSIBIS
— Simple to use— Fast— Unencrypted— Standard
HSPICE— Complex— Slow— Encrypted— Proprietary
IBIS 4.1/IEEE1076.1— Simple— Fast— Unencrypted— Standard
IBIS 4.1/SPICE— Simple— Slow— Encrypted— Proprietary
IBIS Forum - DATE 200512
Copyright ©1999-2001, Mentor Graphics.
IBIS 4.1 Standard
SPICE or Behavioral
Model
SI
Analysis
Multi-Lingual
IBIS
Wrapper
SPICE
VH
DL
-AM
SSI
Analysis
Traditional IBIS
Model
*
.subckt comp
+ inp inm outp outm
*S-parameter model
*RLC SPICE model,
*Transistor model,
*VHDL-AMS Model
.ends
comp.sp[Pin]
1 dcp NC2 dcm NC3 bpn NC4 bpp NC||**********************|[Diff Pin]
1 24 3
|[Series Pin Mapping] 2 3 R_1G_ohm|
[circuit call] componentport_map inp 1port_map inm 2port_map outp 3port_map outm 4[end circuit call]
[external circuit] componentlanguage Spicecorner typ comp.sp compports inp inm outp outm[end external circuit]
IBIS Forum - DATE 200513
Copyright ©1999-2001, Mentor Graphics.
What Next ?
Some more modeling enhancementsHigh Speed Design Kits
IBIS Forum - DATE 200514
Copyright ©1999-2001, Mentor Graphics.
Drop-in Core Layout
Constraints
Footprints
Kit Items
Symbols
Reference Designs
Constraints
Reference Designs
Reuse Blocks
IBIS Forum - DATE 200515
Copyright ©1999-2001, Mentor Graphics.
Custom Menus
SIAnalysis
Transistor Models
Behavioral Models
RLGC Models
S-Param Models
IBIS Table Models
IBIS Multi-Lingual
Wrappers
Eye Masks
Kit Items
Circuit Description
SI Analysis Results
IBIS Forum - DATE 200516
Copyright ©1999-2001, Mentor Graphics.
Kit ItemsRouting Rules
— All signals within a given “QDR-II Match Group” should be matched length from the pin on the FPGA’s (U110 and U148) to the pin on QDR Devices (U101, U102, U106, U108, U117). Maximum deviation is +/- 0.050 inches.
— Keep the distance from the pin on the QDR Device to the termination resistor pack (to VTT_QDRII) to less than 750 mils.
— Keep the distance from the pin on Stratix to the termination resistor pack (to VTT_QDRII) to less than 1250 mils.
— ALL signals must match lengths between pins (as in (1) above) within +/- 0.200 inches (address, control, data, clocks, etc…) Only nets within a match group must be matched tighter as in rule 1. Feedback clocks are exceptions to this rule – see rule 9.
— All signals are to maintain a spacing that is based on its parallelism with other nets. This is as follows:— a. 5 mils for parallel runs < 0.5 inches (~1X spacing relative to plane distance)— b. 10 mils for parallel runs between 0.5 and 1.0 inches (~2X spacing relative to plane distance)— c. 15 mils for parallel runs between 1.0 and 6.0 inches (~3X spacing relative to plane distance)— All signals are to maintain 20 mil separation from other, non-related nets— All signals must have a total length of less than 4 inches.— All signals in the Clock Group should be routed single-ended even though they may seem like
differential clocks based on their naming conventions. As clock signals they must follow spacing rules as outlined in the CLOCKS section of this document.
IBIS Forum - DATE 200517
Copyright ©1999-2001, Mentor Graphics.
Tour de Kit
User Design Area
HSSI KitFootprints
Symbols
Examples and doc Complex Example
IBIS 4.1 wrappers Files to control the HSSI Config
Custom menu
Custom Stimulus
ModelsSimple Example
IBIS Forum - DATE 200518
Copyright ©1999-2001, Mentor Graphics.
Design Kits Development
IC/FPFAVendors
EDAVendors
Customers
IBIS Forum - DATE 200519
Copyright ©1999-2001, Mentor Graphics.
Design Kits – Benefits to Customers
Be up and running fasterHave access to more than just Models, maximize efficiency and productivitySaves significant timeSaves valuable resourcesSaves cost
IBIS Forum - DATE 200520
Copyright ©1999-2001, Mentor Graphics.
Design Kits – Benefits to IC/FPGA Vendors
Facilitates adoption of vendor siliconBetter service to their customers
IBIS Forum - DATE 200521
Copyright ©1999-2001, Mentor Graphics.
Design Kits – Benefits to EDA vendors
Facilitates adoption of toolsMaximize tool usageBetter service to their customers
IBIS Forum - DATE 200522
Copyright ©1999-2001, Mentor Graphics.
IBIS Committee/Forum
Should maybe be another place to drive High Speed Design Kits requirements and make proposal for a common format/content?
IBIS Forum - DATE 200523
Copyright ©1999-2001, Mentor Graphics.