hrushikesh chavan younggyun cho
DESCRIPTION
Structural Fault Tolerance for SOC. Hrushikesh Chavan Younggyun Cho. Agenda. Motivation Introduction BISER FF & Razor FF FITO Implementation Simulation result Conclusion Future work. Motivation. Number of transistors increasing Cramming more components in a single Chip - PowerPoint PPT PresentationTRANSCRIPT
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Hrushikesh ChavanYounggyun Cho
Structural Fault Tolerance for SOC
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• Motivation• Introduction• BISER FF & Razor FF• FITO• Implementation• Simulation result• Conclusion• Future work
Agenda
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Motivation• Number of transistors increasing
• Cramming more components in a single Chip
• Device parameters are not as intended by the designer
• SoC design more vulnerable to internal and external noise
• Important to design a fault tolerant circuit
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Introduction• Transient Fault
• Temporary faults in flip-flop or latch or any memory cell (SEU)
• Temporary faults in a combinational circuit (SET)
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Introduction• Single Event Upset (SEU)
• Another name of Soft Error
• Changing state
• Ionizing radiations
• Electromagnetic interference
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Introduction• Soft Error Fault Tolerant System
• Detect and correct the soft errors
[Mitra-05]
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Introduction• How to make the fault tolerant circuits?
• Redundancy
• Hardware & Time
• BISER FF & Razor FF
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BISER FFs• Built-In Soft Error Resilience
• C-element
• Four Latches
[Ravindran-09]
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BISER FFs• C-element
[http://en.wikipedia.org/wiki/C-element]
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BISER FFs• C-element with four latches
[Ravindran-09]
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Razor FFs
• Razor FF
[Ravindran-09]
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Razor FFs
• How to select CLK Delay
• The shortest path is more than CLK delay
• Time violation can corrupt the system
• More buffers on the path can prevent
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Working of Razor F/F (Fault in Sequential Part)
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Working of Razor F/F (Fault in Combinational Part)
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FITO• Fault Injection Tool
• High observability and controllability
• A key to evaluating fault-tolerant techniques
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FITO• Synthesizable bit-flip fault model
[Reddy-13]
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Implementation
• Implemented 5 Stage Pipeline to test BISER and Razor flop.
• Pipeline implements ADD, ADDI, SUB, AND, OR, SLL, LW, SW, BEQ, JUMP and HLT.
• Replaced ID/EX and EX/MEM flops with fault tolerant flops.
• Executed 4 test benches to test the system.
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Pipelined Processor Architecture
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Tools• Verilog HDL
• Synopsis Design Vision
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Testing Methodology• Clock Period ~ 20ns• Clock Delay ~ 4ns (for Razor F/F)• Transient fault duration < 4ns• Number of faults injected/iteration = 5• Random duration between two consecutive
faults.
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Circuit Modifications with FITO (BISER)
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Circuit Modifications with FITO (Razor)
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Simulation and Results
INDIVIDUAL AREA AND POWER
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Area and Power after 2 Pipelines Swapped with BISER and Razor F/F
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Performance for Normal Operation
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Performance with BISER F/F
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Performance with RAZOR F/F
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• Project implemented two types of fault
tolerant design techniques.
• Choice of design application specific.
• Both techniques efficient and practical to
design systems.
Conclusion
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Future Work
• Reduce cost due to latches.
• Implement Dynamic Voltage and Frequency
Scaling for Razor.
• Hybrid Flop
• Fault Tolerance for Memories
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Thank You
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Questions?