ho #3: elen 384 - review mos transistorspage 1s. saha long channel mos transistors the theory...

HO #3: ELEN 384 - Review MOS Transistors S. Saha

Long Channel MOS Transistors

The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:

The gate bias, VG provides the

control of surface carrier densities.

– For VG < Vth (threshold voltage), the structure consists of two back to back diodes and only

leakage currents flow ( Io of PN junctions), i.e., ID 0

– For VG > Vth, inversion layer exists, a conducting channel exists

from D S and current ID will flow.

Where Vth is determined by the properties of the structure.

n+ n+

S DG

P


Long Channel MOS Transistors

Vth is given by Eq we derived for MOS capacitors. That is,

C

VKqN

C

QV

ox

BBosaB

ox

fmsth

)2(22

(1)

bias substrate

ionconcentrat doping channel

potentialbulk

ecapacitanc oxide gate

density charge interface

torsemiconduc and metalbetween function work

where

B

a

B

ox

f

ms

V

N

C

Q

0 :MOSFETs channel-

0 :MOSFETs channel-

th

th

Vp

Vn


1. NMOSFETs: Band Diagram

FEDG VV 0

0

0

D

G

V

V


NMOSFETs: Band Diagram

0

D

thG

V

VV


2. NMOSFETs: I - V Characteristics


NMOSFETs: I - V Characteristics


I V Characteristics: Basic Equations

Note:• The depletion region is wider around the drain because of the

applied drain voltage VD.

• The potential along the channel varies from VD @ y = L to 0 @ y = 0 between the drain and source.

• The channel charge QI and the bulk charge QB will in general be f(y) because of the influence of VD, i.e. potential varies along the channel length.

+VD+VG

P

ID

QI(y) QB(y)

n+ n+

Inversionlayer

Depletionregion

y

x



where

W = width of the device

V(y) = voltage drop along the channel due to VD

Solving the above three Eq we get ID - VD characteristics.

)(2)(221

)(

:is of influence under theinversioninduce torequired 3.

)()(

:channel in thedensity Charge 2.

:CurrentDrain 1.

0 yVyVVqNKC

VyV

VV

yVVCyQ

dyEQWdydzJ I

BBBasox

fbth

DG

thGoxI

xnIxD



22

:) ,(Region Saturation

2

:) ,(Region Linear

thGoxnD

DSATDthG

DD

thGoxnD

DSATDthG

VVCL

WI

VVVV

VV

VVCL

WI

VVVV

VD

IDVG6

VG5

VG4

VG3

VG2

VG1

LinearRegion Saturation

Region

VD = VDSAT

(Volts) DV

ID (

(am

ps)1/

2 )


3. MOS Device Scaling

3. improve current drive (transconductance, gm)

Benefits of scaling MOSFETs:

1. increase device packing density

2. improve frequency response (transit time) 1/L

n+

P

Ltox

xj

n+

lo

region)n (saturatio for ,

region)(linear for ,

0

0

constant

DSATDthGox

oxn

DSATDDox

oxn

VG

Dm

VVVVt

K

L

W

VVVt

K

L

W

V

Ig

D


MOS Device Scaling

• Note that gm and therefore, the current drive of MOSFETs can be increased by:

– decreasing the channel length, L

– decreasing the gate oxide thickness, tox

• Therefore, much of the scaling is driven by decrease in L and tox.

region)n (saturatio for ,

region)(linear for ,

0

0

constant

DSATDthGox

oxn

DSATDDox

oxn

VG

Dm

VVVVt

K

L

W

VVVt

K

L

W

V

Ig

D


MOS Device Scaling

Though, MOSFET scaling is driven by scaling down L and tox, many problems such as increased electric fields are encountered if scaled only these two parameters.

In 1974, Dennard et al. proposed a scaling methodology which maintains the electric field in the device constants. (R.H. Dennard, et al., IEEE JSSC, vol. 9, p. 256-268, 1974).

Device/circuit parameters Constant field scaling factorDimension: tox, L, W, xj, lo 1/K

Substrate doping: Na K

Supply voltage: V 1/K

Supply current: I 1/K

Parasitic capacitance: WL / tox 1/K

Gate delay: CV / I 1/K

Power dissipation: CV2 / delay 1/K2


MOS Device Scaling

In practice, constant field scaling has not been strictly observed. Since ID gate overdrive, (VG – Vth), thus, the demands for high performance have dictated the use of higher supply voltage. However, high supply voltage implies increased power dissipation (CV2f).

In the recent past, low power applications have become important and have required a scaling scenario with lower supply voltage.

Parameters 1970 1980 1990 2000 2006Channel length (m) 10 4 1 0.18 0.10

Gate oxide (nm) 120 50 15 4 1.5

Junction depth (m) >1 0.8 0.3 0.08 0.02-0.03

Supply voltage 12 5 3.3-5 1.5-1.8 0.6-0.9


MOS Device Scaling

Device/circuit parameters Quasi Constant voltage scaling (K > B > 1)

Dimension: tox, L, W, xj, lo 1/K

Substrate doping: Na K

Supply voltage: V 1/B

Ref: B. Davari, et al., Proc. IEEE, April 1995


4. Limitations of Scaled MOSFETs

A number of factors have been neglected in the simple MOS theory which became increasingly important in scaled devices.

bi, F, and ms of S/D junctions were neglected

– Vth dependence on W, L, and VD is not predicted by simple theory

– I 0 for VG < Vth. Rather I is exponentially dependent on VG.

– Current flow D S can be initiated by VD rather than VG. This can be modeled by a Vth which depends on VD and VG.

– Since fields cannot be held constant because of bi etc. (and because VD has not been scaled in the industry), higher higher carrier velocity. Material limits like vsat become important.


4(a). Effect of Scaling Down L: Vth degradation

In long channel MOSFETs, the gate is completely responsible for depleting the semiconductor (QB). In very short devices, part of the depletion is accomplished by the drain and source biases.

Since less VG is required to deplete QB, Vth as L. Similarly, as VD, more QB is depleted by VD and hence Vth. This effect dominates in lightly doped substrates.


Effect of Scaling Down L: Punchthrough

If the channel length, L becomes too short, the depletion region from the drain can reach source side reducing e- injection barrier. This phenomenon is known as punchthrough.


Effect of Scaling Down L: DIBL

In very short channel devices:

– less VG is required to deplete QB

the barrier to electron injection from source to drain decreases.

– ID at a given VG.

This effect is known as the drain induced barrier lowering (DIBL).


Effect of Scaling L: Effect of DIBL on ID

• DIBL results in an increase in ID at a given VG. Vth as L.

Similarly, as VD, more QB is depleted by VD and hence Vth.


4(b). Carrier Mobility: Velocity Saturation

The mobility of the carriers reduces at higher e-fields in small channel length devices due to velocity saturation (vsat).

As L, while VD constant:- lateral e-field- carrier velocity vsat @ Ec 104 V/cm for e-.

for nMOSFETs with L < 1 m, vsat causes current to saturate for VD < (VG Vth).

satthGoxDSAT vVVWCI )(

. of instead devices short for Thus, square lawLVVI thGDSAT )(


Effect of Vsat on MOSFET I - V Characteristics

MOSFETs with:

L = 2.7 um

tox = 500 A

(a) (b) (c)

(a) Experimental data; (b) simulated data including velocity saturation; (c) simulated data ignoring velocity saturation.


4(c). Sub-threshold Conduction

• For VG < Vth, the surface is in weak inversion and a conducting channel starts to form. As a result, a low level of current flows between the source and drain.

GSV

DI

In MOS subthreshold slope, S is limited to kT/q (60 mv/dec I) ID leakage ; Static power ; and circuit instability .


4(d). Hot Carrier Effects

GVGate Ig

n+ Drainn+ Source

Isub

holehot e

VD > VDSAT

The maximum e-field at the drain-substrate junction is:

0max

)2

s

Dia

K

V(qN E

As L, in the channel near the drain Emaxmore rapidly than long L devices.

The free carriers passing through the high e-field gain sufficient energy to cause hot-carrier effects.


Hot Carrier Effects


• Isub flowing into the

substrate causes an IR drop in the substrate resulting in Body bias – Substrate Current induced Body Effect (SCBE).

– SCBE results in Vth

drop and manifold increase in

Isub

IDS.

Hot Carrier Effects


4(e). Band-to-Band Tunneling

• For small VG ~ 0 and high VD a significant drain leakage can be observed, especially for short channel devices.

• For VG = 0, and VD high, the e-field can be very high in the drain region causing band-to-band tunneling (BTBT):– BTBT happens only when e-field is sufficiently high to cause a

large band bending.


4(f). Effect of Scaled Channel Width

The depletion region extends sideways in the areas outside the gate controlled region increasing the apparent channel width. As a result Vth opposite to short channel devices.

ho #3: elen 384 - review mos transistorspage 1s. saha long channel mos transistors the theory...

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