heart beat monitoring system by gsm technology

CHAPTER 1

INTRODUCTION

Cardiovascular disease is one of the main causes of death in the many countries and

in 1999, it accounted for over 15 million deaths worldwide. In addition, several million

people are disabled by cardiovascular disease (WHO, 1999). The delay between the first

symptom of any cardiac ailment and the call for medical assistance has a large variation

among different patients and can have fatal consequences. One critical inference drawn

from epidemiological data is that deployment of resources for early detection and

treatment of heart disease has a higher potential of reducing fatality associated with

cardiac disease than improved care after hospitalization. Hence new strategies are needed

in order to reduce time before treatment. Monitoring of patients is one possible solution.

Also, the trend towards an independent lifestyle has also increased the demand for

personalized non-hospital based care.

This project “Heart beat monitoring by GSM technology” can be used in hospitals

and also for patients who can be under continues monitoring while traveling from place to

place. Since the system is continuously monitoring the patient and in case of any

abnormal in the heart beat rate of the patient the system will immediately message to the

concerned doctors and relatives about the condition of the patient and abnormal details.

To perform these operations the system uses heart beat sensor, GSM modem, and to

control all these devices the heart of the system micro controller (P89V51RD2) is used.

1.1 Proposed Work

Some severe diseases and disorders e.g. heart failure needs close and continual

monitoring procedure after diagnosis, in order to prevent mortality or further damage as

secondary to the mentioned diseases or disorders. Monitoring these types of patients,

usually, occur at hospitals or healthcare centers. Heart arrhythmias for instance, in many

cases, need continual long-term monitoring. However, the patients are often too early

released, owing to need of hospital bed for another patient on the waiting list, who needs

to be hospitalized immediately.

1.2 Scope of the Work

Long waiting time for hospitalization or ambulatory patient monitoring/treatment,

are other well-known issues for both the healthcare institutions and the patients. This

project provides healthcare authorities to maximize the quality and breadth of healthcare

B.L.D.E.A’s College of Engg & Tech.,Dept. of E&C

services by controlling costs. As the population increases and demand for services

increases, the ability to maintain the quality and availability of care, while effectively

managing financial and human resources, is achieved by this project. The use of modern

communication technology in this context is the sole decisive factor that makes such

communication system successful.

1.3 Design Methodology

In transmitter circuit the Heat Beat is measured by LED and LDR, then it is

applied to the microcontroller. The Microcontroller maintains the records of the measured

readings. It compares the measured heart beat with the normal readings and checks it is

within the normal range or not. If it is normal, then it sends the message as normal

otherwise it sends abnormal to the specified mobile number. The time specified for

sending message is given by the user.


CHAPTER 2

SYSTEM DESCRIPTION

2.1 INTRODUCTION

Embedded systems are one of the emerging technologies which are touching

every nook and corner of the mind. “It is impossible to live without these embedded

gadgets”-says ELECTRONICS magazine. From the above statement, the liveliness of

embedded system can be understood. Data communications is one of the most rapidly

growing commercial market areas today, especially “wireless communications”. In the

past few years, wireless data communications has grown from an obscure and expensive

curiosity into a practical and affordable communication and networking technology.The

convenience of wireless is very appealing as not to deal with running cables to and from

devices in order to interconnect them, and wireless devices can be moved to any location

within the transmission range, while still being able to communicate and broadcast data.

Due to this, it is expected that wireless data communications will become even more

popular and more extensively used in the medical field. Currently the most popular

method of wireless communications is radio frequency transmission. As these devices

have a very low power consumption and power output, perhaps more importantly devices

can achieve good data transmission rates.

2.2 BLOCK DIAGRAM

Transmitter

Receiver


Micro controllerP89V51RD2

Heart BeatSensor

Oscillator

Regulate DC Power

Supply

Serial SwitcherRS 232

GSM Modem

2.2.1 POWER SUPPLY

The 230V line voltage is step-down, rectified, filtered and regulated using

regulators to obtain desired voltages. This circuit can give +5V output at about 150 mA

current and +3.8v and 12v respectively.

2.2.2 MICROCONTROLLER

The microcontroller used is P89V51RD2 operates at 11.0592 MHz at 5V D.C.

Microcontroller controls all the operation. The microcontroller obtains the input from the

heart beat sensors and monitors the heart beat rate.

2.2.3 LIQUID CRYSTAL DISPLAY (LCD)

A Liquid Crystal Display is a low cost, low power device capable of displaying

text. The LCD used is (2 lines X 16 characters) operates at 5V D.C. A microcontroller is

connected to an LCD controller, which in turn is connected to an LCD. The LCD

controller receives control words from the microcontrollers; it decodes the control words

and performs the corresponding actions on LCD. Once the initialization sequence is done,

we can send control words or send actual data to be displayed

2.2.4 GSM MODEM

This GSM-Modem should be a plug and play GSM 900 / GSM 1800 / GSM 1900

modem. A direct and easy integration with RS232 and with in voltage range for the power

supply.

A WAVECOM's GSM/GPRS modem is suitable for the GSM-SMS Transceiver System.

The features of SIMCOM-Modem:

Triband GSM GPRS modem(EGSM 900/1800/1900 MHz)

Designed for GPRS, data, fax, SMS and voice applications

GPRS multi-slot class 10

GPRS mobile station class B

Designed for GPRS, data, fax, SMS and voice applications


Mobile

Fully compliant with GSM Phase 2/2+ specifications

Built-in TCP/IP Protocol

Built-in RTC in the module

AT Command based

2.2.5 HEARTBEAT SENSOR

Heart beat sensor is designed to give digital output of heat beat when a finger is

placed on it. When the heart beat detector is working, the beat LED flashes in unison with

each heart beat. This digital output can be connected to microcontroller directly to

measure the Beats Per Minute (BPM) rate. It works on the principle of light modulation

by blood flow through finger at each pulse.

2.3 CIRCUIT DIAGRAM

CHAPTER 3


HARDWARE DESCRIPTION

3.1 POWER SUPPLY

The transformer 230Volts will be stepped down to 12-0-12 one side of the 12V is

given to the 7805 and Lm317.In this project the microcontroller requires +5V power

supply. The design description of power supply is given below.

The +5 Volt and 3.8V power supply is based on the commercial 7805 & Lm317

voltage regulator IC. This IC contains all the circuitry needed to accept any input voltage

from 8 to 18 volts and produce a steady +5 volt & 3.8volt output, accurate to within 5%

(0.25 volt). It also contains current-limiting circuitry and thermal overload protection, so

that the IC won't be damaged in case of excessive load current; it will reduce its output

voltage instead.

The 1000µf capacitor serves as a "reservoir" which maintains a reasonable input

voltage to the 7805 throughout the entire cycle of the ac line voltage. The bridge rectifier

(WM04) keep recharging the reservoir capacitor on alternate half-cycles of the line

voltage, and the capacitor is quite capable of sustaining any reasonable load in between

charging pulses.

The LED and its series resistor(220ohm) serve as a pilot light to indicate when the power

supply is on and also helps to the reservoir capacitor is completely discharged after power

is turned off. Then I know it's safe to remove or install components for the next

experiment.

Fig 1: Power supply Circuit Diagram

3.1.1 LM317:


The LM317 series of adjustable 3-terminal positive voltage regulators is capable

of supplying in excess of 1.5A over a 1.2V to 37V output range. They are exceptionally

easy to use and require only two external resistors to set the output voltage.Further, both

line and load regulations are better than standard fixed regulators. Also, the LM317 is

packaged in standard transistor packages which are easily mounted and handled.

Fig 2: LM317 pin out

A truly timeless circuit LM317 is a versatile and highly efficient 1.2-37V voltage

regulator that can provide up to 1.5A of current with a large heat sink. It’s ideal for just

about any application. This was my first workbench power supply and I still use it. Since

LM317 is protected against short-circuit, no fuse is necessary. Thanks to automatic

thermal shutdown, it will turn off if heating excessively.

All in all, a very powerful (and affordable!) package, indeed. Although LM317 is

capable of delivering up to 37V, the circuit pictured here is limited to 25V for the sake of

safety and simplicity.

Any higher output voltage would require additional components and a larger heat

sink. Make sure that the input voltage is at least a couple of Volts higher than the desired

output. It’s ok to use a trimmer if you’re building a fixed-voltage supply.

3.1.2 LM7805:

Fig 3: IC Lm7805 pin out


The 7805 is a +5V DC three-terminal fixed-voltage regulator chip. It is a popular

low-cost voltage regulator used in many projects and it is relatively easy to build a power

supply with.

The disadvantage of the 7805 is that it is a "lousy" regulator and therefore not

very efficient. Thus it will not work well using AA batteries, for example. The 7805 is

commonly packaged in a TO-220 case and is rated at 1.0 amp, plenty for the GPS-20.

However, in order for the 7805 to handle its designed rating requires a heat sink be

installed on the 7805.

Bare this in mind when you build this version of the power supply. If the 7805

will be in the open air it may be okay without a heat sink, but if you install it inside an

enclosure, it will require one. If the enclosure is aluminum, simply attach the 7805 to the

enclosure, it will act as a heat sink.

3.2 MICROCONTROLLER P89V51RD2

1.General description

The P89V51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB flash and

1024 B of data RAM. A key feature of the P89V51RB2/RC2/RD2 is its X2 mode option.

The design engineer can choose to run the application with the conventional 80C51 clock

rate (12 clocks per machine cycle) or select the X2 mode (six clocks per machine cycle)

to achieve twice the throughput at the same clock frequency. Another way to benefit from

this feature is to keep the same performance by reducing the clock frequency by half, thus

dramatically reducing the EMI The flash program memory supports both parallel

programming and in serial ISP. Parallel programming mode offers gang-programming at

high speed, reducing programming costs and time to market. ISP allows a device to be

reprogrammed in the end product under software control. The capability to field/update

the application firmware makes a wide range of applications possible. The

P89V51RB2/RC2/RD2 is also capable of IAP, allowing the flash program memory to be

reconfigured even while the application is running.

2. Features

80C51 CPU

5 V operating voltage from 0 MHz to 40 MHz

16/32/64 kB of on-chip flash user code memory with ISP and IAP

Supports 12-clock (default) or 6-clock mode selection via software or ISP


SPI and enhanced UART

PCA with PWM and capture/compare functions

Four 8-bit I/O ports with three high-current port 1 pins (16 mA each)

Three 16-bit timers/counters

Programmable watchdog timer

Eight interrupt sources with four priority levels

Second DPTR register

Low EMI mode (ALE inhibit)

TTL- and CMOS-compatible logic levels

Brownout detection

Low power modes

Power-down mode with external interrupt wake-up

Idle mode

3.Block diagram of P89V51RD2

P89V51RB2/RC2/RD2


Fig 4: DIP40 pin configuration

4. PIN DESCRIPTION

VCC: Supply voltage.

GND: Ground.

Port 0:

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin

can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as

high-impedance inputs. Port 0 may also be configured to be the multiplexed low-order

address/data bus during accesses to external pro-gram and data memory. In this mode P0

has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and

outputs the code bytes during program verification. External pull-ups are required during

program verification.

Port 1:

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output


buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are

pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that

are externally being pulled low will source) because of the internal pull-ups. Current (IIL

Port 1 also receives the low-order address bytes during Flash programming and

verification.

Port 2:




are externally being pulled low will source) because of the internal pull-ups. In this

application, it uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2

Special Function Register. Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3:




are externally being pulled low will source) because of the pull-ups.

Memory organization

The device has separate address spaces for program and data memory.

Flash program memory bank selection

There are two internal flash memory blocks in the device. Block 0 has 16/32/64

kB and is organized as 128/256/512 sectors, each sector consists of 128 B. Block 1

contains the IAP/ISP routines and may be enabled such that it overlays the first 8 kB of

the user code memory. The overlay function is controlled by the combination of the

Software Reset Bit (SWR) at FCF.1 and the Bank Select Bit (BSEL) at FCF.0. The

combination of these bits and the memory source used for instructions is shown in Table

below.


Code memory bank selection

Access to the IAP routines in block 1 may be enabled by clearing the BSEL bit

(FCF.0), provided that the SWR bit (FCF.1) is cleared. Following a power-on sequence,

the boot code is automatically executed and attempts to auto baud to a host. If no auto

baud occurs within approximately 400 ms and the SoftICE flag is not set, control will be

passed to the user code. A software reset is used to accomplish this control transfer and as

a result the SWR bit will remain set. Therefore the user's code will need to clear the SWR

bit in order to access the IAP routines in block 1. However, caution must be taken when

dynamically changing the BSEL bit. Since this will cause different physical memory to be

mapped to the logical program address space, the user must avoid clearing the BSEL bit

when executing user code within the address range 0000H to 1FFFH.

Power-on reset code execution

At initial power up, the port pins will be in a random state until the oscillator has

started and the internal reset algorithm has weakly pulled all pins high. Powering up the

device without a valid reset could cause the MCU to start executing instructions from an

indeterminate location. Such undefined states may inadvertently corrupt the code in the

flash. A system reset will not affect the 1 kB of on-chip RAM while the device is running,

however, the contents of the on-chip RAM during power up are indeterminate. When

power is applied to the device, the RST pin must be held high long enough for the

oscillator to start up (usually several milliseconds for a low frequency crystal), in addition

to two machine cycles for a valid power-on reset. An example of a method to extend the

RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10

mF capacitor and to VSS through an 8.2 kW resistor as shown in Figure 5. Note that if an

RC circuit is being used, provisions should be made to ensure the VDD rise time does not

exceed 1 ms and the oscillator start-up time does not exceed 10 ms. For a low frequency

oscillator with slow start-up time the reset signal must be extended in order to account for

the slow start-up time. This method maintains the necessary relationship between VDD

and RST to avoid programming at an indeterminate location, which may cause corruption


in the code of the flash. The power-on detection is designed to work during initial power

up, before the voltage reaches the brownout detection level. The POF flag in the PCON

register is set to indicate an initial power up condition. The POF flag will remain active

until cleared by software. Following a power-on or external reset the

P89V51RB2/RC2/RD2 will force the SWR and BSEL bits (FCF[1:0]) = 00. This causes

the boot block to be mapped into the lower 8 kB of code memory and the device will

execute the ISP code in the boot block and attempt to auto baud to the host. If the auto

baud is successful the device will remain in ISP mode. If, after approximately 400 ms, the

auto baud is unsuccessful the boot block code will check to see if the SoftICE flag is set

(from a previous programming operation). If the SoftICE flag is set the device will enter

SoftICE mode. If the SoftICE flag is cleared, the boot code will execute a software reset

causing the device to execute the user code from block 0 starting at address 0000H. Note

that an external reset applied to the RST pin has the same effect as a power-on reset.

Software reset

A software reset is executed by changing the SWR bit (FCF.1) from ‘0’ to ‘1’. A

software reset will reset the program counter to address 0000H and force both the SWR

and BSEL bits (FCF[1:0]) = 10. This will result in the lower 8 kB of the user code

memory being mapped into the user code memory space. Thus the user's code will be

executed starting at address 0000H. A software reset will not change WDTC.2 or RAM

data. Other SFRs will be set to their reset values.


Brownout detect reset

The device includes a brownout detection circuit to protect the system from severe

supply voltage fluctuations. The P89V51RB2/RC2/RD2's brownout detection threshold is

2.35 V. When VDD drops below this voltage threshold, the brownout detect triggers the

circuit to generate a brownout interrupt but the CPU still runs until the supplied voltage

returns to the brownout detection voltage VBOD. The default operation for a brownout

detection is to cause a processor reset. VDD must stay below VBOD at least four

oscillator clock periods before the brownout detection circuit will respond. Brownout

interrupt can be enabled by setting the EBO bit (IEA.3). If EBO bit is set and a brownout

condition occurs, a brownout interrupt will be generated to execute the program at

location 004BH. It is required that the EBO bit be cleared by software after the brownout

interrupt is serviced. Clearing EBO bit when the brownout condition is active will

properly reset the device. If brownout interrupt is not enabled, a brownout condition will

reset the program to resume execution at location 0000H. A brownout detect reset will

clear the BSEL bit (FCF.0) but will not change the SWR bit (FCF.1) and therefore will

not change the banking of the lower 8 kB of user code memory space.

Watchdog reset

Like a brownout detect reset, the watchdog timer reset will clear the BSEL bit

(FCF.0) but will not change the SWR bit (FCF.1) and therefore will not change the

banking of the lower 8 kB of user code memory space. The state of the SWR and BSEL

bits after different types of resets is shown in below This results in the code memory bank

selections as shown.

Data RAM memory

The data RAM has 1024 B of internal memory. The device can also address up to 64 kB

for external data memory.

Expanded data RAM addressing

The P89V51RB2/RC2/RD2 has 1 kB of RAM

The device has four sections of internal data memory:

1. The lower 128 B of RAM (00H to 7FH) are directly and indirectly addressable.

2. The higher 128 B of RAM (80H to FFH) are indirectly addressable.

3. The special function registers (80H to FFH) are directly addressable only.

4. The expanded RAM of 768 B (00H to 2FFH) is indirectly addressable by the move

external instruction (MOVX) and clearing the EXTRAM bit


Since the upper 128 B occupy the same addresses as the SFRs, the RAM must be

accessed indirectly. The RAM and SFRs space are physically separate even though they

have the same addresses.

Internal and external data memory structure

Dual data pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1n

determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is

selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data

pointers can be accomplished by a single INC instruction on AUXR1.

Flash memory IAP

1.Flash organization

The P89V51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP

capability, in a second 8 kB block, is provided to allow the user code to be programmed

in-circuit through the serial port. There are three methods of erasing or programming of

the flash memory that may be used. First, the flash may be programmed or erased in the

end-user application by calling low-level routines through a common entry point (IAP).

Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn,

call low-level routines through the same common entry point that can be used by the end-

user application. Third, the flash may be programmed or erased using the parallel method

by using a commercially available EPROM programmer which supports this device.


2.Boot block (block 1)

When the microcontroller programs its own flash memory, all of the low level details

are handled by code that is contained in block 1. A user program calls the common entry

point in the block 1 with appropriate parameters to accomplish the desired operation.

Boot block operations include erase user code, program user code, program security bits,

etc.

A chip-erase operation can be performed using a commercially available parallel

programer. This operation will erase the contents of this Boot Block and it will be

necessary for the user to reprogram this Boot Block (block 1) with the NXP-provided

ISP/IAP code in order to use the ISP or IAP capabilities of this device.

3.ISP

ISP is performed without removing the microcontroller from the system. The ISP

facility consists of a series of internal hardware resources coupled with internal firmware

to facilitate remote programming of the P89V51RB2/RC2/RD2 through the serial port.

This firmware is provided by NXP and embedded within each P89V51RB2/RC2/RD2

device. The NXP ISP facility has made in-circuit programming in an embedded

application possible with a minimum of additional expense in components and circuit

board area. The ISP function uses five pins (VDD, VSS, TXD, RXD, and RST). Only a

small connector needs to be available to interface your application to an external circuit in

order to use this feature

3.1Using the ISP

The ISP feature allows for a wide range of baud rates to be used in your application,

independent of the oscillator frequency. It is also adaptable to a wide range of oscillator

frequencies. This is accomplished by measuring the bit-time of a single bit in a received

character. This information is then used to program the baud rate in terms of timer counts

based on the oscillator frequency. The ISP feature requires that an initial character (an

uppercase U) be sent to the P89V51RB2/RC2/RD2 to establish the baud rate. The ISP

firmware provides auto-echo of received characters. Once baud rate initialization has

been performed, the ISP firmware will only accept Intel Hex-type records

UARTs

The UART operates in all standard modes. Enhancements over the standard

80C51 UART include Framing Error detection, and automatic address recognition.


Mode 0

Serial data enters and exits through RXD and TXD outputs the shift clock. Only 8

bits are transmitted or received, LSB first. The baud rate is fixed at 1¤6 of the CPU clock

frequency. UART configured to operate in this mode outputs serial clock on TXD line no

matter whether it sends or receives data on RXD line.

Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit

(logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the

stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable

and is determined by the Timer 1¤2 overflow rate.

Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit

(logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1).

When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0

or (e.g. the parity bit (P, in the PSW) could be moved into TB8). When data is received,

the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is

ignored. The baud rate is programmable to either 1¤16 or 1¤32 of the CPU clock

frequency, as determined by the SMOD1 bit in PCON.

Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit

(logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1).

In fact, mode 3 is the same as mode 2 in all respects except baud rate. The baud rate in

mode 3 is variable and is determined by the Timer 1¤2 overflow rate.

SCON REGISTER (address 98h) bit allocation


SPI

SPI features

• Master or slave operation

• 10 MHz bit frequency (max)

• LSB first or MSB first data transfer

• Four programmable bit rates

• End of transmission (SPIF)

• Write collision flag protection (WCOL)

• Wake-up from Idle mode (slave mode only)

SPI description

The SPI allows high-speed synchronous data transfer between the

P89V51RB2/RC2/RD2 and peripheral devices or between several P89V51RB2/RC2/RD2

devices. Figure below shows the correspondence between master and slave SPI devices.

The SCK pin is the clock output and input for the master and slave modes, respectively.

The SPI clock generator will start following a write to the master devices SPI data

register. The written data is then shifted out of the MOSI pin on the master device into the

MOSI pin of the slave device. Following a complete transmission of one byte of data, the

SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be

generated if the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit

(ES) are both set. An external master drives the Slave Select input pin, SS/P1[4], low to

select the SPI module as a slave. If SS/P1[4] has not been driven low, then the slave SPI

unit is not active and the MOSI/P1[5] port can also be used as an input port pin. CPHA

and CPOL control the phase and polarity of the SPI clock. Following fig shows the four

possible combinations of these two bits


Watchdog timer

The device offers a programmable Watchdog Timer (WDT) for fail safe

protection against software deadlock and automatic recovery. To protect the system

against software deadlock, the user software must refresh the WDT within a user-defined

time period. If the software fails to do this periodical refresh, an internal hardware reset

will be initiated if enabled (WDRE = 1). The software can be designed such that the

WDT times out if the program does not work properly.

The WDT in the device uses the system clock (XTAL1) as its time base. So strictly

speaking, it is a Watchdog counter rather than a WDT. The WDT register will increment

every 344064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used

as the reload register of the WDT. The WDTS flag bit is set by WDT overflow and is not

changed by WDT reset. User software can clear WDTS by writing ‘1' to it. Figure below

provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control WDT

operation. During Idle mode, WDT operation is temporarily suspended, and resumes

upon an interrupt exit from idle. The time-out period of the WDT is calculated as follows:

Period = (255 - WDTD) ´ 344064 ´ 1 / fCLK(XTAL1) where WDTD is the value loaded

into the WDTD register and fosc is the oscillator frequency.

BLOCK DIAGRAM OF WATCHDOG TIMER

Power-saving modes

The device provides two power saving modes of operation for applications where

power consumption is critical. The two modes are Idle and Power-down.

Idle mode

Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the

program counter (PC) is stopped. The system clock continues to run and all interrupts and

peripherals remain active. The on-chip RAM and the special function registers hold their

data during this mode The device exits Idle mode through either a system interrupt or a


hardware reset. Exiting Idle mode via system interrupt, the start of the interrupt clears the

IDL bit and exits Idle mode. After exit the Interrupt Service Routine, the interrupted

program resumes execution beginning at the instruction immediately following the

instruction which invoked the Idle mode. A hardware reset starts the device similar to a

power-on reset.

Power-down mode

The Power-down mode is entered by setting the PD bit in the PCON register. In

the Power-down mode, the clock is stopped and external interrupts are active for level

sensitive interrupts only. SRAM contents are retained during Power-down, the minimum

VDD level is 2.0 V. The device exits Power-down mode through either an enabled

external level sensitive interrupt or a hardware reset. The start of the interrupt clears the

PD bit and exits Power-down. Holding the external interrupt pin low restarts the

oscillator, the signal must hold low at least 1024 clock cycles before bringing back high

to complete the exit. Upon interrupt signal restored to logic VIH, the interrupt service

routine program execution resumes beginning at the instruction immediately following

the instruction which invoked Power-down mode. A hardware reset starts the device

similar to power-on reset. To exit properly out of Power-down mode, the reset or external

interrupt should not be executed before the VDD line is restored to its normal operating

voltage. Be sure to hold VDD voltage long enough at its normal operating level for the

oscillator to restart and stabilize (normally less than 10 ms).

System clock and clock options

Clock input options and recommended capacitor values for oscillator

Shown in Figure below are the input and output of an internal inverting amplifier

(XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. When

driving the device from an external clock source, XTAL2 should be left disconnected and

XTAL1 should be driven. At start-up, the external oscillator may encounter a higher

capacitive load at XTAL1 due to interaction between the amplifier and its feedback

capacitance. However, the capacitance will not exceed 15 pF once the external signal

meets the VIL and VIH specifications. Crystal manufacturer, supply voltage, and other

factors may cause circuit performance to differ from one application to another. C1 and

C2 should be adjusted appropriately for each design. Table below shows the typical

values for C1 and C2 vs. crystal type for various frequencies.


By default, the device runs at 12 clocks per machine cycle (X1 mode). The device

has a clock doubling option to speed up to 6 clocks per machine cycle . Clock double

mode can be enabled either by an external programmer or using IAP. When set, the EDC

bit in FST register will indicate 6-clock mode. The clock double mode is only for

doubling the internal system clock and the internal flash memory, i.e. EA = 1. To access

the external memory and the peripheral devices, careful consideration must be taken. Also

note that the crystal output (XTAL2) will not be doubled.

Oscillator characteristics (using on-chip oscillator)

Oscillator characteristics (external clock drive)


3.3 HEART BEAT SENSOR

Fig 5:Heart beat sensor

The Heart Beat Sensor provides a simple way to study the heart's function. This

sensor monitors the flow of blood through Finger. As the heart forces blood through the

blood vessels in the Finger, the amount of blood in the Finger changes with time. The

sensor shines a light lobe (small High Bright LED) through the ear and measures the light

that is transmitted to LDR. The signal is amplified, inverted and filtered, in the

Circuit .By graphing this signal, the heart rate can be determined, and some details of the

pumping action of the heart can be seen on the graph.


Fig 6: A sample measurement taken with the heartbeat sensor.

Figure 3.3.1 shows that the blood flowing through the Finger rises at the start of the

heartbeat. This is caused by the contraction of the ventricles forcing blood into the

arteries. Soon after the first peak a second, smaller peak is observed. This is caused by the

shutting of the heart valve, at the end of the active phase, which raises the pressure in the

arteries and the earlobe.

FEATURES

Heat beat indication by LED

Instant output digital signal for directly connecting to microcontroller

Compact Size

Working Voltage +5V DC

APPLICATIONS

Digital Heart Rate monitor

Patient Monitoring System

Bio-Feedback control of robotics and applications

SPECIFICATIONS:

PIN DETAILS:

Board has 3-pin connector for using the sensor. Details are marked on PCB as below.


USING THE SENSOR

Connect regulated DC power supply of 5 Volts. Black wire is Ground, Next

middle wire is Brown which is output and Red wire is positive supply. These

wires are also marked on PCB.

To test sensor you only need power the sensor by connect two wires +5V and

GND. You can leave the output wire as it is. When Beat LED is off the output is

at 0V.

Put finger on the marked position, and you can view the beat LED blinking on

each heartbeat.

The output is active high for each beat and can be given directly to

microcontroller for

interfacing applications.

HEART BEAT OUTPUT SIGNAL

WORKING

The sensor consists of a super bright red LED and light detector. The LED needs

to be super bright as the maximum light must pass spread in finger and detected by

detector. Now, when the heart pumps a pulse of blood through the blood vessels, the

finger becomes slightly more opaque and so less light reached the detector. With each


heart pulse the detector signal varies. This variation is converted to electrical pulse. This

signal is amplified and triggered through an amplifier which outputs +5V logic level

signal. The output signal is also indicated by a LED which blinks on each heart beat.

The pulse signal is applied to the P1.0 input of U2 that is AT89S52 (Can be any

8051 type) which is monitored by the program whenever this input goes high. Internally

to U2, there is a counter which counts how many 1ms intervals there are between two

high going heart beat pulses. This number is then divided by 60,000 and the result is the

pulse rate. For example, if the pulse rate is 60 BPM (beats per minute) there will be a

pulse every second. The duration of one heart beat will be one seconds or 1000 x 1ms.

Dividing 60,000 by 1000 will give the correct result of 60 which is shown on the display.

If there is invalid result (BPM>200) it is invalid and waits for next cycle.


P 0.5

P 0.4

P 0.3

P 0.2

P 0.1

P 0.0

Microcontroller

D7

D6

D5

D4LCDEN

RS

3.4 LIQUID CRYSTAL DISPLAY

Liquid crystal displays (LCDs) offer several advantages over traditional cathode-

ray tube displays that make them ideal for several applications. Of course, LCDs are flat

and they use only a fraction of the power required by cathode-ray tubes. They are easier

to read and more pleasant to work with for long periods of time than most ordinary video

monitors. There are several tradeoffs as well, such as limited view angle, brightness, and

contrast, not to mention high manufacturing cost.16x2 LCD is used in this project to

display data to user. There are two rows and 16 columns. It is possible to display 16

characters on each of the 2 rows. It has two registers, command register and data register.

Fig 7: 8051 and LCD interface.

Description of pins used:

RS, Register Select (Pin 4):

This pin is used to select command register and data register.

If RS=0, instruction command register is selected, allowing the user to send a command

such as clear display, cursor at home, etc.

If RS =1, the data register is selected, allowing the user to send data to be displayed on

the LCD.

EN Enable (Pin 6):

The LCD to latch information presented to its data pins uses the enable pin. When

data is supplied to data pins, a high-to-low pulse must be applied to this pin in order for

the LCD to latch in the data present at the data pins. This pulse must be a minimum of

450ns wide.


R / W, Read/Write (Pin 5):

This pin is connected to ground, as LCD is used only to display data.

D4 – D7 (Pin 11 – Pin 14):

Data to be displayed is sent to LCD on these pins. First MSB is sent, followed by LSB.

D0 – D3 (Pin 7 – Pin 10):

These pins are connected to ground, as they are not used to display data.

Vcc (Pin 2):

This pin is connected to +5v power supply.

Vss (Pin 1):

This pin is connected to ground.

PIN OUT

The module that we are using is a 16 character x 2 line display that we stock over

here. It uses an ST7065C controller, which is HD44780 compatible. The figure below

shows the LCD module and pin out.

Fig 8: LCD pin out

The last 2 pins (15 & 16) are optional and are only used if the display has a

backlight.


http://www.protostack.com/product_by_model.php?model=LC-1602-YG

http://www.protostack.com/product_by_model.php?model=LC-1602-YG

The circuit diagram below shows the LCD module with the basic “plumbing” wired up.

You will notice that pin 5 (RW) is tied to ground. This pin is use to control whether you

are reading or writing to the display. Since reading from the display is very rare, most

people just tie this pin to ground.

The potentiometer connected to pin 3 controls the LCD contrast.

Fig9: LCD pin3 connection

3.5. GSM

GSM (Global System for Mobile Communications originally from Group Special

Mobile) is the most popular standard for mobile telephony systems in the world. The

GSM Association, its promoting industry trade organization of mobile phone carriers and

manufacturers, estimates that 80% of the global mobile market uses the standard.

The ubiquity of implementation of the GSM standard has been an advantage to

both consumers, who may benefit from the ability to roam and switch carriers without

replacing phones, and also to network operators, who can choose equipment from many

GSM equipment vendors.

Newer versions of the standard were backward-compatible with the original GSM

system. For example, Release '97 of the standard added packet data capabilities by means

of General Packet Radio Service (GPRS). Release '99 introduced higher speed data

transmission using Enhanced Data Rates for GSM Evolution (EDGE).


http://ba.protostack.com/2010/03/HD44780_breadboard_03_lrg.jpg

3.5.1The GSM Network – Circuit Switching Domain:

The GSM network was designed keeping in mind the voice activities of the user

and its main purpose was to provide voice connectivity like Public Switched Telephone

Networks but with mobility. The data communication was of secondary importance to

this network but to support this also, designers have considered the circuit switching itself

the mechanism for transmitting data packets.

3.5.2 GSM Architecture:

Fig 10: GSM Architecture

The Mobile Station (MS) directly interacts with one of the Base Transceiver

Stations, which in turn interacts with a Base Station Controllers (BSC). BTS and BSC

combined together forms the BSS. More than one BTSs are connected with one BSC. The

BSC further interacts with Mobile Station Controller (MSC) which is a the heart of the

GSM network. MSC further gives connectivity to the PSTN and other PLMNs. MSC is

also responsible to interact with HLR and VLR, which form the Permanent and

Temporary data bases for all the subscribers’ static and dynamic information.


PSTN

Data Terminal

HLR/VLR

MSCBSC

OMC(Operation & Maintenance

Center)

OperationTerminal

BTS

HandsetA

X.25

A-bis SS7

Network sub-system PSTNRadiosub-system

Mobilestation

UM

SIMcard

3.5.3 GSM Speech and Channel coding :

First of ALL speech is converted to 8 Ksps by going through a LPF and a A/D

converter. Then each symbol is encoded as 13 bits giving 104 Kbps output. Now this is

applied to a RPE/LTP encoder, which converts this to 13Kbps. Speech is divided into 20

millisecond samples, each of which is encoded as 260 bits, giving a total bit rate of 13

kbps.The words, “Mobile Station” (MS) or “Mobile Equipment” (ME) are used for

mobile terminals supporting GSM services. A call from a GSM mobile station to the

PSTN is called a “mobile originated call” (MOC) or “outgoing call”, and a call from a

fixed network to a GSM mobile station is called a “mobile terminated call” (MTC) or

“incoming call”. In this document, the word “product” refers to any product supporting

the AT commands interface.

LED Status Indicator:

The LED will indicate different status of the modem:

- OFF Modem Switched off

- ON Modem is connecting to the network

- Flashing Slowly Modem is in idle mode

- Flashing rapidly Modem is in transmission/communication (GSM only)

Now every embedded system is used to communicate with other system using

GSM and GPRS technology, In this project MODEM is used to access the message sent

by the user to display in doctors mobile.

3.5.4 AT COMMANDS:

1 AT commands features:-

1.1 Wavecom line settings

A serial link handler is set with the following default values (factory settings):

auto baud, 8 bits data, 1 stop bit, no parity, RTS/CTS flow control. Please use the +IPR,

+IFC and +ICF commands to change these settings.

1.2 Command line

Commands always start with AT (which means ATtention) and finish with a <CR>

character.

1.3 Information responses and result codes


Responses start and end with <CR><LF>, except for the ATV0 DCE response format)

and the ATQ1 (result code suppression) commands.

If command syntax is incorrect, an ERROR string is returned.

If command syntax is correct but with some incorrect parameters, the +CME

ERROR: <Err> or +CMS ERROR: <SmsErr> strings are returned with

different error codes.

If the command line has been performed successfully, an OK string is returned.

In some cases, such as “AT+CPIN?” or (unsolicited) incoming events, the

product does not return the OK string as a response. In the following examples

<CR> and <CR><LF> are intentionally omitted.

2 General behaviors:-

2.1 SIM Insertion, SIM Removal

SIM card Insertion and Removal procedures are supported. There are software functions

relying on positive reading of the hardware SIM detect pin. This pin state (open/closed) is

permanently monitored. When the SIM detect pin indicates that a card is present in the

SIM connector, the product tries to set up a logical SIM session. The logical SIM session

will be set up or not depending on whether the detected card is a SIM Card or not. The

AT+CPIN? Command delivers the following responses:

If the SIM detect pin indicates “absent”, the response to AT+CPIN? is “+CME

ERROR 10” (SIM not inserted).

If the SIM detect pin indicates “present”, and the inserted Card is a SIM Card, the

Response to AT+CPIN? is “+CPIN: xxx” depending on SIM PIN state.

If the SIM detect pin indicates “present”, and the inserted Card is not a SIM Card,

the response to AT+CPIN? is CME ERROR 10.

These last two states are not given immediately due to background initialization.

Between the hardware SIM detect pin indicating “present” and the previous results the

AT+CPIN? Sends “+CME ERROR: 515” (Please wait, init in progress). When the SIM

detect pin indicates card absence, and if a SIM Card was previously inserted, an IMSI

detach procedure is performed, all user data is removed from the product (Phonebooks,

SMS etc.). The product then switches to emergency mode.

2.2 Background initialization


After entering the PIN (Personal Identification Number), some SIM user data files are

loaded into the product (Phonebooks, SMS status, etc.). Please be aware that it might take

some time to read a large phonebook. The AT+CPIN? Command response comes just

after the PIN is checked. After this response user data is loaded (in background). This

means that some data may not be available just after PIN entry is confirmed by ’OK’. The

reading of phonebooks will then be refused by

“+CME ERROR: 515” or “+CMS ERROR: 515” meaning, “Please wait, service is not

available, init in progress”. This type of answer may be sent by the product at several

points:

when trying to execute another AT command before the previous one is

completed (before response),

when switching from ADN to FDN (or FDN to ADN) and trying to read the

relevant phonebook immediately,

When asking for +CPIN? Status immediately after SIM insertion and before the

product has determined if the inserted card is a valid SIM Card.

3 General commands

3 .1 Select TE character set +CSCS

3.1.1 Description:

This command informs the ME which character set is used by the TE. The ME can

convert each character of entered or displayed strings. This is used to send, read or write

short messages. See also +WPCS for the phonebooks’ character sets.

3.1.2 Syntax:

Command Syntax: AT+CSCS=<Character Set>

COMMAND POSSIBLE

RESPONSES

AT+CSCS=”GSM” OK

Note: GSM default alphabet Note: Command valid

AT+CSCS=”PCCP437” OK

Note: PC character set code page 437 Note: Command valid

AT+CSCS=? +CSCS: ("GSM","PCCP437","CUSTOM","HEX") OK

Note: Get possible values Note: Possible values


3.1.3 Defined values:

<Character Set>

“GSM”............................................. GSM default alphabet.

“PCCP437”......................................PC character set code page 437.

“CUSTOM” .....................................User defined character set (cf. +WCCS command).

“HEX”...............................................Hexadecimal mode. No character set used ; the user

can read

or write hexadecimal values.

4 Operator selection +COPS

4.1 Description:

There are three possible ways of selecting an operator (PLMN):

The product is in manual mode. It then tries to find the operator specified by the

application and if found, tries to register.

The product is in automatic mode. It then tries to find the home operator and if

found, tries to register. If not found, the product automatically searches for

another network.

The product enters into manual/automatic mode, and then tries to find an

operator as specified by the application (as in manual mode). If this attempt fails it

enters automatic mode. If this is successful, the operator specified by the

application is selected. The mobile equipment then enters into automatic mode.

NOTE: The read command returns the current mode and the currently selected operator.

In anual

Mode, this PLMN may not be the one set by the application (as it is in the search phase).

These commands are not allowed during one communication.

4.1.1 Syntax:

To force an attempt to select and register on a network, the application must send the

following command:

Command syntax: AT+COPS=<mode>, [<format> [ , <oper> ] ]

Possible responses: AT+COPS=<mode>:

OK (Network is selected with full service)

+CME ERROR: 30 (No network service),

+CME ERROR: 32 (Network not allowed – emergency calls only)


+CME ERROR: 3 (Not allowed during one Communication)

+CME ERROR: 4 (Incorrect parameters)

+CME ERROR: 527 (Please wait, and retry your selection later)

+CME ERROR: 528 (Location update failure – emergency calls only)

+CME ERROR: 529 (Selection failure – emergency calls only)

Response syntax for AT+COPS?:

+COPS: <mode> [, <format>, <oper> ]

Response syntax for AT+COPS=?:

+COPS: [list of supported (<stat>, long alphanumeric <oper>, short alphanumeric

<oper>s,

Numeric <oper>) s]

4.2 Network registration +CREG

4.2.1 Description:

This command is used by the application to ascertain the registration status of the product.

4.2.2 Syntax:

Command Syntax: AT+CREG= <mode>

Response Syntax: +CREG : <mode>, <stat> [ ,<lac>,<ci> ] for AT+CREG? Command only

COMMAND POSSIBLE

RESPONSES

AT+CREG? +CREG: <mode>,<stat>

OK

Note: As defined here-above

AT+CREG=0 OK

Note: Disable network registration Note: Command valid

unsolicited result code

AT+CREG=1 OK

Note: Enable network registration Note: Command valid

unsolicited result code

AT+CREG=2 OK

Note: Enable network registration and location Note: Command valid

information unsolicited result code

AT+CREG=? +CREG: (0-2)

Note: 0,1,2 <mode> values are supported


5 AT COMMANDS TO SEND SMS+CMGS:

Description:

This command is used by the application to send the text message of the product.

5.1 Syntax:

Command Syntax: AT+CMGS= <mode>

Response Syntax: + CMGS : <mode>, <stat> [ ,<lac>,<ci> ] for AT+ CMGS? Command only

COMMAND POSSIBLERESPONSES

AT+CMGS? + CMGS: <mode>,<stat>

OK

Note: As defined here-above

AT+CMGS=0 OK

Note: Disable message sending Note: Command valid

Unsolicited result code

AT+ CMGS =1 OK

Note: Enable message sending Note: Command valid

Unsolicited result code

CHAPTER 4


SOFTWARE DESCRIPTION

4.1 SOFTWARE USED

4.1.1 KEIL SOFTWARE

The KEIL 8051 Development Tools are designed to solve the complex problems

facing embedded software developers.In this project we select the KEIL software of

version8.08 .Because it provides Device Database and the µVision IDE sets all compiler,

assembler, linker, and memory options for you. Numerous example programs are

included in this software, and also the KEIL µVision Debugger accurately simulates on-

chip peripherals (I²C, CAN, UART, SPI, Interrupts, I/O Ports, A/D Converter, D/A

Converter, and PWM Modules) of your 8051 device.

Simulation helps you understand hardware configurations and avoids time wasted

on setup problems. When testing the software application with target hardware, use the

MON51, MON390, MONADI, or FlashMON51 Target Monitors, the ISD51 In-System

Debugger, or the ULINK USB-JTAG Adapter to download and test program code on

your target system.

4.1.2 EMBEDDED C

The C programming language is perhaps the most popular programming language

for programming embedded systems. Most C programmers are spoiled because they

program in environments where not only there is a standard library implementation, but

there are frequently a number of other libraries available for use. The cold fact is, that in

embedded systems, there rarely are many of the libraries that programmers have grown

used to, but occasionally an embedded system might not have a complete standard

library, if there is a standard library at all. Few embedded systems have capability for

dynamic linking, so if standard library functions are to be available at all, they often need

to be directly linked into the executable. Oftentimes, because of space concerns, it is not

possible to link in an entire library file, and programmers are often forced to "brew their

own" standard c library implementations if they want to use them at all. While some

libraries are bulky and not well suited for use on microcontrollers, many development

systems still include the standard libraries which are the most common for C

programmers.


C remains a very popular language for micro-controller developers due to the code

efficiency and reduced overhead and development time. C offers low-level control and is

considered more readable than assembly. Many free C compilers are available for a wide

variety of development platforms. The compilers are part of an IDEs with ICD support,

breakpoints, single-stepping and an assembly window. The performance of C compilers

has improved considerably in recent years, and they are claimed to be more or less as

good as assembly, depending on who you ask. Most tools now offer options for

customizing the compiler optimization. Additionally, using C increases portability, since

C code can be compiled for different types of processors.

4.2 PROGRAM#include<p89v51rd2.h>//#include<Reverse.c>#define LINE1_ADDR 0x80#define LINE2_ADDR 0xC0sbit LCD_CS = P3^4;sbit REG_SELECT = P3^5;#define NULL_00 '\0'#define CONTRL_Z 0x1A

#define RELOADLOW0 0x59#define RELOADHI0 0xDCsbit ext =P3^2;sbit TEST =P2^0;

#define MAX_RECD_CHAR 120#define NULL_00 '\0'#define CARRIAGE_RETURN 0X0D#define END_OF_LINE '\n'#include<define.h>static unsigned char ucsthreadState = INIT_STATE;

unsigned char code ucOwnerMGMTNum1[] = "AT+CMGS=\"+919686044657\"\r";unsigned char code ucOwnerMGMTNum2[] = "AT+CMGS=\"+919945345959\"\r";void ClearRecdCharArray(void);void TxdCommandToModem(unsigned char *s);

void Sms_CommandToModem(unsigned char *s, unsigned char ucMGMTIndex);bit mystr_recdchar_ncmp(unsigned char *chkString, unsigned char StrLength);void check_Modem(void);void check_SIM_SIMPIN(void);void SIM_REG(void);void SIM_MODEM_INIT_CHECK(void);void LCD_INIT(void);void write_instr_bit(unsigned char value);void Prep_lcd_Write_Data(unsigned char *line1, unsigned char Line1Addr, unsigned char *line2, unsigned char Line2Addr);void MSDelay(unsigned int delay);void MSDelay_lcd(unsigned int delay);


unsigned char i,j,ucbcd100,ucbcd10,ucbcd1,buffer[15]=" ";void serial_Init(void);void byte_hex_to_bcd_conversion(unsigned int);unsigned char Actual_KeyData,temp100,temp10,temp1;static unsigned int xttemp;static unsigned char xdata ucpulseCount=0,timecount=0,stop=0;

unsigned char recd_count = 0;bit gbok_flag = 0;

unsigned char xdata ABNORM[15]="ABNORMAL ";unsigned char xdata NORM[15]="NORMAL ";

unsigned char xdata recd_char[MAX_RECD_CHAR];

enum ucsthreadState123{ INIT_STATE = 0, MODEM_CHK, SIMPIN_CHK, SIMREG_CHK, SEND_CMNDS,HEART_BEAT_MONITORING,STOP, NO_ACTION }#include<variable.h>void main(void){ while(1) {

switch(ucsthreadState) {case INIT_STATE:TEST=0; ext=0; LCD_INIT(); buffer[14]=NULL_00; buffer[3]=' '; buffer[4]=' ';buffer[5]=' ';buffer[9]=' ';serial_Init();

Prep_lcd_Write_Data(" Heart Beat ",LINE1_ADDR,"Project", LINE2_ADDR); ucsthreadState=MODEM_CHK;break;case MODEM_CHK :check_Modem();ucsthreadState=SIMPIN_CHK;break;case SIMPIN_CHK :check_SIM_SIMPIN();ucsthreadState=SIMREG_CHK;break;case SIMREG_CHK :SIM_REG();ucsthreadState=SEND_CMNDS;break;


case SEND_CMNDS :TxdCommandToModem("AT+CMGF=1\r\n");MSDelay(10);

TxdCommandToModem("AT&W\r\n"); //Store current parameter to user defined profileMSDelay(10);

TxdCommandToModem("AT+CMGD=1,4\r\n"); //Delete All SMSMSDelay(300);

Prep_lcd_Write_Data(" Heart Beat ",LINE1_ADDR,"", LINE2_ADDR); ucsthreadState=HEART_BEAT_MONITORING;break;case HEART_BEAT_MONITORING :while(TEST==0);MSDelay(5);while(TEST==0);TR0 = 1;Prep_lcd_Write_Data(" Heart Beat ",LINE1_ADDR,"Testing Starts", LINE2_ADDR);while(1){ while(ext==0); xttemp++; byte_hex_to_bcd_conversion(xttemp); buffer[0]=ucbcd100; temp10=ucbcd10; buffer[1]=ucbcd10; temp100=ucbcd100;buffer[2]=ucbcd1;temp1=ucbcd1;//Prep_lcd_Write_Data("Heart Beat ",LINE1_ADDR," Project ", LINE2_ADDR);Prep_lcd_Write_Data("PUL SEC PULSRTE",LINE1_ADDR,&buffer[0], LINE2_ADDR);MSDelay(10);

}MSDelay(100);Prep_lcd_Write_Data(" Heart Beat ",LINE1_ADDR,"Testing Stop", LINE2_ADDR);ucsthreadState=STOP;break;case STOP :byte_hex_to_bcd_conversion(ucpulseCount);buffer[6]=ucbcd100;buffer[7]=ucbcd10;buffer[8]=ucbcd1; //Prep_lcd_Write_Data(" ISHWAR ",LINE1_ADDR," ", LINE2_ADDR);

if(stop){

if((xttemp<65)||(xttemp>80)){ ABNORM[9]=' ';

ABNORM[10]=temp100; ABNORM[11]=temp10;


ABNORM[12]=temp1; Sms_CommandToModem(&ABNORM[0],1); MSDelay(10); Sms_CommandToModem(&ABNORM[0],2); MSDelay(10); xttemp=0; TR0 = 0; TL0 = RELOADLOW0; TH0 = RELOADHI0; TR0 = 1;

} else if((xttemp>=65) && (xttemp<=80))

{ NORM[7]=' '; NORM[8]=temp100; NORM[9]=temp10; NORM[10]=temp1; Sms_CommandToModem(&NORM[0],1); MSDelay(10); Sms_CommandToModem(&NORM[0],2); MSDelay(10); xttemp=0;TR0 = 0; TL0 = RELOADLOW0; TH0 = RELOADHI0; TR0 = 1; } }ucsthreadState=HEART_BEAT_MONITORING;break;}}}

void serial_Init(void){ unsigned char int_temp = 0;

////////////////////// Timer 0 10 ms init ////////////////////////// IEN0 = 0; TR0 = 0;

TL0 = RELOADLOW0; TH0 = RELOADHI0;

int_temp = TMOD; int_temp |= 0X01; TMOD = int_temp;

// TR0 = 1;

int_temp = IEN0; int_temp |= 0x02; IEN0 = int_temp;


TF0 = 0;

int_temp = IEN0; int_temp |= 0x80; IEN0 = int_temp;

//////////// Timer 1 serial init with 2400 baud rate ///////////////// int_temp = PCON; int_temp |= 0x80; PCON = int_temp; TMOD |= 0x20;

TH1=0xFA; // 9600 Baudrate SCON=0x50; TR1 = 1; TI = 1; RI=0; ES = 1; PS=1;

}

void serial_interrupt(void) interrupt 4 { unsigned char temp_char; if(TI)

{ TI = 0; } else

if(RI){ temp_char = SBUF; RI = 0; if((temp_char>='A' && temp_char<='Z') || (temp_char>='a' && temp_char<='z') || (temp_char>='0' && temp_char<='9') || (temp_char=='"') || (temp_char==',') || (temp_char=='+') || (temp_char==':')) {

recd_char[recd_count++] = temp_char;

if(recd_count >=MAX_RECD_CHAR) recd_count = 0;

} }

}

void byte_hex_to_bcd_conversion(unsigned int tmp_hex_value){ int hex_value = (int)tmp_hex_value; unsigned char hex_wt; /* variable to store the weights of hex no */

ucbcd100 = ucbcd10 = ucbcd1 = 0; hex_wt = 0x64; /* hex digit 3 weight value */ while(1)


{ hex_value -= hex_wt; if(hex_value<0) break; ucbcd100++; } ucbcd100 = ucbcd100 + 0x30; hex_value += hex_wt; hex_wt = 0xA; /* hex digit 2 weight value */ while(1) { hex_value -= hex_wt; if(hex_value<0) break; ucbcd10++; } ucbcd10 = ucbcd10 + 0x30; hex_value += hex_wt;

ucbcd1 = hex_value+0x30;}

void LCD_INIT(void){ write_instr_bit(0x38);//8-bit data -2-line display MSDelay(10); write_instr_bit(0x0e);//cursor on MSDelay(10); write_instr_bit(0x01);//clear display MSDelay(10); write_instr_bit(0x06);//increment cursor MSDelay(10);}

void write_instr_bit(unsigned char value){

P1=value;REG_SELECT=0;LCD_CS=1;MSDelay(1);LCD_CS=0;

}

void Prep_lcd_Write_Data(unsigned char *line1, unsigned char Line1Addr, unsigned char *line2, unsigned char Line2Addr){ unsigned char i; write_instr_bit(0x01);//clear display MSDelay_lcd(1); write_instr_bit(Line1Addr);


for(i=0;((line1[i]!=NULL_00) && (i<16)); i++) { P1=line1[i];

REG_SELECT=1; LCD_CS=1; MSDelay_lcd(5); LCD_CS=0;

}

write_instr_bit(Line2Addr); for(i=0; ((line2[i]!=NULL_00) && (i<16)); i++) { P1=line2[i];

REG_SELECT=1; LCD_CS=1; MSDelay_lcd(5); LCD_CS=0;

} }

void MSDelay(unsigned int delay){

unsigned int i,j;for(i=0;i<delay;i++)for(j=0;j<2000;j++);

} void MSDelay_lcd(unsigned int delay){

unsigned int i;for(i=0;i<delay;i++);

}

void timer_Interrupt(void) interrupt 1 //10MS TIMER INTERRUPT{ TR0 = 0; TL0 = RELOADLOW0; TH0 = RELOADHI0; TR0 = 1; if(timecount>=100) { timecount=0;

if(ucpulseCount<60) ucpulseCount++;

else{

stop=1;buffer[10]=temp100;buffer[11]=temp10;buffer[12]=temp1;

} } else {


timecount++; } }

void TxdCommand(unsigned char *s){ while(*s!=NULL_00)

{ SBUF = *s;

MSDelay(1); s++;}

SBUF = CARRIAGE_RETURN; SBUF = END_OF_LINE;

MSDelay(10);}

void check_Modem(void){ unsigned char count = 0;

gbok_flag = 0;

while(1){ ClearRecdCharArray(); recd_count=0; TxdCommandToModem("AT\r\n");

gbok_flag = mystr_recdchar_ncmp("OK",2); if(gbok_flag) break; count++; if(count == 10) { Prep_lcd_Write_Data("Modem init",LINE1_ADDR, "Fail", LINE2_ADDR); } } }

void SIM_REG(void){ unsigned char count = 0; gbok_flag = 0; ClearRecdCharArray(); recd_count = 0; while(1)

{ MSDelay(100); Prep_lcd_Write_Data("Network",LINE1_ADDR, "Searching.......", LINE2_ADDR);

TxdCommandToModem("AT+CREG?\r\n"); MSDelay(20);


gbok_flag = mystr_recdchar_ncmp("+CREG:0,1",9); if(gbok_flag) break; gbok_flag = mystr_recdchar_ncmp("+CREG:0,5",9); if(gbok_flag) break;

ClearRecdCharArray(); recd_count = 0;

count++; if(count == 180) Prep_lcd_Write_Data("Network",LINE1_ADDR, "Reg Failed", LINE2_ADDR); } }

bit mystr_recdchar_ncmp(unsigned char *chkString, unsigned char StrLength){

unsigned char uChar1,uChar2=0x00;

while((uChar2+StrLength)<MAX_RECD_CHAR-5) {

uChar1=0x00; while(uChar1<StrLength)

{if(recd_char[uChar2+uChar1]!=*(chkString+uChar1))

break;uChar1++;

}if(uChar1==StrLength)

return(1); uChar2++;

}return(0);

}

void ClearRecdCharArray(void){

unsigned char gucloop;

for(gucloop=0; gucloop<=MAX_RECD_CHAR; gucloop++)recd_char[gucloop] = NULL_00;

}void Sms_CommandToModem(unsigned char *s, unsigned char ucMGMTIndex){ Prep_lcd_Write_Data("Sending.SMS.....",LINE1_ADDR,"", LINE2_ADDR);

if(ucMGMTIndex == 1) {


Prep_lcd_Write_Data("Sending.SMS.....",LINE1_ADDR,&ucOwnerMGMTNum1[9], LINE2_ADDR); TxdCommandToModem(&ucOwnerMGMTNum1[0]); } if(ucMGMTIndex == 2) { Prep_lcd_Write_Data("Sending.SMS.....",LINE1_ADDR,&ucOwnerMGMTNum2[9], LINE2_ADDR); TxdCommandToModem(&ucOwnerMGMTNum2[0]); } MSDelay(50);

ClearRecdCharArray(); recd_count = 0; while(*s!=NULL_00)

{ SBUF = *s;

MSDelay(1); s++;}SBUF = CONTRL_Z;MSDelay(10);s++;SBUF = CARRIAGE_RETURN;MSDelay(10);

while((!mystr_recdchar_ncmp("OK",2)) && (!mystr_recdchar_ncmp("ERROR",5)));

if(mystr_recdchar_ncmp("OK",2)) Prep_lcd_Write_Data("Message Sent ",LINE1_ADDR, "Successfully ", LINE2_ADDR);

else if(mystr_recdchar_ncmp("ERROR",5)) Prep_lcd_Write_Data("Message Sending",LINE1_ADDR, "Failed ", LINE2_ADDR);

MSDelay(50); ClearRecdCharArray();

recd_count = 0; }void TxdCommandToModem(unsigned char *s){ while(*s!=NULL_00)

{ SBUF = *s;

MSDelay(1); s++;}

SBUF = CARRIAGE_RETURN; SBUF = END_OF_LINE;

MSDelay(10);}

4.3 CHARACTERS DISPLAYED IN LCD SCREEN

1. INITIAL DISPLAY

B.L.D.E.A’s College of Engg & Tech.,Dept. of E&C HEART BEATPROJECT

2. WHEN SIM CARD INSERTED

3. WHEN FINGURE PLACED AND PUSH BUTTON PRESSED

4. WHEN MSG SENT SUCCESFULLY

5. IF MSG NOT SENT

4.4.APPLICATIONS

It can be used in hospitals, may be in ICU or general wards so that always a bulky

ECG unit is not required.

It can also be employed in the houses so that the doctor can come to know about

the abnormalities when away.

The use of GSM technology simplifies the delivery of health care services and

enhances communication between health care providers and their patients.

CHAPTER 5

RESULTS AND DISCUSSIONS


NETWORK SEARCHING…

MASSAGE SENT SUCCESFULLY

MASSAGE SENDING FAILED

PUL SEC PULSTR

It is neccesarry to monitor the heart beat rate of patients those already receiving

some forms of surgical treatment,so our device will be nearly helpful for them.

Our device will be able to

- Provides early detection of heart attacks- Eliminates delays in receiving medical treatment- Improves healthcare services to at risk population- Saves lives and improves quality of living

FIG:Heart Beat Monitoring By GSM Technology


a

FIG:Microcontroller With LCD Unit and mobile


FIG:GSM Modem with sim card inserted

CHAPTER 6

CONCLUSION AND FUTURE ENHANCEMENTS

6.1 CONCLUSION

Cardiovascular disease is one of the major causes of untimely deaths in world,

heart beat readings are by far the only viable diagnostic tool that could promote early

detection of cardiac events. Wireless and mobile technologies are key components that

would help enable patients suffering from chronic heart diseases to live in their own

homes and lead their normal life,while at the same time being monitored for any cardiac

events. This will not only serve to reduce the burden on the resources of the healthcare

center but would also improve the quality of healthcare sector. In this project,the heart

beat rate of the patient is sensed.When the implant detects a heart beat rate, it will alert

the microcontroller which in turn will automatically send the message and provide the

patient’s condition so that the patient will be given medical attention within the first few

critical hours, thus greatly improving his or her chances of survival.

6.2 FUTURE ENHANCEMENTS

This algorithm deals only with single patient. This algorithm can be extended to

multiple doctors and multiple patients.


In future we can also design PC software to analyze this received signal and

generate the report and this can be sent back to the doctor.

With the connection established between two ends we can also send patient’s

body temperature, blood pressure to doctor’s side.

In addition to ECG rate, we can also send EEG (electroencephalogram) and

EMG (electromyogram) signals for analyzing.

Using GSM technology we can display the ECG signal on doctor’s mobile

phone.

7.REFERENCES

Kenneth J. Ayala – The 8051 Microcontroller Architecture, Programming and

Applicatins, 2nd Edition, Penarm International, 1996

Muhammad Ali Mazidi an Janice Gillispie – The 8051 Microcontroller

Architecture and Embedded systems, Pearson Education, pearson Eduction, 2003

Boylested and Nashelsky- Electronic Devices and Circuit Theory, EEE, 8th

Edition 2002

Gsm Technology By Lokesh Raghavan

Electronics For You - Magazine

www.Wikipidea.com

www.google.com


http://www.google.com/

heart beat monitoring system by gsm technology

Documents

heart beat monitoring

common entry point

spi clock generator

brownout detect reset

heart beat rate

heart beat sensor

unsigned int delay

clock double mode