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HARP: Hard-Wired Routing Pattern FPGAs Cristinel Ababei , Satish Sivaswamy ,Gang Wang , Kia Bazargan , Ryan Kastner , Eli Bozorgzadeh ECE Dept. ECE Dept. Comp. Science Dept. Univ. of Minnesota Univ. Of California Univ. of California Minneapolis Santa Barbara Irvine MN 55455 CA 93106 CA 92697

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Introduction FPGAs Vs ASICs Lower NRE costs Shorter time to market Num of units Total cost ASIC FPGA NRE cost Eli:You may want to skip this slide

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Problems with FPGAs Circuit Delay: Delay increases due to programmable switches in the FPGA routing architecture Area: Configuration cells and programmable resources incur substantial area penalty Power: Typically not suited for low power applications PerformanceCost ASIC FPGA ASIC FPGA Time to market ASIC FPGA We need to improve

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Motivation Interconnects account for 60% of delay, 75% of area and 80% of power [ Microsystems Tech. Lab @ MIT ] Are we providing too much flexibility? S N W E W N S E Island style routing architecture connection block switch block S W N E

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Our Goal Reduce the number of switches by hard-wiring some intersections Create a mixture of hard wired and flexible switches HARP switches Maintain high degree of routability HARP switchbox

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Outline Routing Pattern Analysis HARP based design flow HARP distribution Simulations Conclusion

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Pattern Analysis Route of a multi-terminal net is a Rectilinear Steiner tree Pattern is a junction in the RST Idea is to form patterns inside switchboxes - HARPs Source Sink 1 Sink 2 Sink 3 Sink 4

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Pattern Analysis Statistical Analysis of routing profiles helps guide HARP insertion Place and route benchmark circuits and determine frequency of various patterns Single segment and multi-segment architectures are considered

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Pattern Types 11 Possible connection patterns inside switch boxes Source Sink2 Sink3 Sink1 Sb A Sb C Sb B - Not connected

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Pattern Length Pattern length: How much each HARP extends along different directions Identify valid pattern Trace along valid directions from the switchbox Minimum length among all directions is the pattern length Source Sink2 Sink3 Sink1 Sb A Sb C Sb B - Not connected 4 6 length 4

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Results of Pattern Analysis For multi-seg architecture, % of ,| decreases and % of L increases

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Results of Pattern Analysis Percentages of patterns remains almost the same Architecture seems to have a bigger impact than the routing algorithm

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Results of Pattern Analysis Distribution for Horizontal and vertical Patterns percentage Pattern length

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Proposed Design Flow Joint Pattern usage Analysis VPR Place and route Statistical Pattern Finder (VPF ) MCNC circuits HARP Architecture design Place & Route on HARP Traditional Architecture definition Compare delay Area & Power HARP-based Routing Architecture Design Flow

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Routing Architecture Design with HARPs HARPs are associated with a length, type and location Length is related to channel segmentation Subset switch box and virtex like channel segmentation is used in this work Challenge is to distribute HARPs inside switchboxes

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Routing Architecture Design New switchbox design includes HARPs besides flexible switches L L T T V H

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FPGA Routing Architecture Routing architecture is represented as a routing graph Routing segments, IO pins represented as nodes Switches are represented as edges Wire 2 Wire 1 Wire 3 Wire 4 LUT in 1in 2 out Source Wire 3Wire 4 Wire 2 Wire 1 in 1in 2 Sink

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Routing Architecture Routing graph construction changes with HARPs Only those edges that form the pattern are present in the routing graph A B C D Normal Switch B A A B D D C C HARP switch C A B D

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Routing Architecture HARPs are not allowed to connect back to back Dangling branches add capacitance Avoid forming large trees of patterns LT dangling branch SB A B

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HARP distribution Populate pattern distribution array with symbolic entries for different patterns Scan FPGA chip and look at candidate locations for HARP insertion Select a pattern from P and an orientation for the pattern For HARPs, insert only those edges that form the pattern into the routing graph and save switch info. All edges are inserted for flexible switches C VLHTLV T HL

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Modeling Changes Capacitance of HARPs include capacitance of all segments forming it When only some segments of a HARP are used, the rest are invalidated Area, delay model of VPR is used Flexible power model developed by Kara Poon et.al. is used CLB SB To sinks Is invalidated CLB out Hard-wired L

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Simulation Results Area X 10 6 Delay X 10 -7 5% Improvement in Area 22% Improvement in Delay

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Simulation Results Channel Width Energy X 10 -7 30% Improvement in Energy 16% increase in Channel Width

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Routing Architecture Relax constraint of not allowing HARPs to connect back to back HARP overlap SB 1 SB 2 SB 1 HARP SW SB1 flex. SW

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Simulation Results Delay X 10 -7 Area X 10 6 Delay improvement is 24%

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Simulation Results Channel width Energy X 10 -7 Improvement in Energy is 32% Channel width increases by 20%

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Limitations and Future work The patterns are distributed randomly inside switchboxes Switchbox layout is an issue as tiling cannot be applied here Future work is to develop a switchbox that can be laid out by tiling and replicating SB1 SB2 SB1 SB2

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Conclusion HARP: Explores the possibility of reducing the number of switches by hardwiring certain switches Delay benefit ~ 24% Energy savings ~ 30% Area reduction ~5% Thank You