hardware development on fpga using vhdl
TRANSCRIPT
Hardware development on
FPGA using VHDL
Benny Thörnberg
Associate Professor in Electronics
2
Parallel statements
� Parallel statements are at architecture-level
� Parallel statements
� The order of the statements as they appear in the code has no meaning
� The result is an event (signal-assignment) in future simulation time
� The parallel statements are
� With-select-when
� When-else
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WITH-SELECT-WHEN
� Is called ”selected signal assignment”
� Parallel statement – sensitive to and operates on signals
� Selects one out of several values that will drive the signal
� The selection is based on all possible values of an expression
with expression select
outsignal <= value1 when val1,
value2 when val2,
...
value9 when val9;
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Results generated from with-select-when
val9val1
value1
value2
value9
outsignal
multiplexer
with expression select
outsignal <= value1 when val1,
value2 when val2,
...
value9 when val9;
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A range of values can be specified
Logical expressions allowed
others is a default choice when
none of the listed choices are true
Examples of use of with-select-when
-- 2-to-1 multiplexer
with addsub select
opcode <= add when ’0’,
sub when ’1’;
with (a and b) select
out <= "1011" when "00"
"11--" when "1Z",
x OR y when "11",
"0000" when others;
add sub
opcode
addsub
with min_integer select
outvec <= X"1F" when 35,
X"27" when 2 TO 5,
X"FF" when OTHERS;
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When-else
� Also called ”conditional signal assignment”
� Parallel statement – sensitive to and operates on signals
� Selects one of several values to drive the signal
� The selection is based on the first condition to be true
outsignal <= value1 when cond1 else
value2 when cond2 else
...
value9;
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Example on the use of when-else
opcode <= add when (addsub = ’0’) else
sub when (addsub = ’1’) else
nop;
out <= "1011" when (a = ’0’) else
"11--" when (b = ’0’) else
x OR y when (a AND b) = ’1’ else
"0000";
-- 4-to-2 priority encoder
outcode <= "11" when in3 = ’1’ else
"10" when in2 = ’1’ else
"01" when in1 = ’1’ else
"00" when in0 = ’1’ else
"00";
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Processes
� A process is a sequential program
� Many processes in an architecture are
executed in parallel
� Communication between processes is done
through signals
� Syntax:
[<process_name>:] process [(sensitivity list>)]
[<declarations in the process>]
begin
<sequential statements>
end process [<process_name>];
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Activated if a, b or c is changed
Activating processes
Active/executing
Waiting
Process is activated when:
-signal in sensitivity list is
changed or
-Signal in wait-statement
Process terminates when:
-end process is reached
-wait-statement is reached
process(a, b, cin)
begin
s <= a xor b xor cin;
end process;
process
begin
s <= a xor b xor cin;
wait on a,b,cin
end process;
Goes to wait-state
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Logic expression with IF-THEN-ELSE in a combinatorial process
� Example:
process (xbus)
begin
if xbus = "111"
then
doitnow <= ’1’;
else
doitnow <= ’0’;
end if;
end process;
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Incorrect usage of IF-THEN …
� Example:process (xbus)
begin
if xbus = "111" then
doitnow <= ’1’; -- a latch will be introduced
end if;
end process;
D Q
G
D-LATCH
doitnow
Xbus(2)
Xbus(1)
Xbus(0)
Nothing in the code assigns the output
To ’0’
process (a,b,c)
begin
d <= (a and b) or c;
end process;
� Include all input signals into the sensitivity list
� If not, the simulation will behave differently from synthesized hardware
� Most synthesis tools do not even consider sensitivity lists
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Sensitivity list
� Example of combinatorial process:
a
bc
d
Synthesis
process
begin
d <= (a and b) or c;
wait on a,b,c;
end process;
Alternatively
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Timing in synchronous systems
� General model for a synchronous system
Combinational logicQ1 D2 Q2
C
tC-Q
tC-Q
tLOGIK tSETUP
tMARGIN
C
Q1
D2
tLOGIK
tSETUP
On clock cycle is the sum of the delays:
MARGINALSETUPLOGIKQC ttttT +++=−
With no timing margin we have obtained the
highest possible clock frequency:
SETUPLOGIKQC tttTf
++
==
−
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min
max
tC-Q and tSETUP are
delays in the flip-flop
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Synchronous processes in VHDL
� Synchronous processes
� Also called clocked processes
� All activated simultaneously at the active clock edge
� Signal assignments in a synchronous process results
in flip-flops
inputs outputs
clock
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Keeps the old value
Latches the new value in the FF clk’event and clk=’1’
clk
clk’event
Example: positive edge-triggeredD-FF in VHDL
library ieee;
use ieee.std_logic_1164.ALL
entity dff IS
port (d, clk : in std_logic;
q : out std_logic);
end dff;
architecture behavior of dff is
begin
process(clk)
begin
if (clk’event and clk = ’1’) then
q <= d;
else
q <= q;
end if;
end process;
end behavior;
clk
d q
dff
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Signal assignment leads to introduction of
FF’s
Example: Code that introduces FF’s in the design
Write a function that stores an 8-bit number in a register if it is greater than 10.
If it is less than 10 the register shall contain 10.
10
10
d
q
2:1 MUX
clk
0
1
d>10
entity load_ge_10 is
port (
clk : in std_logic;
d : in std_logic_vector (7 downto 0);
q : out std_logic_vector (7 downto 0));
end load_ge_10;
architecture rtl of load_ge_10 is
begin
process (clk)
begin
if (clk'event and clk = '1') then
if d > 10 then
q <= d;
else
q <= conv_std_logic_vector(10,8);
end if;
end if;
end process;
end rtl;
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Initialization of FF’s
� At system start the FF’s needs to be initialized
� Two types of initializations
� Synchronous reset/preset
� Asynchronous reset/preset
� Example: synchronous reset
if (clk’event and clk = ’1’) then
if reset = ’1’ then q <= ’0’;
else q <= d;
end if;
end if;
D Q
reset
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� Example: Asynchronous reset
� Exemple: Asynchronous presetprocess (clk, preset)
begin
if preset = ’1’ then q <= ’1’;
elsif (clk’event and clk = ’1’) then q <= d;
end if;
end process;
D Q
preset
process (clk, reset)
begin
if reset = ’1’ then q <= ’0’;
elsif (clk’event and clk = ’1’) then q <= d;
end if;
end process;
D Q
reset
Cont. Initialization of FF’s
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� Automatic synthesis
Develop a state diagram for the problem
Write VHDL-code that captures the problem
Automatic synthesis will perform coding of
state graph and generate a gate level netlist
Design of state machines
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Moore type in VHDL
library ieee; use ieee.std_logic_1164.all;
entity fsm1 is
port (aIn, clk: in std_logic; yOut: out std_logic);
end fsm1;
architecture moore of fsm1 is
type state is (s1, s2, s3, s4);
signal present_state, next_state: state;
begin
process (aIn, present_state) begin
case present_state is
when s1 => yOut <= ’0’;
if (aIn = ’1’) then next_state <= s1
else next_state <= s2;
when s2 => yOut <= ’0’; next_state <= s3;
when s3 => yOut <= ’1’; next_state <= s4;
when s4 => yOut <= ’1’; next_state <= s1;
end case;
end process;
process begin
wait until clk = ’1’;
present_state <= next_state;
end process;
end moore;
S1 S2
S4 S3
yOut=0
aIn=0
yOut=0
yOut=1 yOut=1
aIn=0
aIn=0
aIn=0
aIn=1
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Mealy type in VHDL
architecture mealy of fsm2 is
type state is (S1, S2, S3, S4);
signal present_state, next_state: state;
begin
process (aIn, present_state) begin
CASE present_state IS
when s1 => if (aIn = ’1’)
then yOut <= ’0’; next_state <= s4;
else yOut <= ’1’; next_state <= s3;
end if;
when s2 => yOut <= ’1’; next_state <= s3;
when s3 => yOut <= ’1’; next_state <= s1;
when s4 => if (aIn = ’1’)
then yOut <= ’1’; next_state <= s2;
else yOut <= ’0’; next_state <= s1;
end if;
end case;
end process;
process begin
wail until clk = ’1’;
present_state <= next_state;
end process;
end mealy;
S1 S4
S3 S2
aIn=1/yOut=1
aIn=-/yOut=1
aIn=0/yOut=0
aIn=1/yOut=0
aIn=0/
yOut=1
aIn=-/
yOut=1
aIn yOut
next_statepresent_state
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Counters in VHDL
library ieee;
use ieee.std_logic_1164.ALL;
use work.numeric_std.ALL;
entity modulo8 IS
PORT(clk: in std_logic;
cnt: buffer unsigned (7 downto 0));
END count8;
architecture rtl of count8 is
begin
process (clk)
begin
if rising_edge(clk) then cnt <= cnt +1;
end if
end process;
end rtl;
� Modulo-8 counter
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Shift-register in VHDL
entity shift_r is
port (
clk, resetn, d_in, shift_en : in std_logic;
shift_out : out std_logic_vector(3 downto 0));
end shift_r;
architecture rtl of shift_r is
signal shift_reg: std_logic_vector(3 downto 0);
begin
process (clk, resetn)
begin
if resetn = '0' then
shift_reg <= (others=>'0');
elsif clk'event and clk = '1' then
if shift_en='1' then
shift_reg(3 downto 1) <= shift_reg(2 downto 0);
-- shift_reg <= shl(shift_reg, "1");
-- shift_reg <= shift_reg sll 1;
shift_reg(0) <= d_in;
end if;
end if;
end process;
shift_out <= shift_reg;
end rtl;
d_in shift_out
shift_en
resetn
Alternative ways
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Memories in VHDL
� A RAM or ROM can be designed in two ways
� Use the datatype array
� Use a pre-defined macro cell for the memory device
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Example: 4×8 ROM in VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port (
address : in std_logic_vector(1 downto 0);
dout : out std_logic_vector(7 downto 0));
end ROM;
architecture rtl of ROM is
type rom_table is array (0 to 3) of std_logic_vector(7 downto 0);
constant rom_contents : rom_table := rom_table'("00101111",
"11010000",
"01101010",
"11101101");
begin -- rtl
dout <= rom_contents(conv_integer(address));
end rtl;
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Define existing RAM module
existing in a library
Example #1: RAM in VHDL
architecture rtl of rmodul is
component RAM4_8
port (
din: in std_logic_vector(7 downto 0),
address0, address1, we : in std_logic;
dout : out std_logic_vector(7 downto 0);
end component;
begin -- rtl
ram1:
RAM4_8 port map (
din => d,
address0 => a0,
address1 => a1,
we => we,
dout => q)
end rtl;
din dout
address0
address1
we
RAM4_8
din
a0
a1
we
q
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Define a matrix
Example #2: Synchronous RAM in VHDLlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram32_16 is
port (
addr : in std_logic_vector(4 downto 0);
clk, we_n : in std_logic;
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0));
end ram32_16;
architecture rtl of ram32_16 is
type ram_type is array (31 downto 0)
of std_logic_vector(15 downto 0);
signal ram_array : ram_type;
begin
process(clk)
begin
if clk'event and clk='1' then
if we_n='0' then
ram_array(conv_integer(addr)) <= din;
end if;
end if;
end process;
dout <= ram_array(conv_integer(addr));
end rtl;
dindout
addr
we_n
RAM32_16
clk