Graphene oxide gate dielectric for graphene-based monolithic field effect transistorsGoki Eda, Arokia Nathan, Paul Wöbkenberg, Florian Colleaux, Khashayar Ghaffarzadeh, Thomas D.

Anthopoulos, and Manish Chhowalla Citation: Applied Physics Letters 102, 133108 (2013); doi: 10.1063/1.4799970 View online: http://dx.doi.org/10.1063/1.4799970 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/102/13?ver=pdfcov Published by the AIP Publishing

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Graphene oxide gate dielectric for graphene-based monolithicfield effect transistors

Goki Eda,1,a),b) Arokia Nathan,2,c) Paul W€obkenberg,3 Florian Colleaux,3

Khashayar Ghaffarzadeh,2 Thomas D. Anthopoulos,3 and Manish Chhowalla4

1Department of Materials, Imperial College London, Exhibition Road, London SW7 2AZ, United Kingdom2London Center for Nanotechnology, University College London, London WC1H 0AH, United Kingdom3Department of Physics and Centre for Plastic Electronics, Blackett Laboratory, Imperial College London,Exhibition Road, London SW7 2BW, United Kingdom4Materials Science and Engineering, Rutgers University, 607 Taylor Road, Piscataway,New Jersey 08854, USA

(Received 18 January 2013; accepted 21 March 2013; published online 5 April 2013)

We report unique electrical anisotropy and dielectric properties of graphene oxide (GO) thin

films, which allow facile implementation of GO-based monolithic field effect transistors (FETs).

We demonstrate that exposure of GO films to hydrogen plasma leads to self-limiting reduction of

only the uppermost layers such that a semiconductor-on-insulator type heterostructure is realized.

In such heterostructures, the reduced uppermost layers and the unmodified bulk GO layers serve

as the channel and gate dielectric components, respectively, of a thin film FET. VC 2013 AmericanInstitute of Physics. [http://dx.doi.org/10.1063/1.4799970]

State of the art electronics are enabled by efficient

micro- and nano-fabrication technologies. Silicon, a primary

example in which properties, functionality, and geometrical

features can be modified via chemical and physical processes

at high spatial resolution, allows high-density integration of

device circuitry on a chip.1 Silicon electronics is also facili-

tated by the stable oxide and nitride that can be used as reli-

able gate dielectric and passivation layers that effectively

isolate and protect the device components.

Emerging semiconductors such as graphene require

effective device integration strategies. While scalable growth

and deposition techniques of graphene are rapidly being

developed,2 integration of dielectrics in graphene-based field

effect transistors (FETs) has been challenging due to its

chemical inertness. Growth of uniform Al2O3, for example,

requires deposition of seed or buffer layers followed by

atomic layer deposition (ALD).3–5 Integration of HfO2 (Ref.

6) and hexagonal boron nitride7 as the gate dielectric has

shown promise in device performance but scalable integra-

tion schemes are still being explored.

Graphene oxide (GO) is an insulating form of graphene

with a range of remarkable physical properties as summar-

ized in a number of recent reviews.8–10 Electronically, GO is

a localized insulator with apparent band gap of �3.6 eV

(Refs. 11 and 12) but semiconductor-like gate modulation

has been observed in the basal plane electrical conductiv-

ity.13 Reduced GO (rGO) is a conductor with its electronic

properties strongly dependent on the degree of reduction.

Since GO is a chemical derivative of graphene with similar

mechanical robustness and flexibility, use of GO in

graphene-based flexible devices has recently attracted

attention. Specifically, GO was used as a gate dielectric layer

in bottom-gated FETs with chemical-vapor-deposited (CVD)

graphene as the channel material.14

These reports indicate the viability of GO as the gate

dielectric for graphene-based devices. Integration of these

devices requires graphene and GO to be separately prepared

and subsequently deposited in sequential steps. Here, we pro-

pose a facile route to fabricating FETs having GO and rGO

as the gate dielectric and the channel material, respectively.

The procedure is simple and requires one step plasma reduc-

tion of the top surface layer of GO thin films such that semi-

conductor-on-insulator structure is realized. We further

discuss the unusually large conductivity anisotropy in GO,

which allows fabrication of homostructure FETs.

Graphene oxide was synthesized using the modified

Hummers method15 with graphite crystals obtained from

Branwell Graphite Ltd. The colloidal dispersion of GO was

purified through extensive centrifugation in order to ensure

removal of metallic ions. Films with varying thicknesses

(100 to 650 nm) were deposited by drop casting GO suspen-

sions (�0.5 mg/ml) onto glass or quartz substrates and dried

at 50 �C for 1 h. Capacitance was measured for GO thin films

sandwiched between gold electrodes in a cross bar geometry

in frequency range of 103 to 106 Hz. Out-of-plane DC resist-

ance was measured under the same configuration. Surface re-

sistance was measured between two gold electrodes that

were directly deposited on GO or rGO via thermal evapora-

tion. Multiple separations of the electrodes and different

metals (Au and Al) were tested to obtain the contact resist-

ance. It should be noted that in all cases, contact resistance

was minor compared to the resistance of the channel.

Reduction of GO was achieved under H2 plasma at 2 W and

1 Torr. Plasma exposure time was varied to control the

degree of reduction. Bottom-gated FETs were fabricated by

depositing �350 nm GO films onto substrates with pre-

deposited gold gate electrodes. Source and drain electrodes

aligned with the gate electrodes were evaporated onto GO

a)Current address: Department of Physics, National University of Singapore,

2 Science Drive 3, Singapore 117542.b)Author to whom correspondences should be addressed. E-mail:

g.eda@nus.edu.sgc)Current address: Department of Engineering, University of Cambridge,

Trumpington Street, Cambridge CB2 1PZ, United Kingdom.

0003-6951/2013/102(13)/133108/4/$30.00 VC 2013 American Institute of Physics102, 133108-1

APPLIED PHYSICS LETTERS 102, 133108 (2013)

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thin films. All electrical measurements, except for moisture

sensitivity of capacitance that was conducted inside a vac-

uum chamber, were conducted in dry nitrogen conditions.

Figure 1(a) shows the variations in specific capacitance

Ci as a function of inverse GO film thickness. Linear fit to

the plot gives a dielectric constant of �2.8, which is some-

what lower than the previously reported values.14 It is well

known that GO is highly hygroscopic and water molecules

intercalate the layers depending on the humidity condi-

tions.16 We observed that the dielectric constant is substan-

tially higher (�6) in ambient conditions as compared to that

measured in vacuum or in dry nitrogen conditions (Figure

1(b)). Quick response in capacitance to moisture indicates

rapid uptake of ambient water molecules. Specific capaci-

tance was found to be weakly dispersive at frequencies

below 1 MHz (Figure 1(c)) and also weakly dependent on

voltage (Not shown). For films with thicknesses above

200 nm, the leakage current density was typically between

0.1 and 1 lm/cm2 at applied electric field of 2 MV/cm, indi-

cating the excellent leakage resistance of GO (Figure 1(d)).

Low bias c-axis resistivity of the GO thin films was found to

be on the order of 1014 X cm, comparable to that of SiO2.

We previously reported that the in-plane sheet resistance

of as-synthesized individual GO sheets to be on the order of

1011� 1012 X.17 This translates into in-plane resistivity of

roughly 105 X cm, indicating that the conductivity anisot-

ropy in GO is unusually large (�109) as compared to graph-

ite where the anisotropy ratio is typically 102� 103.18

We fabricated three-terminal devices with 300 nm thick

as-synthesized GO thin films as schematically shown in

Figure 2(a). Conduction in GO occurs via hopping of elec-

trons between localized states.17,19 The hopping probability

diminishes rapidly with the separation between the hopping

sites. Since the GO sheets are separated by the functional

groups and intercalating molecules, interlayer hopping

conduction, i.e., out-of-plane conduction, is strongly sup-

pressed compared to in-plane conductivity (Figure 2(b)).

Due to giant conductivity anisotropy, GO behaves as a semi-

conductor for in-plane conduction but as a dielectric for elec-

tric field applied in the out-of-plane direction. Surprisingly,

we found the resistance between the source and drain elec-

trode to be modulated by the gate bias with “on/off” ratio of

�10 (Figures 2(c) and 2(d)). Leakage current measured at

the gate electrode was consistently below 1 nA in this device

configuration. The conduction was found to be p-type sug-

gesting hole doping by adsorbed water and oxygen mole-

cules commonly observed in GO and other forms of carbon

nanostructures.20 These devices exhibited large channel re-

sistance and limited transconductance of 1.3� 10�9 A/V.

Assuming that the depth of the conductive channel is within

few-layer thickness, field effect mobility is estimated to be

�10�3 cm2/Vs.

We employed dry chemical reduction using H2 plasma

to create a highly conductive channel at the top surface of

the GO thin films. Figures 3(a) and 3(b) show I-V character-

istics and the low bias sheet resistance of the channel as a

function of plasma reduction time for two different batches

of samples. Rapid drop in sheet resistance by 3� 4 orders of

magnitude in the initial few minutes of plasma exposure and

saturation after 600 s are observed. The extent of reduction,

which is typically evident from the color change, could not

be recognized by visual inspection, suggesting that the chem-

istry of the bulk remains largely unchanged. The absorption

spectra also show minor increase with increasing plasma ex-

posure time (Figure 3(c)). The absorption peak, which is

known to shift with reduction,21 remains at 225 nm indicat-

ing that bulk of the film is unaffected by the plasma expo-

sure. Figure 3(d) shows difference in the absorption

FIG. 1. (a) Specific capacitance Ci of GO thin films as a function of inverse

thickness (1/d). (b) Changes in specific capacitance upon evacuation and

purging of air. (c) Specific capacitance as a function of frequency. (d)

Leakage current through 450 nm thick GO thin film measured in a sandwich

structure (inset).

FIG. 2. (a) Schematic of monolithic GO-based FET. (b) Schematic showing

the conduction pathway in the device. The in-plane hopping conduction

dominates the ID-VD current over the interlayer hopping conduction, which

contributes to the gate leakage (IG). ((c) and (d)) Transfer (c) and output (d)

characteristics of the device. In (c), the drain voltage is varied from 5 to

15 V in 5 V steps.

133108-2 Eda et al. Appl. Phys. Lett. 102, 133108 (2013)

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spectrum of plasma-treated and untreated samples. The dif-

ference spectrum (DA¼Aplasma-treated – Auntreated) shows a

peak at 272 nm, which is in agreement with that of rGO.21

The absorptance at the near-infrared (NIR) end of the spec-

trum is 2.4%, which is consistent with that of monolayer gra-

phene,22 suggesting that plasma exposure resulted in

reduction of topmost layer of the GO film.

Figure 4(a) shows the schematic of a FET consisting of

plasma-reduced GO as the channel material and GO as the

gate dielectric. As compared to the case of untreated GO

devices, the in-plane conduction in the uppermost rGO

layer is enhanced while the bulk dielectric property remains

unchanged (Figure 4(b)). The transfer and output character-

istics of a 1 min reduced device shown in Figures 4(c) and

4(d), respectively, indicate substantially improved channel

conductance due to reduction of GO. The field effect mobil-

ity and transconductance were typically found to be 2

orders of magnitude higher than those of GO homostructure

FETs. The leakage current at the highest applied gate bias,

however, also increased by a similar order of magnitude

suggesting that reduction may have resulted in creation of

leaky pin holes on GO films. Longer exposure to plasma

led to higher channel conductance but also higher gate

leakage. The on-off ratio was between 2 and 3 consistent

with most rGO-based field effect devices reported in the

literature.9

In summary, we demonstrated that GO thin films repre-

sent a unique dielectric material with unusual conductivity

anisotropy that can be viewed as a substrate on which device

structures can be fabricated in a manner analogous to silicon

processing. Short exposure to H2 plasma is found to reduce

only the uppermost layer of GO, leading to rGO/GO hetero-

structure from which graphene-based monolithic FET fabri-

cation can be achieved.

G.E. acknowledges the Royal Society for the Newton

International Fellowship and financial support from the Centre

for Advanced Structural Ceramics (CASC) at Imperial College

London. G.E. also acknowledges Singapore National Research

Foundation for partly funding the research under NRF

Research Fellowship (NRF-NRFF2011-02). M.C. acknowl-

edges support from NSF ECCS Award 1128335.

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FIG. 3. (a) ID-VD characteristics and (b) extracted sheet resistance (Rs) of

rGO layer formed on top of GO at different plasma exposure time. (c)

Absorption spectrum of untreated GO and rGO/GO films as a function of

plasma exposure time. (d) Difference spectrum between the 600 s plasma

exposed and the untreated samples.

FIG. 4. (a) Schematic of a bottom-gated FET based on rGO/GO heterostruc-

ture. (b) Schematic showing the conduction pathway in the device. In-plane

hopping conduction is enhanced in the rGO layer while the interlayer hop-

ping conduction remains suppressed. ((c) and (d)) Transfer (c) and output

(d) characteristics of the device. In (c), the drain voltage is varied from 5 to

15 V in 5 V steps.

133108-3 Eda et al. Appl. Phys. Lett. 102, 133108 (2013)

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