monolithic integration of detectors and transistors on high-resistivity silicon

STD6, Carmel, CA, Sept. 11-15, 2006

Monolithic Integration of Detectors and Transistors on High-Resistivity Silicon

G.-F. Dalla Betta1, G. Batignani2, L. Bosisio3, M. Boscardin4, P. Gregori4, C. Piemonte4,

L. Ratti5, G. Verzellesi6, N. Zorzi4

1 INFN Trento and University of Trento,Italy2 INFN Pisa and University of Pisa, Italy3 INFN Trieste and University of Trieste, Italy4 ITC-irst,Trento, Italy5 INFN Pavia and University of Pavia, Italy6 INFN Trento and University of Modena/Reggio Emilia, Italy


Outline

• Introduction

• Process development at ITC-irst

• Transistor description:

• Experimental results

• Conclusions

n-JFET (tetrode, triode)

n-MOSFET

npn BJT


Introduction

• Front-end electronics embedded on the detector substrate

can provide better noise performance and easier assembly,

at the expense of process complexity and cost

• Normally worth for low capacitance detectors only

• Pioneering work in this field dates back to late 80’s:

MPI Munich & BNL (for drift detectors),

LBNL (detector compatible CMOS process for pixels)

• Most successful developments: fully depleted CCDs and

DEPFET DEPFET talk by J.Velthiustalk by J.Velthius


Process development at ITC-irst

• It all started as a major technological challenge: first step

toward becoming a primary technological partner for INFN

• The process development went on in the framework of few

national projects (INFN and MIUR), mainly device oriented

• When device performance improved, we could start to

identify suitable applications

• Current activity is oriented to:

–-ray scintimammography (PIN diode + tetrode JFET)

– X-ray imaging (JFET-MOSFET active pixels)

– Radon monitoring (BJT)


Fabrication technology overview

1.1. Starting material: HR Si, 4”, <111>, n-type Starting material: HR Si, 4”, <111>, n-type

2.2. P-doped poly-Si gettering (back-side)P-doped poly-Si gettering (back-side)

3.3. Deep implantations (p-well, n-channel) Deep implantations (p-well, n-channel)

4.4. Active area & poly-Si (low- and high-doping)Active area & poly-Si (low- and high-doping)

5.5. Shallow implantationsShallow implantations

6.6. Interconnections (metal 1, Interconnections (metal 1, metal 2metal 2) )

Standard steps Dedicated steps


2 options (different doping profiles)

b) BJT (by product)b) BJT (by product)

n- Si substratep-well p-well

n+ n+ n+p+p+ p+

n-channel

11

12

13

14

15

16

17

18

19

20

21

0 0,5 1 1,5 2 2,5 3depth (um)

Net

do

pin

g (

cm^

-3)

n+/n-ch. p-well n- sub.

Emitter

Base

Col

lect

or

a) JFETa) JFETp+ p-well n- sub.

Top

-gat

e

Bottom-gate

n-ch.


Process parameters

0.0

0.2

0.4

0.6

0.8

1.0

0 20 40 60 80 100

reverse voltage, Vrev [V]

Jle

ak

[nA

/cm

2]

Parameter Typical Range

Subst. doping concentration

2 – 5 × 1011 cm-3

Full depletion voltage

15 – 30 V

Leakage current density

0.15 – 0.75 nA/cm2

Generation lifetime 50 – 250 ms

Surface generation velocity

5 – 15 cm/s

Field oxide

charge density

3.5 – 4.0 × 1011 cm-2

Data from last batch (JSD6, 2006)Diode leakage current

(thickness=300m)

Additional steps do not degrade the process quality


Transistors: tetrode n-JFETs

Enclosed layout

Top-gate

drain source

Bo

ttom

-ga

te

p+

n-channel

Bottom gate

n+

n+

p+ p+n+

source

drain

n substrate-

n poly+

substrate

p-well

n+

Top gate

p+

100/6

(Lmin=6m): it needs contact on top-gate


Tetrode JFET (W/Lmm)

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

-1.5 -1 -0.5 0top-gate voltage, Vtg [V]

dra

in c

urr

en

t, Id

[A]

Vbg= 0V -0.25V -0.5V -0.75V -1V

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

-2 -1.5 -1 -0.5 0bottom-gate voltage, Vbg [V]

dra

in c

urr

en

t, Id

[A]

Vtg= 0V -0.25V -0.5V -0.75V -1V

Transfer characteristics in saturation region (Vds=3V)

Top-gate modulation Bottom-gate modulation

Allows for independent top-gate and bottom-gate control


Tetrode JFET (W/Lmm)

Output characteristics (Vbg=0) Input capacitance (Vbg=0)

0.1

0.2

0.3

0.4

0.5

0.6

-1.5 -1 -0.5 0top-gate voltage, Vtg [V]

Ctg

ss [p

F]

Vds=1V

Vds=3V

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

0 1 2 3 4 5

drain voltage, Vd [V]

dra

in c

urr

en

t, Id

[A]

Vtg= 0V -0.25V -0.5V -0.75V -1V

Low capacitance can match small area detectors


Detector head for scintimammography

0

50

100

150

0 5 10 15 20

shaping time (us)

EN

C (

e-

rms)

Jlk=0.2nA/cm2Jlk=0.5nA/cm2Jlk=1nA/cm2

8x8 PIN+JFETmatrix

Front side: 8x8 PIN+JFET array (pitch 2mm)Tetrode JFET as CSA input transistor

Bump bonding to ASICs via LTCC interconnection

1.6 cm

1.6

cm

Back side:

CsI(Tl) scintillator + ARC

99mTc -rays (140keV)

CsI(Tl) scintillator

550nm photons

PIN detector

~2000 electrons

Modular design

tile


Transistors: triode n-JFETs

Stripe interdigitated layout (Lmin=4m) gate

drain

source

top-

gate

p+

n-channel

gate

n+

n+

p+ p+n+

source

drain

n substrate-

n poly+

substrate

p-well (bottom-gate)

p-w

ell c

onta

ct

1000/4

Top-gate & Bottom-gate shorted at the implant level


Triode JFET (W/Lmm)

Transfer characteristics (Vds=3V) Input capacitance

gate voltage, Vg (V)

drai

n cu

rren

t, I d

(mA

)

0

5

10

15

-1.5 -1.0 -0.5 0.00

5

10

15

tran

scon

duct

ance

, gm

(mS

)

transconductance

drain current

gate voltage, Vg (V)

drai

n cu

rren

t, I d

(mA

)

0

5

10

15

-1.5 -1.0 -0.5 0.00

5

10

15

tran

scon

duct

ance

, gm

(mS

)

transconductance

drain current

Due to bottom gate contribution, larger transconductance, but also larger capacitance (and gate current)


Triode JFET (W/Lmm)

Noise spectrum (Vds=3V) White noise (Vds=3V)

101 102 103 104 105

frequency (Hz)

Noi

se v

olta

ge s

pec

trum

(n

V/H

z0.5

)

0

2

4

6

8

10

Id=250 A

Id=500 A

Id=1 mA

Id=2 mA

Id=5 mA

101 102 103 104 105

frequency (Hz)

Noi

se v

olta

ge s

pec

trum

(n

V/H

z0.5

)

0

2

4

6

8

10

Id=250 A

Id=500 A

Id=1 mA

Id=2 mA

Id=5 mA

0

2

4

6

8

10

12

14

0 200 400 600gm

-1 (V/A)

Pow

er s

pect

ral d

ensi

ty (

10-1

8V

2 /Hz)

=0.67, RGG’=490

'

14 GG

mBw R

gTkS

'

14 GG

mBw R

gTkS

White noise close to theoretical value (normal RGG’), Very good low-frequency noise behavior


Benchmark: JFET-based CSAMonolithic part

+ external passive components1 10Peaking tim e [s]

100

1000

EN

C [

e- r

ms]

C d=0C d=5.6pFC d=10pFC d=22pFC d=33pF

Equivalent Noise Charge(with 8th order semigaussian

unipolar shaper)

Good ENC, in spite of large Cstray from the test board


Transistors: n-MOSFETs

gate

drain

source

well

p+

well

n+

n+

p+

source

drain

n substrate-

n poly+

substrate

p-well

n+

gate

n+

Enclosed layout (Lmin=4m)125/5S&D self-aligned to poly-Si gate.


0.0

0.5

1.0

1.5

0.0 1.0 2.0 3.0 4.0 5.0

drain voltage, Vds [V]

dra

in c

urr

en

t, Id

[mA

]

Vgs=2V

Vgs=2.5V

Vgs=3V

Vgs=3.5V

Vgs=4V

0

50

100

150

200

0.0 1.0 2.0 3.0 4.0 5.0

gate voltage, Vgs [V]

dra

in c

urr

en

t, Id

[A

] Vw=0

Vw=-0.5V

NMOS (W/Lmm)

Transfer characteristics(Vds=0.1V)

Output characteristics

Static characteristics are good enough to implement basic circuit functions


0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.2 0.4 0.6 0.8 1.0

input current, Id1 [mA]

ou

tpu

t cu

rre

nt,

Id2

[mA

]

Example: current mirror

0

100

200

300

400

500

600

0.0 1.0 2.0 3.0 4.0 5.0

output voltage, Vd2 [V]

ou

tpu

t cu

rre

nt,

Id2

[A

]

Id1=100uA

Id1=200uA

Id1=300uA

Id1=400uA

Id1=500uA

Max. error 4%

Vd2=3V

D1 D2

GND

Max. Error 7%

vD2

ID1

M 2M 1

ID2


Fully integrated CSA

JFETs

Bias/F

ee

dba

ck

J4400/6

IN

OUT

VDD

J5400/4

J8400/4

M2125/5

M1144/10

CF0.5pF

J340/6

J2200/4

J1400/4

J6400/6

J720/6

M3144/10

M4125/5

M10144/10

M5125/5

VSS

GND

650 m

900

m


• Column pull-down: J2

• Readout: DDS stage

• P-well/substrate detector

• Punch-through Reset

• Address: M1

• Source follower: J1

Active pixel arrays (1)

On pixel (3T-like APS)


Active pixel arrays (2)

Pixelmatrix

Pixel

DDS

J2

J1 M1 RES

4 mm

6 m

m

235 m

235

m

Only one collecting electrode


Transistors: npn BJTs

base

emitter

Two emitter profiles and different layouts possible

Emitter area 0.01mm2

p+

n-channel

base

n+

p+n+

emitter

n substrate-

n poly+

collector

p-well


Deep emitter npn BJT (AE=0.01mm2)

0

100

200

300

400

500

600

700

800

900

1000

1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

Ic (A)

curr

en

t ga

in

Vcb=10V

Vcb=50V

Vcb=100V

Very high gain(~600) allows for radiation

detection with a simple setup (load resistor only) …

Current gain ()

… but it needs bias to obtain a time constant of ~ 10s of s.

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0E+00 1E-04 2E-04 3E-04Time (s)

Em

itter

vol

tage

(V

)

Iem=150nA

Iem=3uA

Iem=7uA

Iem=18uA

Lbcbebcbe

E

RCrCC

tQI

exp0

Transient response

Without bias


particle counter

Rpoly~100M(must be rbe

0

20

40

60

80

100

120

0 100 200 300

time [us]

Sig

na

l [m

V]

80V from top 9V from top 80V from bottom

particles from 239Pu source (with 150 k Rload)

Interesting for Radon monitoring with anextremely simple setup

E

C

P

B

RpolyNPN

scope

RL

Vbias


Conclusions• We have reported on recent results from the development of detector-compatible transistors at ITC-irst• Devices feature good characteristics that are promising in view of full detector system implementations• With last batch, we have started to focus on some applications• The prototype functional tests are under way• The technology is available to interested application-oriented partners


Additional slides


Radiation damage effects

Gate current (Vgs=0, Vds=3V)

Noise spectrum(Id=250A, Vds=3V)

10-11

10-10

10-9

10-8

10-7

0 20 40 60 80 100

Substrate voltage, Vsub (V)

Gat

e cu

rre

nt, I

g(A

)

Before irradiation

After 1×1012 n/cm2

After 9×1012 n/cm2

10-11

10-10

10-9

10-8

10-7

0 20 40 60 80 100

Substrate voltage, Vsub (V)

Gat

e cu

rre

nt, I

g(A

)

Before irradiation

After 1×1012 n/cm2

After 9×1012 n/cm2

Before irradiation

After 1×1012 n/cm2

After 9×1012 n/cm2

Single JFETs (1000/4) irradiated with neutrons

102 103 104 105 106

frequency (Hz)

Noi

se v

olta

ge

spec

trum

(n

V/H

z0.5

)

1

10

100

After 1×1012 n/cm2

After 9×1012 n/cm2

Before irradiation

Increase of gate current (proportional to fluence)Lorentzian noise contributions appear


Irradiated CSA: ENC prediction

400

600

800

1000

1200

1400

0 4 8 12 16 20 24

Peaking time (s)

Equ

ival

ent N

oise

Cha

rge

(e-rm

s)

Before irradiation, sim.Before irradiation, exp.

After 1×1012 n/cm2, sim.


400

600

800

1000

1200

1400

0 4 8 12 16 20 24

Peaking time (s)

Equ

ival

ent N

oise

Cha

rge

(e-rm

s)

Before irradiation, sim.Before irradiation, exp.



RF=10M

400

500

600

700

800

900

1000

1 10

Eq

uiv

ale

nt

no

ise

char

ge

[e- r

ms]

Peaking time [s]

High fluence

Low fluence

w Lorentzian contribution

w/o Lorentzian contribution

Based on input JFET characteristics (1000/4)

Minor effect of Lorentzian noiseLarge effect of gate current increase and related need of lower RF value

Should be better with tetrode JFET (lower current from top-gate alone)


BJT biasing: pnp BJTEpnp

Cnpn

Enpn

Bpnp

vcontr

1.E-13

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

0 0.1 0.2 0.3 0.4 0.5 0.6

Vcontr [V]

I En

pn

, IE

pn

p, I

Bp

np

[A

] IEnpn

IEpnp

IBpnp

Lnn = 400 μm

Lnn = 100 μm

Lnn = 200 μm

Lnn = 800 μm

Cnpn

n-

n+

pn+

n p+n+ nLnn

Enpn BpnpEpnp

ICpnpIBnpn

npn detector pnp biasing transistor

Cnpn

n-

n+

pn+

n p+n+ nLnn

Enpn BpnpEpnp

ICpnpIBnpn

npn detector pnp biasing transistor

-50 0 50 100 150 200 250 300 350 400 450-0.0002

0.0000

0.0002

0.0004

0.0006

0.0008

0.0010

0.0012

0.0014

0.0016

0.0018

0.0020

0.0022

0.0024

0.0026

0.0028

Q0=(Ve(0)*)/(RL*)

Ve(0) Q0[mV] [sec] [fC]

0.462 507 123.258 5.5960.973 520 68.256 6.3642.137 568 40.684 7.6272.558 500 34.482 8.7900.772 126 25.137 7.674

RL

*IE

(t)

[V

]

t [sec]

B IE=2.9 A C 3.6 A D 10.2 A E 50.7 A F 175.5 A

IR laser pulses@ different Vcontr

(with 20k Rload)

Allows for multi-elementcurrent biasing(current mirror)

bias region

x

x

monolithic integration of detectors and transistors on high-resistivity silicon

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