gnu radio conference 2015: aha prototyping dvb-s2x using the ettus x310
TRANSCRIPT
Sales and Contact Information• Website
- www.aha.com• Sales Contact
- [email protected]• White Paper to Presentation
- http://www.aha.com/Uploads/AHA_4709E2IQ_C4ISR_White_Paper3.pdf
• Youtube Presentation- https://www.youtube.com/watch?v=hYSLJadvlDc
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AHA Product Group• AHA’s Expertise
- Over 25 years of developing Forward Error Correction ASICs, boards, and FPGA cores.
• AHA’s Mission- Advance IP Development Center for Comtech EF Data- Communication and Data Analysis Technologies
• Our Core Products
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LDPCVersaFEC®
Reed Solomon Turbo-Product
Introduction• Purpose
- Share Experience Creating DVB-S2X Modem on Ettus X310
- Invite Discussion FPGA cores in SDR Ecosystem
• Motivation to Listen- Commercial SATCOM 80% of DoD Capacity- Bigger Pipes- DVB-S2X increases spectral efficiency and throughput
• Outline- DVB-2X Overview- Modem Design- Conclusion
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DVB-S2X Overview
DVB-S2X Overview• DVB-S2X Ratified in 2014• Unidirectional Data Link
- Physical and Link Layer• Roll Off Factors:
- DVB-S2 0.20, 0.25, 0.30- DVB-S2X 0.05, 0.10, 0.15
• Modulation and Coding :- BPSK to 256APSK- Inner LDPC + Outer BCH- Rates : 1/5 to 8/9
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Spectral Efficiency and MODCODs7
DVB-S2X Data Framing8
EPGSE EP
GSE EP
GSE
GSE
DATABBHSTREAMADAPT
BCH-P LDPC-PCODED BBFRAME FECENCODE
PLH Slot-1 Slot-2 Slot-3 Slot-16 Pilot Slot-17 Slot-18 Slot-N
Slot-1 Slot-2 Slot-3 Slot-NPLFRAMER
Modem Design
Hardware Block Diagram10
X310 SBX
FPGA
AHAE2IQ
HOST
ETHERNETPACKETS
10111
RX LO
ADADC
TX LO
DAC
I
Q
I
Q
RX
TX
I/Q
I/Q
SPIBUS
E2IQ Block Diagram11
HOST
ETHERNETPACKETS
10111
DigI/Q
DigI/Q
E2IQ
MODEMCONTROL
SPIBUS
SPICONTROL
DEMODPLDEFRAMERLLRFEC
DECODEGSD
MODPLFRAMER
FECENCODEGSE SYMBOL
MAP
STREAMADAPT
STREAMADAPT
ZPU
User Interface12
BER Testing Setup13
HOST
CARRIER/NOISEGENERATORRX
TXX310/SBX
E2IQ
Performance Results14
Summary and Conclusion
Summary• DVB-S2X
- Increased Spectral Efficiency over DVB-S2• Modem Design and Performance
- SBX, X310, E2IQ- Data Flow and Control/Configuration- Low Implementation Loss- 324 Mbps Max Data Rate
• FPGA Cores in the SDR Ecosystem?- CPU Limitations- RFNoC, NI Labview, Pothos
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Sales and Contact Information• Website
- www.aha.com• Sales Contact
- [email protected]• White Paper to Presentation
- http://www.aha.com/Uploads/AHA_4709E2IQ_C4ISR_White_Paper3.pdf
• Youtube Presentation- https://www.youtube.com/watch?v=hYSLJadvlDc
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THANK YOU