gentest: an automatic test-generation system for sequential circuits

Gentest: An Automatic Gentest: An Automatic Test-Generation System for Test-Generation System for

Sequential CircuitsSequential CircuitsMohamed Abougabal,Mohamed Abougabal,

Wael Hermas,Wael Hermas,Tarek Saad,Tarek Saad,

Rami AbielmonaRami AbielmonaELG 5194ELG 5194

Wednesday November 22, 2000Wednesday November 22, 2000Prof. Sunil DasProf. Sunil Das

Presentor: Mohamed Presentor: Mohamed AbougabalAbougabal

Introduction GentestIntroduction Gentest DefinitionDefinition Converting Sequential to Combinational circuitConverting Sequential to Combinational circuit Gentest ArchitectureGentest Architecture

Introduction to GentestIntroduction to Gentest Definition:Definition:

– Gentest is an automatic Test-Generation System for Gentest is an automatic Test-Generation System for sequential Circuits.sequential Circuits.

Gentest:Gentest: – Was introduced because of the rapid growth of VLSI chips, Was introduced because of the rapid growth of VLSI chips,

we certainly know that these chips contains faults. Therefore we certainly know that these chips contains faults. Therefore we need Gentest to help us achieve the high fault coverage. we need Gentest to help us achieve the high fault coverage.

– It Overcomes the inefficiency of previous ATG methods for It Overcomes the inefficiency of previous ATG methods for sequential circuits by combining a sequential test generator sequential circuits by combining a sequential test generator with a concurrent fault simulator.with a concurrent fault simulator.

Test Generation Test Generation Techniques (1)Techniques (1)

1. Manually write test vectors1. Manually write test vectors (write a sequence of values provided (write a sequence of values provided to the circuit input)to the circuit input)– Disadvantage:Disadvantage:

It’s tedious and time-consuming process It’s tedious and time-consuming process 2.2. BIST : Built-In-Self test Circuit BIST : Built-In-Self test Circuit

The circuit itself create test vectors . The circuit generates random patterns The circuit itself create test vectors . The circuit generates random patterns that can thoroughly test a combinational circuit.that can thoroughly test a combinational circuit.– Disadvantage: Disadvantage:

It requires more circuitry. It requires more circuitry. The cost of chip is higher because of the area.The cost of chip is higher because of the area. It causes the chip to be slowerIt causes the chip to be slower Finding the exact fault coverage for test vector is difficult.Finding the exact fault coverage for test vector is difficult.

Test Generation Test Generation Techniques (2)Techniques (2)

3. ATG: Automatic Test Generation.3. ATG: Automatic Test Generation.– GGiven the description of a circuit , ATG programs deliver a iven the description of a circuit , ATG programs deliver a

set of vectors.set of vectors.A complete ATG algorithm guarantee finding a test for a fault A complete ATG algorithm guarantee finding a test for a fault if one exists.if one exists.

– Disadvantage: Disadvantage: It’s not practical for every circuitIt’s not practical for every circuit

Since most of the sequential circuits are practical circuits we Since most of the sequential circuits are practical circuits we can use Scan Design Techniques to convert sequential circuits can use Scan Design Techniques to convert sequential circuits into combinational circuits.into combinational circuits.

The difficulty of sequential test generation lies on the large The difficulty of sequential test generation lies on the large number of decision steps.number of decision steps.

Converting Sequential Converting Sequential to Combinational to Combinational

Circuits (1)Circuits (1)

The First Sequential Test Generation Algorithm were The First Sequential Test Generation Algorithm were just an extension of the combinational test algorithm.just an extension of the combinational test algorithm.

Those Algorithm are:Those Algorithm are:– D- AlgorithmD- Algorithm– Podem (Path-Oriented Decision making.)Podem (Path-Oriented Decision making.)

We can model Sequential circuits by two blocks We can model Sequential circuits by two blocks (Combinational and Memory)(Combinational and Memory)

Converting Sequential Converting Sequential to Combinational to Combinational

Circuits (2)Circuits (2)

Figure 1. Sequential circuit model

Iterative Logic Array Iterative Logic Array Method (1)Method (1)

Now use this same concept and expanding on it we Now use this same concept and expanding on it we can model a Sequential circuits into Combinational in can model a Sequential circuits into Combinational in time Domain and this method is known as The time Domain and this method is known as The Iterative Logic Array MethodIterative Logic Array Method..

In Figure 2: Each copy corresponds to the circuit In Figure 2: Each copy corresponds to the circuit behavior at one time frame. Therefore D-Algorithm behavior at one time frame. Therefore D-Algorithm and Podem can be applied because these are and Podem can be applied because these are combinational circuits.combinational circuits.


Figure 2. Iterative logic array model


Problems:Problems:– Inefficient in dealing with repeated faults sites.Inefficient in dealing with repeated faults sites.– Excessive memory usage because the circuit must be saved Excessive memory usage because the circuit must be saved

for each time frame in test sequence.for each time frame in test sequence.

Solution: Solution: – Mallela and Wu have introduced Mallela and Wu have introduced STG2STG2 (sequential test (sequential test

generator using the Back algorithm)generator using the Back algorithm)– Then Gentest was introduced. Gentest is combination of Then Gentest was introduced. Gentest is combination of

STG2 and Csim ( Concurrent fault simulator).STG2 and Csim ( Concurrent fault simulator).

Gentest Architecture Gentest Architecture (1)(1)

Functionality of:Functionality of:– STG2STG2: Generates a test sequence for every target fault selected by : Generates a test sequence for every target fault selected by

GentestGentest– Csim Csim : Determines which faults are detected by the STG2-generated test : Determines which faults are detected by the STG2-generated test

sequences.sequences.– Gentest:Gentest: Submits the vectors created for fault detection to a fault simulator. Submits the vectors created for fault detection to a fault simulator.

Now the overall operation of Gentest .Now the overall operation of Gentest .– 1. 1. The user can provide a fault list; otherwise, Gentest creates one after The user can provide a fault list; otherwise, Gentest creates one after

collapsing all equivalent faults.collapsing all equivalent faults.– 2. User can set a time limit or let it be generated by an experimental 2. User can set a time limit or let it be generated by an experimental

formula in SGT2.formula in SGT2.– 3. User can provide some initializing vectors that Csim will simulate to 3. User can provide some initializing vectors that Csim will simulate to

initialize the circuitinitialize the circuit

Gentest Architecture Gentest Architecture (2)(2)

– 4. Gentest selects an untried and undetermined fault as a 4. Gentest selects an untried and undetermined fault as a target fault for SGT2.target fault for SGT2.

– 5. SGT2 tries to generate a test sequence for the target 5. SGT2 tries to generate a test sequence for the target fault.fault.

– 6. So by looking at steps 1 to 5. Test sequence can be 6. So by looking at steps 1 to 5. Test sequence can be generated in one of the three cases:generated in one of the three cases:

Test sequence can be generated to detect the target faultTest sequence can be generated to detect the target fault The target fault can prove untestableThe target fault can prove untestable Time limit can be reached.Time limit can be reached. In either of these cases Gentest returns to step 4.In either of these cases Gentest returns to step 4.

Presentor: Wael Presentor: Wael HermasHermas

Iterative Logic Array ModelIterative Logic Array Model Podem AlgorithmPodem Algorithm Putzolu and Roth Test MethodPutzolu and Roth Test Method STG2 DiscussionSTG2 Discussion Back AlgorithmBack Algorithm

The Test GeneratorThe Test Generator

Problems of previous test generation method– Iterative Logic Array Model– Podem Algorithm– Putzolu and Roth Test Method

Iterative Logic Array Iterative Logic Array Model (1)Model (1)

The following figure (refer to figure 3) shows a sequential circuit with a single stuck-at fault.

Each “*” is the fault site in each time frame. Using the iterative logic array model, this fault has a

repeated fault effect at every time frame.

Iterative Logic Array Iterative Logic Array Model (2)Model (2)

Figure 3. General model of a test sequence

Podem AlgorithmPodem Algorithm Assume that the fault, in the previous example, can only

be tested by a test sequence with eight test vectors Lets us say that the Podem algorithm needs to know

that the propagation of fault effects should start after time frame 5 (Podem algorithm will stop at frame 4) since all the sensitized paths are blocked

Without knowing the test sequence, having this information would be impossible, therefore we can conclude that Podem algorithm can be very inefficient in generating test sequence for sequential circuits.

Putzolu and Roth Test Putzolu and Roth Test Method (1)Method (1)

Uses the two-step approach of the D-algorithm to generate the test sequence.

Their method has the same problem as Podem at time frames 1-4.

To solve this problem, the five-valued model of the D-algorithm was extended to be the nine-valued model

Table 1 compares the five-valued and nine-valued models

Putzolu and Roth Test Putzolu and Roth Test Method (2)Method (2)

Table 1. Comparison of 5-valued and 9-valued models

The nine-valued modelThe nine-valued model The nine-valued model lets us use single-path

sensitization in the D-algorithm. – The nine-valued model is very inefficient during justification– The nine-valued model has the following efficiency problems– To justify an N-input gate's output value, there are N*N

choices– No simple testability guidance can rank these N*N choices.

Sequential Test Sequential Test Generator (STG2)Generator (STG2)

Because of the efficiency problems in the previous test generators, a complete test generator STG2, without excessive memory requirements, is developed.

Uses the Back Algorithm and the Split value model

The Back Algorithm (1)The Back Algorithm (1) The Back Algorithm proceeds as follows:

– the algorithm selects the primary output with the sensitized value

– this is accomplished through a new testability measurement called derivability

– the fault is not testable if no primary output can have a sensitized value

– the algorithm justifies the values required at the current time frame

– the test sequence has been found if the state input requirements of the current time frame match the initial state values

The Back Algorithm (2)The Back Algorithm (2)

Continued:– the back algorithm justifies time frame by time frame (all the

requirements of one time frame can be handled simultaneously)

– during test generation, the circuit status has to contain at most two time frames: the current and previous time frames.

– Hence, we can conclude the Back Algorithm's memory requirements is minimal.

Presentor: Tarek SaadPresentor: Tarek Saad

Fault simulationFault simulation Sequential circuit fault simulationSequential circuit fault simulation Nine-valued modelNine-valued model Split value modelSplit value model Testability guidancesTestability guidances

Fault SimulationFault SimulationGood machineGood machine

A logic model of the circuit-under test without any faults insertedA logic model of the circuit-under test without any faults inserted

Faulty machinesFaulty machinesA logic model of the circuit-under-test with one or more fault A logic model of the circuit-under-test with one or more fault models insertedmodels inserted

Fault specificationFault specificationDefining the set of modeled faults and performing fault collapsingDefining the set of modeled faults and performing fault collapsing

Fault insertionFault insertionSelecting a subset of the faults to be simulated and creating the Selecting a subset of the faults to be simulated and creating the data structures to indicate the presence of the faultsdata structures to indicate the presence of the faults

Sequential Circuit Fault Sequential Circuit Fault SimulationSimulation

Figure 4. Sequential circuit test simulation model

Nine-valued Model (1)Nine-valued Model (1) The good machine and bad machine are The good machine and bad machine are

two independent sub-circuits with the two independent sub-circuits with the same primary inputs.same primary inputs.

It combines the values of the two sub It combines the values of the two sub circuits to reduce memory needed to circuits to reduce memory needed to store circuit status.store circuit status.

In this arrangement the two circuits must In this arrangement the two circuits must be justified simultaneously.be justified simultaneously.

Figure 6. The nine-valued model

Figure 5. Realization of a Sequential circuit

Nine-valued Model (2)Nine-valued Model (2)

Inefficiencies:Inefficiencies: Justifying two independent sub circuits simultaneously Justifying two independent sub circuits simultaneously

increases the number of backtracks and the time increases the number of backtracks and the time wasted.wasted.

Split value algorithm will solve this problem.Split value algorithm will solve this problem.

Split Value Model (1)Split Value Model (1) Extension to nine-value model to Extension to nine-value model to

improve it’s performance during improve it’s performance during justification.justification.

It splits the nine values into two sets It splits the nine values into two sets of three values for the good, and bad of three values for the good, and bad machine.machine.

Separate storage for the circuit Separate storage for the circuit statuses, good/bad machine can be statuses, good/bad machine can be justified separately.justified separately.

Figure 7. The split value model

Split Value Model (2)Split Value Model (2) Each machine is justified separately, we can use testability measurement Each machine is justified separately, we can use testability measurement

of each circuit to rank available choices.of each circuit to rank available choices. Split model uses default value to reduce backtracks significantlySplit model uses default value to reduce backtracks significantly..Definitions:Definitions:

Good valueGood value. Value at the good machine.. Value at the good machine.Bad valueBad value. Value at the bad machine.. Value at the bad machine.RelationRelation. Relation between good and bad value.. Relation between good and bad value.Good/bad values Good/bad values can be 0, 1, x(don’t care), or z(high can be 0, 1, x(don’t care), or z(high impedance).impedance).Sensitized linesSensitized lines.. Lines with unequal good and bad values. Lines with unequal good and bad values.Non-sensitized Non-sensitized lineslines. Lines with equal good and bad value, not . Lines with equal good and bad value, not affected by fault site.affected by fault site.RelationRelation.Could be sensitized, non-sensitized, or unknown..Could be sensitized, non-sensitized, or unknown.

Split Value Model (3)Split Value Model (3)

Dynamic identification of relation information proceeds Dynamic identification of relation information proceeds as follows:as follows:

– If all input of an element are non sensitized lines, then all If all input of an element are non sensitized lines, then all outputs must be non-sensitized.outputs must be non-sensitized.

– If any output of an element is a sensitized line, then at If any output of an element is a sensitized line, then at least one input must be a sensitized line.least one input must be a sensitized line.

Advantages:Advantages:– The high impedance value is used in bus element The high impedance value is used in bus element

containing circuits to avoid bus conflicts.containing circuits to avoid bus conflicts.

Testability GuidanceTestability GuidanceTwo testability measurements guide decision making in conventional test generators:Controllability: measures the difficulty of placing a specific logic (0or1) value on that line.Observability: measures.The difficulty of observing the fault effect at that line from the primary outputs.• Both are calculated based on the good machine.• Observability guides the sensitized-path selection while controllability guides the line value justification.• Back algorithm (as mentioned) uses drivrablitiy similar to observabilityand measures the dificulty of driving the fault effect from the fault site to a line.

Presentor: Rami Presentor: Rami AbielmonaAbielmona

Experimental resultsExperimental results STG2 AnalysisSTG2 Analysis Gentest AnalysisGentest Analysis ConclusionsConclusions Future Work and BiographiesFuture Work and Biographies

Experimental ResultsExperimental ResultsSequential Test GeneratorsSequential Test Generators

STG2 is an extension of STG1, described by STG2 is an extension of STG1, described by Mallela and WuMallela and Wu

STG2 uses the Back algorithm and the Split STG2 uses the Back algorithm and the Split value model, while STG1 utilizes the extended value model, while STG1 utilizes the extended backtrace method and the nine-valued model.backtrace method and the nine-valued model.

STG1.5 uses the D-algorithm and the Split STG1.5 uses the D-algorithm and the Split value model.value model.

From the experimental results that will be From the experimental results that will be presented next, STG2 was chosen for presented next, STG2 was chosen for implementation in Gentest, because it has implementation in Gentest, because it has shown the best fault coverage and total test-shown the best fault coverage and total test-generation time. generation time.

Experimental ResultsExperimental ResultsSTG2 Analysis (1)STG2 Analysis (1)

The three sequential test generators were The three sequential test generators were compared by live-testing them on a Convex compared by live-testing them on a Convex C-1 computer using a myriad of circuits, the C-1 computer using a myriad of circuits, the latters’ characteristics shown in Table 2latters’ characteristics shown in Table 2

Looking at that table, a few definitions are in Looking at that table, a few definitions are in order:order:– GatesGates >>> >>> The number of gates in the circuit;The number of gates in the circuit;– p1,p0p1,p0 >>> >>> The primary inputs and outputs;The primary inputs and outputs;– I/O pins I/O pins >>> >>> Either input or output, but not both;Either input or output, but not both;– FF FF >>> >>> The number of flip-flops in the circuitThe number of flip-flops in the circuit– FaultsFaults >>> >>> The number of faults in the circuit.The number of faults in the circuit.


Table 2. Characteristics of the circuitsTable 2. Characteristics of the circuits


Table 3 shows the detailed results of the Table 3 shows the detailed results of the analysis of STG2analysis of STG2

The definitions are as follows:The definitions are as follows:– TimeTime

The sum of the test-generation time in The sum of the test-generation time in seconds for all the target faults;seconds for all the target faults;

– Detected/Untestable/DroppedDetected/Untestable/Dropped The number of tests in each category;The number of tests in each category;

– EfficiencyEfficiency The sum of detected and untestable faults divided by The sum of detected and untestable faults divided by

the total faults.the total faults.


Table 3. Results for STG2


Table 4 compares efficiency and time for all three Table 4 compares efficiency and time for all three test generators.test generators.

As we can see from the results, STG2 spent more As we can see from the results, STG2 spent more time than STG1.5 for circuits c499 and c880, but time than STG1.5 for circuits c499 and c880, but overall, as the number of gates and faults in the overall, as the number of gates and faults in the circuit increase, the efficiency of STG2 is much circuit increase, the efficiency of STG2 is much higher than that of STG1.5, with a lower time factor higher than that of STG1.5, with a lower time factor as well.as well.

The latter observation leads us to the conclusion that The latter observation leads us to the conclusion that test-generation overall time is much better using test-generation overall time is much better using STG2, thus was chosen for incorporation in Gentest.STG2, thus was chosen for incorporation in Gentest.


Table 4. Comparison for STG1, STG1.5 and STG2

Experimental ResultsExperimental ResultsGentest Analysis (1)Gentest Analysis (1)

Another set of experiments were carried out Another set of experiments were carried out on a Sun 3/60 workstation, using the Gentest on a Sun 3/60 workstation, using the Gentest test generation algorithmtest generation algorithm

The set of circuits implemented this time vary The set of circuits implemented this time vary from the previous ones, but still are from the previous ones, but still are represented by the same characteristics as the represented by the same characteristics as the previous ones (See table 5, for a brief previous ones (See table 5, for a brief reference).reference).


Table 5. Characteristics of the circuits


Table 6 shows the detailed results of the analysis of Table 6 shows the detailed results of the analysis of GentestGentest

The definitions are as follows:The definitions are as follows:– TimeTime

The sum of the test-generation time, fault-simulation time and The sum of the test-generation time, fault-simulation time and communication time between the CPU and the circuit in seconds for communication time between the CPU and the circuit in seconds for all the target faults;all the target faults;

– Trial/Untestable/SequencesTrial/Untestable/Sequences The number of tests or sequences in each category;The number of tests or sequences in each category;

– Vectors/DetectedVectors/Detected The number of vectors is the size of the final test sequence, while The number of vectors is the size of the final test sequence, while

the detected column lists the faults detected by CSim;the detected column lists the faults detected by CSim;– Fault CoverageFault Coverage

The sum of untestable faults identified by STG2 and detected faults The sum of untestable faults identified by STG2 and detected faults identified by Csim, divided by the total number of faults.identified by Csim, divided by the total number of faults.


Table 6. Results for Gentest


Observations of the results are as follows:Observations of the results are as follows:– The number of sequences generated by STG2 is always The number of sequences generated by STG2 is always

much smaller than the faults detected by CSim;much smaller than the faults detected by CSim;– The number of runs needed by STG2 to identify all the The number of runs needed by STG2 to identify all the

untestable faults cannot be reduced, hence is on the critical untestable faults cannot be reduced, hence is on the critical path of the total test-generation time;path of the total test-generation time;

– The CPU time limit was set to two seconds per fault, thus for The CPU time limit was set to two seconds per fault, thus for circuits “logic6” and “mickey”, the fault coverage was very circuits “logic6” and “mickey”, the fault coverage was very low due to the amount of target faults in these circuits; andlow due to the amount of target faults in these circuits; and

– The total average fault coverage did increase as the Gentest The total average fault coverage did increase as the Gentest algorithm was applied, as opposed to the results in table 3, algorithm was applied, as opposed to the results in table 3, which showed the circuits after STG2 alone was applied.which showed the circuits after STG2 alone was applied.

Paper ConclusionsPaper Conclusions

Gentest has proven to be a very efficient Gentest has proven to be a very efficient automatic test-generation system for automatic test-generation system for sequential circuitssequential circuits

It minimizes the total time needed for test-It minimizes the total time needed for test-generation, as well as maximizes the efficiencygeneration, as well as maximizes the efficiency

Gentest also demonstrates an improved, but Gentest also demonstrates an improved, but not ideal, test fault coveragenot ideal, test fault coverage

Future WorkFuture Work Future work on test-generation algorithms will Future work on test-generation algorithms will

concentrate on large functional units, and more concentrate on large functional units, and more complex circuitriescomplex circuitries

To do so, the test-generation process has to be To do so, the test-generation process has to be sped up, through the use of high-level models or sped up, through the use of high-level models or functional units, such as instantiating behavioral functional units, such as instantiating behavioral models of a circuit (e.g. ALU, shift register, models of a circuit (e.g. ALU, shift register, binary counter), rather than their gate- or even binary counter), rather than their gate- or even switch-level implementationsswitch-level implementations

Such an algorithm had not yet been well definedSuch an algorithm had not yet been well defined

Author BiographiesAuthor Biographies

gentest: an automatic test-generation system for sequential circuits

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