fvtx ll1

04/22/23 J. Lajoie - FVTX LL1 Collaboration Mtg. 1

FVTX LL1• What should an FVTX LL1 do?

– Goals of an FVTX LL1– Relationship to the Forward Muon Trigger Upgrade

• The Forward Muon Trigger Upgrade– Basic Design– Simulation– pp Rejection (W physics)– HI Rejection (Inv. Mass Trigger)

• Adding the FVTX LL1– FVTX LL1 Algorithm– Hardware– Simulations Required…


MuID LL1 Rejections• Heavy flavor physics in the muon arms currently limited

by the MuID LL1:

MuID 1-DeepTrigger

AchievedRejection

Rejection Needed in

2008

Rejection Needed for

RHIC-II

p+p 478 478*21 478*71

Au+Au 5 5*15 5*116

MuID LL1Trigger

AchievedRejection

Rejection Needed in

2008

Rejection Needed for

RHIC-II

p+p(1D1S)

23,500 <23,500 23,500*1.4

Au+Au(2-Deep)

15.7 15.7*5 15.7*37

Single Muon Physics (from the proposal)

Dimuon Physics (from the proposal)

NEED


What can the FVTX LL1 add?• An FVTX LL1 can contribute to three main types of

triggers:– Event trigger for Min-Bias and Ultraperipheral physics– Displaced single tracks for open charm and beauty– Pair trigger for J/, B -> J/ and upsilon production

• The FVTX LL1 can’t do it alone – You need the muon arm to select muons for the latter two

triggers• There’s no way you’ll get the needed rejection otherwise

– Need momentum selectivity– Existing MuID LL1 extremely sensitive to beam backgrounds.


Forward Muon Trigger Upgrade


Trigger Rate and Rejection (W Physics)

HQ signal

momentum dist. At vs=200 GeVDesign Luminosity√s = 500 GeV σ=60mb L = 2x1032/cm2/s

Total X-sec rate ＝ 12MHz

DAQ LIMIT=1-2kHz （ forμarm ）

Required RF~ 10,000

5025Momentum GeV/c

PT>10GeV/c

PT>20GeV/cW signal

REAL DATA

Need Momentum Selectivity in the LVL-1 Trigger!


RPC1(a+b)MuTr St. 1

RPC2

3strip

Trigger Algorithm

Candidates found by matching RPC1/2 hits within angular range. Momentum cut made by matching hit in MuTr station 2 within three cathode strip2 of RPC projection.

(MuID LL1 1D Trigger also required.)

(RPC3 hit also required in three inner theta rings)


Detector Setup – Run 10


Detector Setup – Run 12


Simulation Framework• Framework designed to permit integrated trigger studies with new

upgrade detectors– Steering routine “ForwardTriggerSim.C”

• Additional objects for each trigger system– MuID LL1

» Same hardware simulator used in online monitoring (Mutoo input added)– MuTrRPC LL1

» Combined MuTr+RPC LL1 trigger algorithm– MuTrLL1

» Based on Aoki’s code– NCC LL1

» Basic algorithms for 2x2, 4x4 and flying 8x8 in place– FVTX LL1

» Under development…

• All code in CVS – Look in offline/analysis/MuonTriggerUpgradeSim


pp Minbias Events @ 500 GeV• Regenerated pythia pp minbias events at ISU

– 997,000 events generated in total• Minbias pythia configuration

– Run through pisa including all forward detectors:• BBC, MuID, MuTr, NCC, MuRPC’s, FVTX

– Converted to DST’s for analysis • 1,000 events per DST

• All DST’s stored locally at ISU– Quick access to events

• Run through full event sample in ~2hrs


“Baseline” Rejections/Efficiency

• Based on 997,000 pythia pp events @500GeV.• Rejection factors are combined for both muon arms.• Additional rejection possible with small loss in

efficiency

RPC1/2 Angle Cut:

MuRPC+ST2|strip|<=3

Single Muons (25 GeV)

EFFICIENCY

MuRPC+ST2|strip|<=3CLUSTERS

10Hz/cm2 Noise

MuRPC+ST1+ST2

|strip|<=3CLUSTERS

10Hz/cm2 Noise(RPC1->ST1)

2 degree cut 95% N / 92% S 17,800 14,0003 degree cut 98% N / 96% S 11,726 9,000


Rejection vs. RPC Noise Rate

10,000

Error bars on rejection are

statistical only.No MuTr St2 noise

included

North Arm

South Arm

Both Arms


HI Triggering• Can the same trigger be extended to be useful as a

J/trigger at RHIC-II? – Widen the MuTr ST2 strip cut

• Select lower momentum muons– Sort candidates by sign of charge

• Use sign of strip

– Use correlation between pZ and strip• Lookup table to generate pZ

• Theta/phi at RPC2 to get pX, pY

– Combine opposite sign candidates to get invariant mass• Breaks the octant boundary!

– Can we do this in hardware?

– Set invariant mass windows for triggering


Single J/ events• Efficiency ~60% in each arm

– Dominated by same octant requirement (~80% without)

Invariant Mass (GeV/c2) Invariant Mass (GeV/c2)

Invariant mass resolution ~600MeV


Rejection via HIJING• Trigger rejection estimated using HIJING/double-HIJING

events– Mass window 2.2 to 4 GeV (2.2 to 4.2 GeV)

MuID LL1 Seed

TriggerMuID LL1

SINGLE HIJING

MuRPC+ST2

CLUSTERS10Hz/cm2 Noise

SINGLE HIJING

MuID LL1

DOUBLE HIJING

MuRPC+ST1


DOUBLE HIJING

1D 5.6 12 2.4 41D1S 7.3 13 2.5 4

2D 36 47 6.5 8


Invariant Mass Background

Invariant Mass (GeV/c2)

Rel

ativ

e Y

ield

NorthSouth

(from Double-HIJING Events)

Upsilon trigger?


MuID LL1 Symset Matching• Improve trigger rejection by explicit matching to hit MuID

LL1 symsets– Will require redesign/implementation of existing MuID LL1 trigger

MuID LL1 Seed

TriggerMuID LL1

SINGLE HIJING

MuRPC+ST2


SINGLE HIJING

MuID LL1

DOUBLE HIJING

MuRPC+ST1


DOUBLE HIJING

2D 36 94 6.5 27

(Could also be implemented with a 1D1S seed trigger)


MuTr LL1 Channel Count

Arm St1 St2 St3 Octant TotalNorth 96ch / octant 192ch

/octant320ch

/octant608ch

/octantSouth 96ch /octant 160ch

/octant256ch

/octant512ch

/octant

Arm St1 St2 St3 Octant Total TotalNorth 1 /octant 1 /octant 2 /octant 4 /octant 32 /armSouth 1 /octant 1 /octant 2 /octant 4 /octant 32 /arm

Fiber Counts (@ 2.5Gbit) :

Channel Counts:

Fibers will come off the detector at 1.25Gbit (96 bits) and combined to 2.5 Gbit fibers (192 bits).

NOTE: MuTr clustering to be done at FEM level.


RPC LL1 Channel Count

Arm RPC1a RPC1b RPC2 RPC3North 192ch /

octant192ch

/octant256ch

/octant192ch

/octantSouth 192ch

/octant192ch

/octant256ch

/octant192ch

/octant

Arm RPC1a || RPC1b RPC2 RPC3 Octant Total TotalNorth 1 /octant 2 /octant 1 /octant 5 /octant 40 /armSouth 1 /octant 2 /octant 1 /octant 5 /octant 40 /arm

Fiber Counts (@ 2.5Gbit) :

Channel Counts:

RPC channel counts assume channels OR’d in pairs of rings at FEM level, highest channel count in pair used.

Assume RPC1a and RPC1b OR performed at FEM level:


VMELogic

Virtex-4FX20/40

xcvrxcvrxcvrxcvrxcvrxcvrxcvrxcvrxcvrxcvrxcvrxcvr

P1

P0

P2

P3

Virtex-4FX20/40

12 x 2.5Gbit serial lines available

1 x 2Gbit serial line(Aurora protocol)

(4 daughtercards total) Virtex-4Event

Readout

32 bits LA/LD, clock control

(RPC1,2,3 @ 2.5Gbit)

(MuTr St2 @ 2.5Gbit)

12 fibers per octant maximum



(One board is 4 octants.)(9 fibers per octant)


LL1 Board Layout

70mm x 250mm

Fiber Receivers


Optical Connect

• Using new high-density optical (receive only) connections– Agilent AFBR 732/742 series

(12 inputs)– 2.5Gb/s on each input


Level-1 Electronics Development• Redeveloped VME Interface

– Existing interface logic (Cypress 960/4) EOL– Option to use commercial FPGA core replacement custom ASICS

developed for military applications• Decided to purchase FPGA core ($6K)

– Millogic 960/964 cores implemented, debugged and tested on Xilinx prototyping board wired in to VME crate, including multi-chip capabilities.

• Exploring Xilinx Virtex-4/5– Integrated multi-Gbit serial interfaces

• Eliminates need for interface logic, complicated/dense bus• Simplifies inter-chip communication

– This is a departure from just revising the MuID LL1 board design• Current design doesn’t scale well with new technologies• Some existing problems extremely difficult to solve

– Bus termination


Development and Schedule• Plan to pursue through Spring/Summer:

– Virtex-4/5 development and testing • Purchased development board w/Cu and XCVR interfaces• “Loopback” serial connections for chip-to-chip comm. development• Use this as a platform to develop/test FPGA code for final board

– Produce/populate a prototype board (Summer 2007)• Simple design, attention to serial link traces• Take advantage of learning cycle from development

– Build the final hardware as late as possible in the development cycle

• Schedule– Prototype LL1’s : Summer 2007– LL1 Design Review : November 2007– LL1 Production: Spring 2008


Adding the FVTX LL1…


FVTX LL1 Revisited• What will the FVTX LL1 have to do:

– Determine the event vertex• Combine hits with linear correlation coefficient ~1

– For a solenoidal field a fit to tracks in ,z is a straight line– Track list contains slope, intercept for fit, z(=0)

» Histogram z(=0) for each track» Better yet, intersect pairs of lines (nonzero for beam spot)

– Correlation coefficient calculation could be integer• Octant-by-octant? Or can each octant determine its own vertex?

– Needs to be studied in simulation» Answer likely different for p+p, Au+Au

• Histogram determines event vertex– Sort track list for displaced vertices

• Calculate (zVTX) for all tracks• Floating point or integer?

B

z


Linear Correl. CoefficientQuick check – MC hits in FVTX from same MC track ID, sorted by pT (AuAu Hijing events)

400<pT<600 MeV

200<pT<400 MeV

600<pT<800 MeV

r=1 – straight line

i iii

iii

zz

zzr

22 )(*)(

)(*)(


Displaced Vertices

• Want tight LOWER

– Consistent with resolution, keep most charm/beauty decays• Momentum dependent?

• Want tight UPPER

– Consistent with c~300-500um– Eliminate pion decays

• Again, should this be momentum dependent?

UPPERLOWER


Track Matching• Match tracks in the FVTX and Muon Forward Trigger

using hit locations in the last plane of the FVTX and the inner plane of the Muon Forward Trigger (MuTr ST1 or RPC1a,b)

X

X

thet

a

phi

FVTX LL1Muon Forward LL1

phith

eta

MomentumRanges


FVTX LL1 Hardware• Can we utilize the hardware being developed for the

Muon Forward Upgrade for the FVTX LL1? – STTR hardware development will use the daughtercard format

• 10 Fibers/ROC (one wedge)– What’s the low momentum cutoff if we track in one wedge? – Can we pack more data into faster fibers?

• FPGA daughtercard can contain:– Two high-density FPGA’s

» Embedded PPC’s a plus for this application– High-speed memory (several GB)

– Like to try a prototype of the daughtercard design with the LDRD• Proof-of-principle of a lot of key concepts


Simulations…• Lots of simulation work needs to be done:

– Establish vertex finding algorithm• Study pT cutoff and efficiency as a function of slice width• Study sharing of vertex information

– Do all slices need to share vertex information?

– Study displaced vertex cuts• Should UPPER, LOWER be a function of momentum?

– Do we win with this or does the addedd complication hurt?

– Study track matching with Muon Forward Trigger• What momentum windows are required

– Combine with Muon Forward Trigger• Study single, dimuon triggers

– Efficiency and rejection in p+p, Au+Au…


BACKUP


MuTR LL1 Simulations • I took a copy of Aoki’s code and created a module that

hooks into the forward simulation framework– It’s greatly modified, so mistakes are mine, not Aoki’s– Run algorithm on same events, only parameter is strip cut– Resolution, etc., is set by MUTOO response chain

Strips atStation 1

Strips atStation 3

Strips atStation 2

acceptstrip :Sagitta at station 2 strip<=1

Cathode clustering, uses peak strip


MuTr LL1 Rejections

MuIDLL1 required to fire, no geom. matchRejection factors combined for both armsComparable to Aoki’s results from Aug. 2005 meetting.(uses PEAKSTRIP not CENTERSTRIP)

500 GeV pp minbiasStrip Eff. (15 GeV muons)

Rejection Factorstrip = 0 68% 249,428

strip = 1 98.6% 25,582

strip = 2 98.6% 12,791

strip = 3 98.6% 8,178


RPC Clusters

• RPC cluster size using data from Colorado– Implemented cluster width using fit by Andy Glenn

• MC yields good fit to observed cluster size distribution– Fit test bench data assuming a hit-inducing Gaussian radius

• Extendible to arbitrary pad sizes.

RPC1a RPC2 RPC3

Cluster Size (in number of RPC strips)


Fiber Data Rates• Data rate on fibers assumes 8b/10b

encoding, 16-bit words, two header words (frame header and clock counter)

– The data rate on the fiber is then given by:

– N is number of data frames

N bits Rate (Gb/s)

16 256 3.318

15 240 3.133

14 224 2.949

13 208 2.765

12 192 2.580

11 176 2.396

10 160 2.212

9 144 2.028

8 128 1.843

)Ghz0096.0(2.1)2(bits16Rate N

Nominal 2.5Gbit fiber.


Logic Estimate• Assume the logic required scales like the number of

input bits, scale MuID LL1 logic required:– 1920 bits for MuID LL1, processed in five XCV2000E chips

• 38,400 logic cells• At best 21% utilization

– 1248 bits for MuTr+RPC LL1, to be processed in one chip• Assume we can go to 50% occupancy• Require 38,400*5*(1248/1920)*(21/50) = 52,416 logic cells

– Possible Xilinx Options: • Virtex-4:

– XC4VFX60 (12 Rocket I/O, 56,880 logic cells) – XC4VFX100 (16 Rocket I/O, 94,896 logic cells)

• Virtex-5:– XC5VLX85T (12 Rocket I/O, 82,944 logic cells)– XC5VLX110T (16 Rocket I/O, 110,592 logic cells)


Hi-Tech PCIE-SYS60PCIe Module with multiple hardware and RocketIO Serial connections. Uses SFP Optical Modules (Finisar)

Loopback connection using these two

transceivers – allows testing of RocketIO

MGT’s.


Rocket I/O + Chipscope

Frame errors – 125MHz clock too slow (156Mhz min).


RPC1a RPC1b RPC2 RPC3

theta (deg) Radius width radius width radius width radius width

possible 5280.2 5231.7

34.36 933.2 773.1 1016.8 842.3 4675.4 3873.2

ring 8

strips: 181.4 x 12.1 (64) strips: 197.7 x 13.2 (64)

strips: 467.9 x 60.5 (64)

31.60 4207.5 3485.6

ring 7 strips: 441.0 x 60.5 (58)

28.84 751.8 622.8 819.1 678.6 3766.5 2120.3 4991.4 4135.0

ring 6

strips: 164.3 x 9.7 (64) strips: 177.7 x 10.6 (64)

strips: 418.2 x 48.8 (64) strips: 554.2 x 64.6 (64)

26.09 3348.3 2773.9 4437.2 3675.9

ring 5 strips: 298.9 x 48.8 (57) strips: 528.6 x 64.6 (57)

23.33 588.7 487.7 641.4 531.4 2949.4 2443.4 3908.6 3238.0

ring 4

strips: 151.1 x 15.2 (32) strips: 163.5 x 16.6 (32)

strips: 382.7 x 38.2 (64) strips: 507.1 x 50.6 (64)

20.57 22566.8 2126.4 3401.5 2817.9

ring 3 strips: 369.1 x 38.2 (56) strips: 493.3 x 50.6 (56)

17.81 438.7 363.4 477.9 395.9 2197.7 1820.6 2912.3 2412.7

ring2

strips: 141.0 x 11.4 (32) strips: 153.6 x 12.4 (32)

strips: 357.8 x 28.4 (64) strips: 474.2 x 37.7 (64)

15.06 1839.8 1524.2 2438.1 2019.8

ring1 strips: 3548.7 x 28.4 (54) strips: 462.1 x 37.7 (54)

12.30 297.6 246.6 324.3 268.6 1491.1 1235.3 1976.1 1637.0

possible 1468.4 1926.4

split gap: ring 4 and 5 split gaps: ring 2 and 3 + ring 6.and 7 no split gaps no split gaps

RPC dimensionsall units in mm (except theta)

strip length and width consider full acceptance in theta and phi in the octants (i.e. no loss due to readout and boxes)strip widths are determined at the outer radius of two paired rings

fvtx ll1

Documents

upsilon productionthe

fvtx ll1relationship

fvtx ll1what

event trigger

trigger rate

trigger algorithmcandidates

beautypair trigger

forward muon trigger