future trends in microelectronics – impact on detector readout final.pdfedwin hubble. detector...

Future Trends in Future Trends in Microelectronics Microelectronics –– Impact on Impact on

Detector ReadoutDetector ReadoutPaul O’Connor

Detector Development Symposium Paul O'Connor BNL April 5, 2006 2

OutlineOutline

• CMOS Technology Scaling

• Analog Circuits

• Radiation Effects

• Cost


Edwin HubbleEdwin Hubble


Gordon MooreGordon Moore


CMOS Logic ElementCMOS Logic Element• Pair of nearly-ideal switches in

series

• Complementary polarity ⇒common control voltage

• input impedance ~ ∞

• VDD-tolerant

• Zero static power

VDD


MOSFET ScalingMOSFET Scaling

• Voltages, dimensions reduced by α• Results:

αα

/ Speed

1 eCapacitanc

const. / eConductancconst.

CVI

VIE =r

const. density Power Density

1 Power/gate

1 energy Switching

2

22

32

αα

α

fCV

CV

20V 4V


Industry Scaling RoadmapIndustry Scaling Roadmap

• New generation every ~2 years with α = √2

• Lg (1970) 8 µm (2007) 18 nm

180


Transistor CountTransistor Count

Year

40048008

8080

8086

80286Intel386

Intel486Pentium

Pentium ProPentium II

Pentium IIIPentium 4

1970 1975 1980 1985 1990 1995 2000

MO

SF

ET

s

103

106

109

2.5e4


4004

8008

8080

8086

80286

Intel386

Intel486

Pentium

Pentium Pro/II/III

Pentium 4

Year

1970 1975 1980 1985 1990 1995 2000 2005

CPU Clock FrequencyCPU Clock FrequencyH

z

106

108

107

109

4e3


Transistor CostTransistor Cost$

100

10-3

10-6

Year

3e6


Digital State of the ArtDigital State of the Art

• 65 nm node: – SRAM test chip Nov. 2003

– production Nov. 2005

– “crossover” 3Q 2006

• 45 nm node: – 153MB SRAM Jan. 2006

– >109 MOSFETs

– production 3Q ‘07


Failures of Classical ScalingFailures of Classical Scaling

• ignores kT• ignores mobility degradation and velocity

saturation

• ignores fringing capacitance

• ignores tunneling

• ignores atomistic effects

• ignores industry economics


kTkT ≠≠ 00

• MOSFET in weak inversion when Vgs < Vth:

nkTqV

offnkT

VVq

D

THTHGS

eIIeII−−

=⇒= 0

)(

0

VDD

kT

• Can’t continue to scale VTH

• Tradeoff of speed for leakage current (static power)

• Multi-VTH processes

VTH

fast

low power


Gate tunneling currentGate tunneling current• Significant tunneling through

SiO2 when tox < 3nm

• Jtunnel increases 100X per generation

• Replace SiO2 with high-κdielectric (?)

• Multi-tox processes

κκ ε

ε

−−=

hi

SiOhitEOT 2


Atomistic EffectsAtomistic Effectsrandom dopantdistribution

oxide thickness variation

line edge roughness

σVTH, RTS σVTH, σJtunnel, σµ σVTH

A. Asenov, IEEE Trans. Electron Dev. 50(9), 1837 (2003)


Scaling in PracticeScaling in Practice• Until 180nm node:

– follow classical scaling with α = √2– 2.8X performance per generation

• Now:– continue (super) scaling Lg

– sub-scaling of tox

– VDD, VTH have stopped scaling• Gate density and speed continue

to scale• Increase of E, conductance• Switching energy decreases only

by 1/α not 1/α3

• Power density increase ~ α• Static power from leakage, gate

tunneling make power problem worse

SiO2 latticeconstant

3 kT/q


Power is biggest impediment to Power is biggest impediment to further scalingfurther scaling

LG-1

LG-4

E. Nowak, IBM J. Res. & Dev. 45(2), 169 (2002)


M. Bohr, Intel, 2003 IEDM

E. Gusev et al., IBM, 2004 IEDM

F.-L. Yang et al., IMEC, 200 VLSI Symp.

S. Thompson, Intel,IEEE T-ED 51(11), 1790 (2004)

NextNext--generation Transistorsgeneration Transistors

M. Ieong, IBM, Sol. State and IC Tech. 2004

Strain Engineering• Reduce mobility degradation

UTSOI, DG-FET• Suppress SCE through improved electrostatics

High-k gate dielectric• Suppress Jtunnel


SiGeSiGe HeterojunctionHeterojunction Bipolar Bipolar Transistor (HBT)Transistor (HBT)

• Power-performance ~ 2X standard CMOS at same feature size

• Cost also ~ 2X

• Provides 3 – 4 year “head start”over CMOS

• Eventually CMOS provides better cost-performance


Analog: Speed, Gain & MatchingAnalog: Speed, Gain & Matching• Speed/intrinsic gain tradeoff

– fT ~ 1/LG for min-LG devices– Output conductance gds sensitive to geometry

and bias– Gain gm/gds severely degraded in ultra-scaled

devices:• failure to adhere to classical constant-E scaling

• Threshold Mismatch– Dopant fluctuations:– Overcome by increasing W*L– Power penalty

ασ ~min, −∆ LGVTH

Pelgrom, Philips, 1998 IEDM

0

50

100

150

200

250

250 180 130 90 65

Technology Node, nm

f T, G

Hz

0

5

10

15

20

fT

gm/gds

g m/g

ds

f T, H

z

P, W10-6 10-4 10-2

107

108

109

1010

1011

250nm

65nm

130m


Analog LowAnalog Low--VVDDDD ChallengesChallenges• Increasing ratio of VTH/VDD rules out use of many classical analog

design toplogies, e.g. cascodes.• To achieve same performance at lower VDD, analog circuits need

increased power.

(performance limited by thermal noise)

A. Annema et al., IEEE JSSS 40(1), 132 (2005)

0.1 1Min. Feature Size, um

103

104

Dyn

am

ic R

an

ge

10 uW100 uW1000 uW

SNR, BW held constant Power held constant

100X Power4X SNR


Noise in scaled CMOSNoise in scaled CMOS• For CSA, consider noise in relation to gate capacitance• Thermal noise improvement from higher fT:

– ENCth ~ √1/α• 1/f noise depends on interface trap density, device area, inversion charge density –

– no consistent trend with scaling• Choice of L,W for minimum noise needs to account for moderate inversion operation• Gate leakage current shot noise (parallel)

G. Anelli 2005

0.01 0.1 1100

200

300

400 TECHNOLOGY SUPPLY COST/RUN

0.35µm 3.3V 14k$ 0.25µm 2.5V 19k$ 0.18µm 1.8V 32k$

En

erg

y R

esol

utio

n [

EN

C]

Preamplifier Power [mW]

P O'Connor and G. De Geronimo, Prospects for charge sensitive amplifiers in scaled CMOS, NIM A480, 713 (Mar. 2002)

EN

C (

rms

e- )


Radiation Tolerant InverterRadiation Tolerant Inverter

metal 1 polysilicon

p+ guard ring

NMOS Enclosed Layout Transistor (ELT)

VDD

n+ diffusion p+ diffusion

PMOS

contact to diffusion

DRAIN

DRAIN

GATE

SOURCESOURCEGATE IN

OUT


Radiation Effects below 0.25Radiation Effects below 0.25µµmm• Thinner gate oxides more

tolerance to Total Ionizing Dose

• Thick field oxide charging – edge leakage in NMOS– loss of isolation NWELL-

NWELL• 0.13µm IBM technology harder

than 0.25µm:– non-ELT devices OK except

narrow/thick-oxide NMOS– to 70 Mrad+– lateral isolation OK, no guard

ring needed– SEU cross section higher,

lower critical charge– No radiation-induced SEL

ELT

non-ELT

F. Faccio, CERN, FEE Workshop Snowmass 2003


FabFab Line CostLine Cost

http://www.tf.uni-kiel.de/matwis/amat/elmat_en/index.htmlElectronic Materials© Prof. Dr. Helmut FöllUniversity of Kiel; Faculty of Engineering

$B


Mask Set and Fabrication CostMask Set and Fabrication Cost

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.5um 0.35um 0.25um 0.18um 0.13um

Technology

Cost/run ($M)

Cost/mm^2 ($)

Technology

0

0.2

0.4

0.6

0.8

MASK SET ENGINEERING RUN

$M


Example Example -- BNL ASIC Design BNL ASIC Design GroupGroup

• Develops Low Noise FEE for gas and semiconductor detectors– accelerator experiments– medical imaging– astrophysics– homeland security

• 70% Federal, 30% commercial• Staff

– 5 ASIC professionals– 1 DAQ engineer– 1 Technician

• CAD suite and test labs• 7 – 8 runs/year through MOSIS

– 0.35, 0.25, and 0.18um mixed-signal CMOS– 5K – 600K MOSFETs per chip– $20K – $80K per MPW run

• Development cost per design ~ $200K x no. revisions needed


SummarySummary• Power dissipation is the major obstacle to further CMOS

scaling.

• Foundry and mask costs going up as process options (multi-Vth, multi-tox, HBT, passives, etc.) added for SOC.

• Analog design is compromised by the low supply rail.

• Except for high radiation resistance and packing density, ultra-scaled technologies offer few advantages to justify their enormous cost.

• Plenty of opportunity to innovate in (n-4)-generation CMOS.


Bon AppBon Appéétit!tit!

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