functions and tasks in verilog

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Functions & Tasks ANINDRA

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Page 1: Functions and tasks in verilog

Functions &

Tasks

ANINDRA

Page 2: Functions and tasks in verilog

Functions

Tasks

Function vs Tasks

Page 3: Functions and tasks in verilog

Functions:-

This is used for reusability of code.

Decreases the size of the program(where the same statements are

used for many times).

This functions are used for combinational circuits only.

In this functions no delay is used.

There is no nonblocking assignments.

Page 4: Functions and tasks in verilog

Functions (cont’d..) a function can enable another function but not another task.

Function executes always at 0 simulation time.

In functions not only delay and also there is no event or

timing control statements.

Function must have at least one input argument. They can

have more than input.

Function always return a single value.

Page 5: Functions and tasks in verilog

Funtions (cont’d….) They cannot have output or inout arguments.

This contains only behavioral statements only.

This not contain always and initial but are called from always blocks , initial block.

In this no wires are used.

Functions have local variables , registers , time variables , integers , real , or events.

Page 6: Functions and tasks in verilog

Functions(cont’d…) The keywords are function and endfunction.

The function is declared as follows :

<function>

function <range_or_type>? <name_of_function> ;

<tf_declaration>+

<statement_or_null>

endfunction

Page 7: Functions and tasks in verilog

Function(cont’d…) <range_or_type>

<range>

||= integer

||= real

<name_of_function>

<IDENTIFIER>

<task and function_declaration>

||= <parameter_declaration>

||= <input_declaration>

||= <reg_declaration>

||= <time_declaration>

||= <integer_declaration>

||= <real_declaration>

||= <event_declaration>

Page 8: Functions and tasks in verilog

Functions (cont’d…)

The calling of function is as follows:-

<function_call>

<name_of_function> ( <expression> <,<expression>>* )

<name_of_function>

<identifier>

Page 9: Functions and tasks in verilog

Tasks :-

A task can be enable other task and functions.

Tasks may executes in non-zero simulation time.

Task may contain delay , event , or timing control statements.

Tasks may have zero or more arguments.

In this input , output , inout are used.

Tasks do not return with a value , but can pass multiple values through output and

inout arguments.

Page 10: Functions and tasks in verilog

Tasks (cont’d…)

In this both comb and seq circuit are designed.

This also contains only behavioral statements.

No always and initial but called from always block ,

initial blocks ,other tasks and function.

Keywords are task and endtask are used.

Page 11: Functions and tasks in verilog

Tasks (cont’d....)

Task syntax is declared as follows:

<task>

task <name_of_task> ;

<tf_declaration>

<statement_or_null>

endtask

Page 12: Functions and tasks in verilog

Tasks (cont’d…) <name_of_task>

<IDENTIFIER>

<tf_declaration>

||= <parameter_declaration>

||= <input_declaration>

||= <output_declaration>

||= <inout_declaration>

||= <reg_declaration>

||= <time_declaration>

||= <integer_declaration>

||= <real_declaration>

||= <event_declaration>

Page 13: Functions and tasks in verilog

Tasks (cont’d…) Task will be called as follows:

<task_enable>

<name_of_task> ;

<name_of_task> ( <expression> <,<expression>> ) ;

Page 14: Functions and tasks in verilog

Functions vs Tasks:-

Page 15: Functions and tasks in verilog

Thank you