functions and tasks in verilog
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Functions &
Tasks
ANINDRA
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Functions
Tasks
Function vs Tasks
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Functions:-
This is used for reusability of code.
Decreases the size of the program(where the same statements are
used for many times).
This functions are used for combinational circuits only.
In this functions no delay is used.
There is no nonblocking assignments.
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Functions (cont’d..) a function can enable another function but not another task.
Function executes always at 0 simulation time.
In functions not only delay and also there is no event or
timing control statements.
Function must have at least one input argument. They can
have more than input.
Function always return a single value.
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Funtions (cont’d….) They cannot have output or inout arguments.
This contains only behavioral statements only.
This not contain always and initial but are called from always blocks , initial block.
In this no wires are used.
Functions have local variables , registers , time variables , integers , real , or events.
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Functions(cont’d…) The keywords are function and endfunction.
The function is declared as follows :
<function>
function <range_or_type>? <name_of_function> ;
<tf_declaration>+
<statement_or_null>
endfunction
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Function(cont’d…) <range_or_type>
<range>
||= integer
||= real
<name_of_function>
<IDENTIFIER>
<task and function_declaration>
||= <parameter_declaration>
||= <input_declaration>
||= <reg_declaration>
||= <time_declaration>
||= <integer_declaration>
||= <real_declaration>
||= <event_declaration>
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Functions (cont’d…)
The calling of function is as follows:-
<function_call>
<name_of_function> ( <expression> <,<expression>>* )
<name_of_function>
<identifier>
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Tasks :-
A task can be enable other task and functions.
Tasks may executes in non-zero simulation time.
Task may contain delay , event , or timing control statements.
Tasks may have zero or more arguments.
In this input , output , inout are used.
Tasks do not return with a value , but can pass multiple values through output and
inout arguments.
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Tasks (cont’d…)
In this both comb and seq circuit are designed.
This also contains only behavioral statements.
No always and initial but called from always block ,
initial blocks ,other tasks and function.
Keywords are task and endtask are used.
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Tasks (cont’d....)
Task syntax is declared as follows:
<task>
task <name_of_task> ;
<tf_declaration>
<statement_or_null>
endtask
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Tasks (cont’d…) <name_of_task>
<IDENTIFIER>
<tf_declaration>
||= <parameter_declaration>
||= <input_declaration>
||= <output_declaration>
||= <inout_declaration>
||= <reg_declaration>
||= <time_declaration>
||= <integer_declaration>
||= <real_declaration>
||= <event_declaration>
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Tasks (cont’d…) Task will be called as follows:
<task_enable>
<name_of_task> ;
<name_of_task> ( <expression> <,<expression>> ) ;
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Functions vs Tasks:-
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Thank you