floating point representation and digital logic · digital logic lecture 11 cs301. administrative...
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Floating Point Representation and
Digital Logic
Lecture 11CS301
Administrative
• Daily Review of today’s lecturew Due tomorrow (10/4) at 8am
• Lab #3 due Friday (9/7) 1:29pm• HW #5 assigned
w Due Monday 10/8 at 5pm• Program #1 assigned
w Due Thursday, 10/18 at 11:59pm• Read Appendix C.1-C.3, C.5
Digital Logic
(How do we construct a processor?)
Multi-Million Transistor Chips
Intel Core i7 Extreme Edition - 731 million transistors, 263 mm^2 area
MOS Semiconductor Transistors
P-type silicon: Excess positive charges (electron holes)
N-type silicon: Excess negative charges (electrons)
Oxide: Insulator
Gate: Metal pad In this state, current (electrons) cannot flow between source and drain – switch is OPEN
Silicon Bulk (p-type)
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Gate n-type Si
n-type Si
Source Wire Gate Wire
Oxide
Drain Wire
MOS Semiconductor Transistors
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Gate n-type Si
n-type Si
Source Wire Gate Wire
Oxide
+5V
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Place a positive charge on the gate wire (gate = +5V)
The gate’s positive charge attracts negatively-charged electrons
This row of electrons forms a channel connecting the Source and Drain – Current can flow – Switch is CLOSED
Drain Wire
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Transistors
• Transistorsw Emits 0 or 1 when on
or offw Can connect
transistors in series or parallel to create larger building blocks called gates
Pull-up pMOS transistor
Pull-down nMOS transistor
GND
+5V
A
Z
CMOS Inverter createdfrom two transistors
Digital Logic
• Voltages represent valuesw Logically false - 0w Logically true - 1
• Values are complements or inverses
Gates: Basic Building Blocks:
• Depending on organization of transistors, different inputs give specific outputs
• Basic gates equivalent to boolean operatorsw INVERTER or NOT, !w AND, &&w OR, ||
• Combinational logicw Outputs based on inputsw No memory
A A
A A • B B
A A + B B
Truth Tables
• Functionality fully specified by truth table
• n inputsw n input columnsw 2n input rows
• m outputsw m output columns
A Z 0 1 1 0
A B Z 0 0 0 0 1 0 1 0 0 1 1 1
A B Z 0 0 0 0 1 1 1 0 1 1 1 1
NOT
AND
OR
Combinational Logic
• Gates can be combined inw Seriesw Parallel
• Any combination of both possible A B Y Z
0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1
A A
A
B
Y
Z
Other Important Gates
• NAND
• NOR
A B Z 0 0 1 0 1 1 1 0 1 1 1 0
A B Z 0 0 1 0 1 0 1 0 0 1 1 0
A A B B
A A + B B
Universal Gates
• Any other gate can be constructed from some arrangement of universal gatesw Examples: NAND / NOR
• Important because frequently less expensive to design chips with “homogeneous” gates
Universal Gates (NAND)
• NOTA A AA 0 1 1 1 0 0
A A A
Universal Gates (NAND)
• NOT
• AND
A A AA 0 1 1 1 0 0
A A A
A B AB 0 0 0 0 1 0 1 0 0 1 1 1
Universal Gates (NAND)
• NOT
• AND
A A AA 0 1 1 1 0 0
A B AB AB
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
A A A
A A B B
Universal Gates (NAND)
• ORA B A+B
0 0 0
0 1 1
1 0 1
1 1 1
Universal Gates (NAND)
• ORA B A+B AB
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
A
B AB
For Fun: XOR
A B A⊕B 0 0 0 0 1 1 1 0 1 1 1 0
For Fun: XOR
A B A⊕B 0 0 0 0 1 1 1 0 1 1 1 0
Few Final Notes
• Gates can have more than 2 inputsw Generally keep number small due to
electrical engineering issues• Circuits that create current computers
are constructed from these basic gates
Equivalent
• Truth tables• Circuit• Boolean algebra expression
Truth tables are great for evaluating when circuit or Boolean expression evaluate to true
Combinatorial Logic: Multiplexor
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Really a selector: One of the inputs is selected by the controlC = (A * ~S) + (B * S)
Combinational Logic: Multiplexor
n:1MUX
2n inputs
n control
1 output
n control lines select which of 2n inputs goes to output n possible input lines requires ceiling(log2n) control lines. Equivalently, n control lines with 2n input lines.
1-bit MUX
AS + BS
Combinational Logic: De-Multiplexor
n:1DEMUX 2n outputs
n control
1 input
n control lines select which of 2n outputs input goes to
1 to 2 De-multiplexor
Combinational Logic: Decoder
n control lines select which of 2n outputs set to 1
2n outputs n control
1 to 8 De-multiplexor
Combinational Logic: Encoder
One of 2n inputs set to 1. Output encodes which input set to 1.
2n inputs n bit output
4 to 2 Encoder
8 to 3 Encoder
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Combinational Logic
• Comparatorw Given 2 inputs, sets output to 1 if inputs
match
Combinational Logic
• Half-Adderw No carry in
Combinational Logic
• Half-Adderw No carry in A B Sum Carry
Out 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
A⊕B AB
1-bit Full Adder
• Three inputs:w Aw Bw Cin
• Two outputs:w Sum = (A⊕B) ⊕ Cinw Cout = AB + (A⊕B) Cin
Ripple Carry Adder
• Construct n-bit adder with n 1-bit adders
• Delay is problem• Faster alternative:
w Carry-lookahead adder