flip-flops and related devices - universidad de...
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Flip-Flops and Related DevicesCH. 5 of Digital Systems by Widmer and Tocci
Flip-Flops and Related DevicesCH. 5 of Digital Systems by Widmer and Tocci
Kim, Rin-ChulDept. of ECE, Univ. of Seoul
2nd semester, 2001
Kim, Rin-ChulDept. of ECE, Univ. of Seoul
2nd semester, 2001
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
IntroductionIntroduction
Sequential logiccombinational logic + memoryoutput ∼ f ( current inputs, current states )states : binary information stored in the memory elements at anygiven time
Flip Flopbasic memory element made up of logic gates
one or more inputstwo outputs ( )two output states
Set, Reset(Clear)
, Q Q
Combinational logic
Memoryelements
inputsoutputs
FlipFlop
inputsQ
Q
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
R-S (S-C) F/F using NAND gatesR-S (S-C) F/F using NAND gates
Set /Clear(Reset)to keep previous values when S = R = 1 (memory)
Set Reset output1 1 No change0 1 Q=11 0 Q=00 0 1Q Q= =
A B AB0 0 10 1 11 0 11 1 0
1
0
0
10
0
1
1
1
0
0
1
Q
Q
Set
Reset
Q
Q
Set
Reset
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
R-S (S-C) F/F using NOR gatesR-S (S-C) F/F using NOR gates
to keep previous values when S = R = 0 (memory) invalid state( ) when S = R = 1
Set Reset output0 0 No change1 0 Q=10 1 Q=01 1 0Q Q= =
A B A B+0 0 10 1 11 0 11 1 0
1
0
0
11
1
0
0
1
0
0
1
Q
Q
Set
Reset
Q
QSet
Reset
Q Q=
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Debouncing circuitDebouncing circuit
Phenomenon of contact bounce
debouncing circuitSet Reset output1 1 No change0 1 Q=11 0 Q=00 0 1Q Q= =
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Asynchronous systemthe outputs of logic circuits can change state whenever one or more inputs change
synchronous systemthe exact time at which any output can change states are determined by a signal, called CLOCK
CLOCKrectangular pulse train or square wave
Clock signalsClock signals
Positive going edge Negative-going edge
1T
T1duty cycle TT
=
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Triggering of F/FTriggering of F/F
To trigger F/Fto switch the state of F/F by a change in the input
level trigger : to trigger when a signal is at level 0 or 1to cause a racing(multiple transition) problem ( two or more state change during triggering signal activated)a group of F/Fs sensitive to pulse duration is called a latch
edge trigger : states are changed during signal transitionpositive edge triggerednegative edge triggereda group of F/Fs sensitive to pulse transition is called a registerregister
Implementation of edge triggered F/FMaster-slave F/Fusing an edge detector
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Clocked R-S(S-C) F/FClocked R-S(S-C) F/F
Asynchronous F/F -> synchronous F/Fwhen CP=1, outputs change according to the inputswhen CP=0, outputs remains their previous states
→ level-triggered F/F
S
RCP
Q
Q
Q
Q
Set
Reset
CP
S
R
Set Reset CP Qx x 0
0Q
0 0 1 0Q
1 0 1 10 1 1 01 1 1
1Q Q= =
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Master-Slave F/FMaster-Slave F/F
Act as if it is a negative edge triggered F/Fmaster F/F : normal F/F behavior
triggered when CP=1
slave F/F : copy the results of master F/Ftriggered when CP=0
S
RCP 1Q
1Q
S
RCP 2Q
2Q
Set
Reset
CP
master F/F slave F/F
1Q
1Q
CPSet
Reset
2Q
2Q
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Edge detector for clocked F/FEdge detector for clocked F/F
Edge detectoran RC circuit to generate a spike in response to a momentary change of input signal (HPF)using propagation delay of logic gates
duration of CLK pulses is typically 2-5 nanoseconds.
CP CLKCP
CP
CP
CLK
Positive edge detector
CP CLKCP
CP
CP
CLK
Negative edge detector
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Edge triggered S-C(R-S) F/FEdge triggered S-C(R-S) F/F
Internal circuitry
F/F responding to positive(negative) edge
Q
Q
Set
Reset
CPEdge
detector
S
RCP
Q
Q
S C C L K Q0 0 x 0Q1 0 10 1 01 1 Inva lid
S
RCP
Q
Q
S C C L K Q0 0 x
0Q
1 0 10 1 01 1 In v a lid
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Clocked J-K F/FClocked J-K F/F
To convert invalid state in R-S F/F to toggle modeS C C L K Q0 0 x 0Q1 0 10 1 01 1 Invalid
J K CLK Q0 0 x 0Q1 0 10 1 01 1 0Q
Q
Q
S
C
CP Edgedetector
J
K
Pulse steeringcircuit
NANDlatch
J
KCP
Q
Q
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Clocked D F/FClocked D F/F
To avoid invalid state by connecting S and Conly one control input D, which stands for dataused for parallel transfer of binary data
Q takes on the value of D only at certain time instance Q is then used for subsequent processing
D latch(transparent latch) : level-triggered D F/Fwhen CP=0, the outputs are latched to their current levelwhen CP=1, the outputs will look exactly like D (transparent)
S
R
Q
Q
DCP
D Q
Q
D CLK Q0 01 1
D Q
QCP
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Asynchronous inputsAsynchronous inputs
Synchronous inputs : control inputs such as D, J,K, S,C the effect on the F/F output is synchronized with the CP input
asynchronous inputs(direct inputs)the output is directly affected, regardless of the conditions atother inputs including CPPRESET and CLEAR
J
KCP
Q
Q
PRESET
CLEAR
CLR PRE CLK J K Q Q’0 0 X X X Invalid0 1 X X X 0 11 0 X X X 1 01 1 0 0 memory1 1 0 1 0 11 1 1 0 1 01 1 1 1 toggle
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Timing considerationsTiming considerations
Setup time tS (Hold time tH)the time interval immediately preceding(following) the active transition of the CLK signal during which the control input must be maintained at the proper level
propagation delaythe delay from the time the signal is applied to the time when output makes its change
St Ht
Control input
CLOCK
PLHt
CLK, PRE or CLR
QPHLt
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Timing consideration(2)Timing consideration(2)
Maximum clocking frequency fMAXthe highest frequency that may be applied to the CLKf = 1/T, where T is the period
clock pulse HIGH and LOW timesthe minimum time duration that the CLK signal must remain its HIGH (or LOW) level
CLK transition timetime duration during which the CLK goes from LOW to HIGH, or vice versa≤50 nS for TTL devices≤200 nS for CMOS devices
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Each FFs are triggered by the same CLK signal
clock skewbecause of propagation delay, a clock signal may arrive at individual FFs at different timesremedy : equalizing the delays in various paths of clock signal
Clock skewClock skew
1J
1KCP
1Q
1Q
1
1
2J
2KCP
2Q
2Q
CLK CLK
1Q
2Q
1J
1KCP
1Q
1Q
1
1
2J
2KCP
2Q
2Q
CLK
Multi-gates
2CLK
CLK
1Q
2Q2CLK
Delay due to multiple
gates
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Timing example in Data sheetTiming example in Data sheet
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
F/F synchronizationF/F synchronization
To synchronize the behavior of an asynchronous input, actuated by human, with the clock input
preventing the appearance of partial pulse, X contains only complete pulses
A
clock
X
Debouncing switch
clock
A X
Partialpulse
Debouncing switch
clock
A
XD Q
Q
A
clock
X
Q
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Parallel data transferParallel data transfer
Data transfer : the transfer of data from one F/F to another
synchronous transferthe data is transferred at the time when the CLK is asserted
asynchronous transferthe data transfer is performed independently of CLK inputlevel-triggered
parallel data transferthe contents of group of F/Fs aretransferred simultaneously into other F/Fs
D 1X
1X
D 2X
2X
D 3X
3X
D 1Y
1Y
D 2Y
2Y
D 3Y
3YCLK
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Serial data transferSerial data transfer
Serial transferthe contents of the register is transferred to another register one bit at a time
serial registera group of F/Fs arranged so that the bits in the F/Fs are shifted from one F/F to the next for every clock pulse
X1 X2 X3 Y1 Y2 Y3 before pulse applied 1 0 1 0 0 0
after first pulse 0 1 0 1 0 0after second pulse 0 0 1 0 1 0
after third pulse 0 0 0 1 0 1
D 1X
1X
D 3X
3X
D 1Y
1Y
D 2Y
2Y
D 3Y
3Y
D 2X
2XCLK
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
CounterCounter
Frequency divider division of a frequency by 1/2N using N flip-flops
binary counter : a circuit that makes an increment by 1 at the occurrence of eachclock pulse
1J
1KCP
1Q
1Q
1
1
2J
2KCP
2Q
2QCLK 0J
0KCP
0Q
0Q
1
1
1
1
clock
2Q
1Q
0Q
1 2 3 4 5 6 7 00 1 2
Q2 Q1 Q00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 00 0 1
State transition table
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Counter(2/2)Counter(2/2)
State transition diagramto show how the states of the flip-flops change with each clock pulsea circle represents the state arrows indicate the state transition paths
Mod number# of states in the counting sequenceif N flip-flops are connected, it would be an MOD-2N counter which counts from 0 to 2N-1 repeatedly
ex) MOD-6 counter1, 2, 3, 4, 5, 6, 1, 2, 3,……0, 1, 2, 3, 4, 5, 0, 1, 2,… …
000001
010110
100011101
111
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Schmitt-trigger devicesSchmitt-trigger devices
Schmitt-trigger devicesdesigned to accept slow-changing signals produce an output that has oscillation-free transition
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
One-ShotOne-Shot
Multivibratorbistable multivibrator : two stable states (flip-flop)monostable multivibrator(one shot)
only one stable statesonce triggered, it remains in the quasi-stable state for a fixed period of time tp
non-retriggerable one-shotignore triggering pulse during quasi-stable state
retriggerable one-shotretriggered while it is in the quasi-stable state, and it will begin a new tp interval
R-OS
N-OS
T
pt
pt
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
Clock generatorClock generator
Schmitt-trigger Oscillator555 TimerCrystal-controlled clock generators
using CMOS 74HC04 using 74LS04 R = 100KΩ R=300-1500Ωf ≤ 10MHz f ≤ 20MHz
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김 인 철 (UOS 00-1)김 인 철 (UOS 00-1)
Digital Signal Processing
HomeWork #4HomeWork #4
5-3, 5-9, 5-12, 5-22, 5-25, 5-265-30, 5-33, 5-34, 5-58