flip flops summary
TRANSCRIPT
-
8/7/2019 flip flops summary
1/25
1
ECS 465: Digital Systems
Lecture Notes # 7
(A) Introduction to Sequential Circuits
(B) Latches and Flip-Flops
(C) Counter Design
SHANTANU DUTT
Department of Electrical and Computer Engineering
University of Illinois, Chicago
Phone: (312) 355-1314: e-mail: [email protected]
URL: http://www.eecs.uic.edu/~dutt
-
8/7/2019 flip flops summary
2/25
2
(A) Introduction to Sequential Circuits
Current o/p depends on the current i/p and past history of all i/ps
seen by the circuit.
Where the relevant past history should be representable by a finite
number of classes or states
No RedRed Light
State
Reset
Encode as state=0
Light = Red
O/P = 0
Light = Green
O/P = 1
Light = Not green
O/P = 0
Light = Not red
O/P = 0
Encode as
state = 1
State Transition Diagram
Design Problem: Output of the circuit is 1 only if it has seen a red
light in the past and currently light is green.
-
8/7/2019 flip flops summary
3/25
3
Circuit-Level Model of a Sequential Circuit.
Combinational
Circuit
Memory
Unit
Z0
Zm-1
Going to
external
world
x0
xn-1
I/p from
external
point
Statebits of
seq. ckt.
Current
State
Next
State
yk-1
y0
yk-1
y0
-
8/7/2019 flip flops summary
4/25
4
Components to store bits ( latches or flip flops )
1)
1
1
0
1
Problem: cant storenew data
Cascade of inverter
0
I/P 1/0 O/PA
A
LD
LD
LD
LD
Will conduct when
A=1, and open when
A=0
2)
(B) Latches and Flip-Flops
-
8/7/2019 flip flops summary
5/25
5
Another storage element:
3) Cross coupled NOR gates ( R-S latch )
R=0
0
Q
1
S=1
0
Q
Q
R
Q
S
Q
(Set)
(Reset)
NOR gates ( R-S latch )
Property of a NOR gate
A=0
B
B
BBA !
When one I/P of NOR is 0, it acts like an inverter.
When one I/P is 1, then O/P=0.
Different I/P conditions for R-S latch:
i) R=S=0, current I/P is stored indefinitely
( becomes cascade of inverters)Hold
-
8/7/2019 flip flops summary
6/25
6
ii) R=1, S=0, when we want to store a 0 in the R-S latch.
Q=0, 1!Q
iii) R=0, S=1, when we want to store a 1 in the latch.Q=1, 0!Q
iv) R=1, S=1; Forbidden inputs!
Both Q = 0, : Q and its complement have the same value !
Will play havoc in the rest of the logic circuit.
Transit to: R=0, S=0.
R=1, S=1, both Q and and 0.Q
0 0 O/P oscillates.
Q
Q
R=1p0
S=1p0
0
1
0p1
0p1
0pppp
pppp
Oscillates
between 1 and 0
when we transit from
R=S=1 to R=S=0.
0!Q
-
8/7/2019 flip flops summary
7/25
7
Cross-coupled NORR
Q
S
Q
Cross-coupled NAND
R
S
Q
Q
Hold State R=S=0 Hold State R=S=1
Q
QR=1, S=1
R=0, S=0
Forbidden I/Ps
From R, S = 1, 1 transit to R=0, S=1
then Q, transit to 1, 0 ( correctly )
From R, S = 1, 1 transit to R=1, S=0
then Q, correctly transit to 0, 1
Q
Q
Two implementations for R-S latch:
-
8/7/2019 flip flops summary
8/25
8
4) The D-Latch
R-SLatch
DS
RR1
S1
Q
enbQ
Clocked Latch
(level-sensitive clock latch)
see terminology defined
later.
D=1, S=1, R=0
Q=1,
D=0, S=0, R=1
Q=0,
enb=0 R1,S1=0 (hold state)
0!Q
1!Q
enb=1
enb=1
-
8/7/2019 flip flops summary
9/25
9
5) The J-K Latch:
Proposed to get rid of the forbidden I/P problem of R-S
i) J=1, K=0: (a) Let Q=1, p R=0,S=0
p Hold state of R-S p Q=1,
1!Q 0!Q
0!Q
0!Q
ii) J=0, K=1 Q=0, using a similar analysis
iii) J=K=0 | Hold state
iv) J=K=1, suppose Q=1, =0 R=1, S=0 Q=0, =1
S=1, R=0 Q=1, =0
This type of toggling continues as long as J=K=1, and the latch
is enabled ( CLK=1 below )
Q
Q
Q
(b) Let Q=0, , R=0, S=1 p Q=1,
1!Q
R
R-S
Q
QS
RQ
1
Q 0p1 0p
1
1p0 1p0
CLK
K
J
-
8/7/2019 flip flops summary
10/25
10
Latch classification with respect to response to control signal
Terminology:Note that the terminology below applies to all types of latches:R-S, D, J-K, T, etc., though the examples are given for the R-S latch.
i) Transparent Latch: O/P responds to latch I/Ps without any enable or clock signal.
R Q
S
Q
Clock:
Fixed frequency alternating 1 and 0 signal
ii) Clocked or Level-Sensitive Latch:
Q
Q
S
Clock
or
enb
R
O/P responds to I/Ps only when enb orclock is at a pre-determined level (high
or low In this example, it is High)
R
S
Q
Q
Symbol:
R
S
Q
Q
CLK(high enable)
Symbol: or R
S
Q
Q
CLK (low enable)
-
8/7/2019 flip flops summary
11/25
11
iii) Edge-Triggered Flip-Flop (FF) or simply Flip-Flop
O/P will respond to I/Ps only at either:
(a) the positive or rising edge of the enb/clock signal (positive
edge-triggered FF), or
(b) the negative or falling edge of the enb/clock signal (negative
edge-triggered FF).
Clock:
O/P response
period for a
positive
edge-triggered
FF.
O/P response
period for a
negative
edge-triggeredFF
O/P response
period for a
HIGH-enable/clock
level-sensitive
latch
O/P resp. period for
a low-enable/clock
level sensitive latch
Symbol:
R
S
Q
Q
CLK
Symbol:
R
SQQ
CLK
-
8/7/2019 flip flops summary
12/25
12
Setup Times and Hold Time of FFs and Latches
Assume, positive edge-triggered D-FFTHoldn relates to propagation delay
of another part of circuit.
D
CLK
TSetupn relates to propagation delays of
various gates in the FF.The high point ofthe CLK determines the positive edges arrival.
If negative edge-triggered
CLK
D
THoldTSetup
Negative edge arrival
If D-Latch is high-level sensitive: Tsetup and Thold have to be around the negative edge
of clock (more specifically, when the clock begins to go low), similar to negative edge-triggered.
If D-Latch is low-level sensitive: Tsetup and Thold have to be around the positive
edge of clock, similar to positive edge-triggered.
-
8/7/2019 flip flops summary
13/25
13
Solutions to Race Condition Problem with Level Sensitive Latches
Solution 1: Master-Slave FF:
Master-Slave J-K is a solution to race-condition problem: Any change in Q,
during CLK=0 is not propagated to P, and hence back to Q, during the
same CLK=0. Any change to Q, will occur in next CLK=0 period.
J
K
Q
Q
(O/P responds when CLK goes
From 1 to 0)
J-K
M-S
Master-Slave J-K works similarto a J-K latch: E.g. Let
J=1, K=1, CLK=1
Q=1, =0 =1 , P=0
When CLK=0
Q=0, =1
Q
Q
Q
R-S
Latch
CLK
K
J
Q
R
S
R-SQm
mQ R
S
sQ
Qs
1
0
1
0P
P1
0
1
0
Master R-S is level sensitive. Slave R-S is level sensitive.
Q
Q
P Q
Q
P
-
8/7/2019 flip flops summary
14/25
14
Solution 2: Edge-Triggered FF:
Q
Q
R
S
D
Clk=1
D
D
0
0
Holds D whenclock goes low
Holds when
clock goes low
D
Q =D
DQ !
R
S
D
Clk=0
D
D
D
Assume D=1
D=1=S
Q=1,
RD !! 0
0!Q
CLK
Q
Q
R
S
D
Clk=0
D
D
0
0
Q responds to
internal S signal;
responds to
internal R signal.
Q
When CLK is 1 D I/P is
internally sampled but
does not appear at the O/P.O/P is held (changing D does not
cause any change in internal
signals in the FF or in its output)
O/P appears (Q=D)
D
D
D
D
-
8/7/2019 flip flops summary
15/25
15
Characteristic Equations of Latches/FFs
The next O/P Q+ defined in terms of the current O/P Q and the I/P.
(FF/Latch is the simplest possible sequential ckt.)
1) R-S Latch Truth Table:
S(t) R(t) Q(t) Q+ = Q( t+( )
0 0 0 0
0 0 1 10 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x1 1 1 x
Values at time t
Hold
Reset
Set
Forbidden
Q(t)\SR 00 01 11 10
0 0 0 x 1
1 1 0 x 1
Q+= S+ Q
(Characteristic equation)R
-
8/7/2019 flip flops summary
16/25
16
Similarly: Characteristic Equations of
2) J-K, Q
+
= Q + J.3) D-FF, Q+ = D
4) Toggle FF/Latch Q+ = T + Q
or T-FF / Latch
K Q
Q T
Whenever I/P T is high,the FF will toggle, i.e., Q+ = .
When T=0, Q+=Q.
Q
Of course, these characteristic equations come into play onlywhen the FF/Latch is enabled.
Q
QT
Symbol:
-
8/7/2019 flip flops summary
17/25
17
Excitation Table
Reversed Truth Table
What the inputs to FFs should be for given outputtransitions (Q p Q+)
Q Q
+
R S J K T D0 0 x 0 0 x 0 0
0 1 0 1 1 x 1 1
1 0 1 0 x 1 1 0
1 1 0 x x 0 0 1
-
8/7/2019 flip flops summary
18/25
18
Conversion between FFs
Example: J-K to D
D-FF
D
0 1
x x
0 1
0
1
Q
D
x x
1 0
DQ
D
O/P function = JJ=D
Function = KK= D
Map the D,Q input combination to a QpQ+ transition
and then map this to J-K excitation required.
Thus, when D=1, Q=0, Q+
=1
J,K = 1,xD=0, Q=0, Q+=0 J,K = 0,x
D=1, Q=1, Q+=1 J,K = x,0
D=0, Q=1, Q+=0 J,K = x,1.
This should
behave like a
D-FF.
J
K
QQ
D
CLK
Logic
J
K
Q
QD
CLK
-
8/7/2019 flip flops summary
19/25
19
Example 2: D p J-K
Excitation Table for D
Q Q+ D
0 p 0 0
0 p 1 1
1 p 0 0
1 p 1 1
J K Q Q+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Q
Q
DJ
K
CLK
TT for J-K
JKQ
0
1
00 01 11 10
0 0 1 1
1 0 0 1
Function is
Q
Q
D
CLK
J
K
Q
Q
J-K FF/LatchQKQJD !
QJ
QK
Logic
should work like a J-K
-
8/7/2019 flip flops summary
20/25
20
(C) Counter Design
A counter is a special case of an FSM that cycles through its states
on receiving triggering clock pluses. It does not have any external data I/Ps.
A
B
C
D
EReset
000
001
010
011
100
FFs
LogicCounter O/P
Next State
bits
nn
CLK
The states need to be encoded by binary bits.
No external I/Ps
-
8/7/2019 flip flops summary
21/25
2
1
Synthesis (3-Bit Up Counter)
000 111
001 110
010 101
011 100
Reset
(a) State Transition
Diagram
C B A C+ B+ A+ TC TB TA
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
Input
Present State
Output
Next State
Toggle Flip-Flop
Inputs
(b) State Transition TableFF Excitation Table Revisited
Q Q+ R S J K T D
0 0 x 0 0 x 0 0
0 1 0 1 1 x 1 1
1 0 1 0 x 1 1 0
1 1 0 x x 0 0 1Excitation table for R-S, J-K, T, and D Flip-Flops
(What next statewill be given the
current state.)
State Transition Diagram and Table for a 3-bit Binary Up-Counter
-
8/7/2019 flip flops summary
22/25
22
From excitation table for FF inputs, get K-map for the FF inputs.
1 1 1 1
1 1 1 1
00 01 11 10
0
1
CB
A
TA=1
0 0 0 0
0 1 1 0
00 01 11 10
0
1
A
CB
TC=AB
0 0 0 0
1 1 1 1
00 01 11 100
1
A
CB
TB=A
K-maps for Up-Counter Using ToggleFlip-Flops.
Obtain logic expr. for FF I/Ps (as functions of current state bits A,B, C, --- A=QA, B=QB, C=QC) and realize the counter
-
8/7/2019 flip flops summary
23/25
23
Counters with More Complex Sequencing (Non-Consecutive Binary Outputs)
000 110
010 101
011
State Transition
Diagram
C B A C+ B+ A+
0 0 0 0 1 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 1 0 1
1 0 0 x x x
1 0 1 1 1 0
1 1 0 0 0 01 1 1 x x x
Present State Next State
State Transition Table
Implementation Using J-K FFs:
C B A C+ B+ A+ JC KC JB KB JA KA
0 0 0 0 1 0 0 x 1 x 0 x
0 0 1 x x x x x x x x x
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 1 1 x x 1 x 0
1 0 0 x x x x x x x x x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 0 0 0 x 1 x 1 0 x
1 1 1 x x x x x x x x x
Present
State
Next
State
Remapped Next
State
State Transition Table and Remapped Next-State Functions
Q Q+ J K
0 0 0 x0 1 1 x
1 0 x 1
1 1 x 0
QKQJQ !
J-K Flip-Flop Excitation Table
-
8/7/2019 flip flops summary
24/25
24
Next State Functions
CBJJ
AJ
A
B
C
!
!
!
1CK
CAK
AK
A
B
C
!
!
!
0 0 x x
x 1 x x
00 01 11 10
0
1
CB
A
JC
x x 1 x
x x x 0
CBA 00 01 11 10
0
1KC
1 x x x
x x x 1
CBA 00 01 11 10
0
1JB
x 0 1 x
x 1 x x
CBA 00 01 11 10
0
1KB
0 1 0 x
x x x x
00 01 11 10
0
1
CB
A
JA x x x x
x 0 x 1
00 01 11 10
0
1
CB
A
KA
Remapped K-Maps for J-K Implementation.
-
8/7/2019 flip flops summary
25/25
25
Actual Implementation ( Using J-K)
J Q
CLK
K Q
J Q
CLK
K Q
J Q
CLK
K Q
+
Count
signal
AC
KB
B JA
C
A
JAB
KB
A
C
J-K Flip-Flop Implementation of3 Bit Counter.
A C B A
C