fixed point arithmetics 1

Upload: suhaskognole1575

Post on 14-Apr-2018

227 views

Category:

Documents


0 download

TRANSCRIPT

  • 7/29/2019 Fixed Point Arithmetics 1

    1/26

    Fixed-Point Arithmetics: Part I

  • 7/29/2019 Fixed Point Arithmetics 1

    2/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Binary Representation

    Unsigned Magnitude

    Signed Magnitude

    Twos Complement

  • 7/29/2019 Fixed Point Arithmetics 1

    3/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Unsigned Magnitude

    Only positive number are presented

    No sign bit

    For N bits we can represent the signedintegers between 0 and 2N -1

    Example: 111 -> 7

  • 7/29/2019 Fixed Point Arithmetics 1

    4/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Signed Magnitude

    The most significant bit is used torepresent the sign: 1 means negative,

    0 means positive

    For positive numbers the result is thesame as unsigned magnituderepresentation

    For N bits we can represent the signedintegers between -2(N-1) +1 and +2(N-1)-1

  • 7/29/2019 Fixed Point Arithmetics 1

    5/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Disadvantage of Signed Magnitude

    Two encoding for the zero 0. Addition of two numbers of opposite sign will not yield

    0!! -5 + 5 = (85)H + (05) H = (8A) H = -10!!

    Arithmetic operations of numbers with unlike sign and

    with same sign must be handled differently (subtracterneeded with unlike signs)

    AB A + (-B) Example: 3 2Addition Operation 3 + (-2) Subtraction Operation (3-2)

    0011 (+3) 0011 (+3)+ 1010 (-2) - 0010 (+2)

    ------- -------1100 (-5) WRONG! 0001 (+1) CORRECT!

  • 7/29/2019 Fixed Point Arithmetics 1

    6/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Disadvantage of Signed Magnitude

    A hardware adder and subtracter needed Special treatment also for A B if B > A

    Example 3 2 & 2 3 Subtraction Operation 3 - 2 Subtraction Operation 2 - 3

    0011 (3) 0010 (+2)- 0010 (2) - 0011 (+3)

    ------- ------0001 (1) CORRECT 1111 (-7) WRONG

    Solution: Switch order of operands (3 2 instead of 2 3) Perform subtraction (Result = 1)

    attach the minus sign (Result = -1)

  • 7/29/2019 Fixed Point Arithmetics 1

    7/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Twos Complement example

    1 = 0001 1 = 1110 + 1 = 1111 2 = 0010 2 = 1101 + 1 = 1110 6 = 0110 6 = 1001 + 1 = 1010 8 = 1000 8 = 0111 + 1 = 1000

    Note that the max positive number that can berepresented is 7! Since to get the negative of -8 weneed:

    -8 = 1000To bitwise invert : 0111Add +1 to LSB: +1

    Result: 1000So(-8) = -8 (abnormal result) 8 cannot be represented

    For N bits, the max number is 2(N-1)-1 while the minnumber is -2(N-1)

    G t i D i ti f T

  • 7/29/2019 Fixed Point Arithmetics 1

    8/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Geometric Depiction of TwosComplement Integers

  • 7/29/2019 Fixed Point Arithmetics 1

    9/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Benefits of 2s Complement

    One unique representation of the number 0: 0 = 0000 Complement: 1111 Add +1 to LSB: +1 Result: 0000 (Ignoring carry bit)

    -0 = +0 Negation: take complement and add +1 Extending word length:

    For positive number pack with leading zeros +3 =011

    +3 = 000011 For negative numbers pack with leading ones

    -4=100 -4 =111000

  • 7/29/2019 Fixed Point Arithmetics 1

    10/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Benefits of 2s Complement

    Subtraction Rule: to subtract b from a, take the 2s

    complement of b and add it to a: a b = a + (-b)

    Adder

    ab

    Result

    2s

    If Subtractionenable

    a b

    Compare signs bitsEqual??

    Adder: a + b Is a > b

    Yes No

    Sub: a - b

    Yes

    Swap OperandSub: a b

    Negate

    No

    2s Comp

    Signed Mag

  • 7/29/2019 Fixed Point Arithmetics 1

    11/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Benefits of 2s Complement

    Overflow Rule: if two numbers with same signare added and overflow occurs the resultnumber has different sign: Addition: 011 + 011 = 110

    3 + 3 = -2 Subtraction: 110 011 = 011

    -2 - 3 = 3 Multiplication: 011 * 010 = 110

    3 * 2 = -2

  • 7/29/2019 Fixed Point Arithmetics 1

    12/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    What to Do In case of Overflow

    Prevention rule: design your code with minimal possibleoverflows

    DSP can be configured to saturate the number atoverflow (N=4): 5 x 2 = 0010 Overflow

    5 x 2 = 0111 Saturate Guard bits in accumulator could be useful for

    intermediate results Example: 5 x 2 - 1 x 4 = 10 4 = 6 If accumulator has one extra bit called guard bit the final

    result will not overflow!

  • 7/29/2019 Fixed Point Arithmetics 1

    13/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Multiplication Example

    1011 Multiplicand (11 dec)

    x 1101 Multiplier (13 dec)

    1011 Partial products

    0000 Note: if multiplier bit is 1 copy 1011 multiplicand (place value)

    1011 otherwise zero

    10001111 Product (143 dec) Note: need double length result

  • 7/29/2019 Fixed Point Arithmetics 1

    14/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Unsigned Binary Multiplication

  • 7/29/2019 Fixed Point Arithmetics 1

    15/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Execution of Example

  • 7/29/2019 Fixed Point Arithmetics 1

    16/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    owc ar or ns gne naryMultiplication

  • 7/29/2019 Fixed Point Arithmetics 1

    17/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Problem: Multiplication & 2s Complement

    Addition and Subtraction can be treated asunsigned integer

    1001 (-7)

    + 0011 (+3)

    1100 (-4)

    1001 (+9)

    + 0011 (+3)

    1100 (+12)

    Unsigned

    2s Complement

    What about multiplication??

    1010 (10)

    x 1110 (14)

    0000

    1010

    1010

    1010

    10001100 (140)

    Unsigned

    1010 (-6)

    x 1110 (-2)

    0000

    1010

    1010

    1010

    10001100 (-116) Wrong Result!!!

    2s Complement

  • 7/29/2019 Fixed Point Arithmetics 1

    18/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Problem: Multiplication & 2s Complement

    Addition and Subtraction can be treated asunsigned integer

    1001 (-7)

    + 0011 (+3)

    1100 (-4)

    1001 (+9)

    + 0011 (+3)

    1100 (+12)

    Unsigned

    2s Complement

    What about multiplication??

    1010 (10)

    x 1110 (14)

    0000

    1010

    1010

    1010

    10001100 (140)

    Unsigned

    1010 (-6)

    x 1110 (-2)

    0000

    1010

    1010

    1010

    10001100 (-116) Wrong Result!!!

    2s Complement

    Need to sign extend partial products

  • 7/29/2019 Fixed Point Arithmetics 1

    19/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Problem: Multiplication & 2s Complement

    Addition and Subtraction can be treated asunsigned integer

    1001 (-7)

    + 0011 (+3)

    1100 (-4)

    1001 (+9)

    + 0011 (+3)

    1100 (+12)

    Unsigned

    2s Complement

    What about multiplication??

    1010 (10)

    x 1110 (14)

    0000

    1010

    1010

    1010

    10001100 (140)

    Unsigned

    1010 (-6)

    x 1110 (-2)

    00000000

    1111010

    111010

    11010

    000101100 (44) Still Wrong Result!!!

    2s Complement

    Need to sign extend partial products

  • 7/29/2019 Fixed Point Arithmetics 1

    20/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Multiplying Negative Numbers

    This does not work! Solution 1

    Convert to positive if required

    Multiply as above

    If signs were different, negate answer

    Solution 2

    Booths algorithm

  • 7/29/2019 Fixed Point Arithmetics 1

    21/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Solution 1

    Solution 1 is as follows: If either multiplicand or multiplier is negative

    convert it to positive

    Do the multiplication operation

    Check the signs of the multiplicand andmultiplier if different negate the result

    Adds HardwareComplexity

  • 7/29/2019 Fixed Point Arithmetics 1

    22/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Solution 2: Booth Algorithm (1951)

    Knn

    K

    n

    K

    nKnnn

    22

    2

    11

    2

    11

    22

    1

    2

    1

    2

    112222 1

    1

    2

    1

    Booth starts from the fact that a seriescan be represented as:

    Suppose that we have to perform the followingmultiplication:

    M*30 -> M * (00011110) = M * (24+23+22+21)

    From series the multiplication can be written as:

    M * (00011110) = M * (25 21)Savings on computations

  • 7/29/2019 Fixed Point Arithmetics 1

    23/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Booth Algorithm:

    Multiply the multiplicand by -2n-Kwhen atransition from 0 to 1 (0-1) is encounteredgoing from right to left.

    Multiply the multiplicand by 2n+1whenever an transition from 1-0 isencountered

    Add the partial products obtained.

  • 7/29/2019 Fixed Point Arithmetics 1

    24/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Booth Algorithm:

    When multiplying 2n-bit numbers, form 22n-bit partialproducts as follows:

    When the first 1 of a block is encountered (1-0), partialproduct is formed by negating the multiplicand andappropriately shifting the negated multiplicand

    When the last 1 of a block is encountered (0-1), partialproduct is formed by taking the multiplicand andappropriately shifting it

    When either 0-0 or 1-1 is encountered, partial product is allzeros

    Sign-extend all partial products

    Add the partial products to obtain the multiplicationresult.

  • 7/29/2019 Fixed Point Arithmetics 1

    25/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591Real Time DSP

    Booth Algorithm: Example 1

    Multiplying: -6 x -2

    00001100

    0000110

    0-000000000

    (0)X 1110

    1010

    1-0000000 1-100000 1-1

    -6

    -2

    (Subtract multiplicand)(Shift)(Shift)

  • 7/29/2019 Fixed Point Arithmetics 1

    26/26

    I ra Fu lton School of Engineeri ng

    Electri cal Department

    EEE404/591 R l Ti DSP

    Multiplication: Why MSB is Redundant?

    Assume that we have a number represented by 4 bits(N = 4) 2s complement range is from -8 to +7. The min/max number obtained from multiplication is

    -56/+64 7 bits are enough to represent the result. In general: 2N-1 bits are needed if NxN multiplication is

    performed The additional MSB is a sign extension bit and can be

    removed Another way to interpret it is that if converted to

    unsigned the multiplication result will be (N-1) + (N-1)+ 1 sign bits giving 2N 1.