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Fixed-Point IP Cores(ALTERA_FIXED-POINT_FUNCTIONS) User GuideUG-200672017.03.31

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Contents

1 About Fixed-Point IP Cores.............................................................................................. 3

2 Getting Started................................................................................................................ 42.1 Installing and Licensing IP Cores...............................................................................42.2 Design Flow........................................................................................................... 4

2.2.1 IP Catalog and Parameter Editor................................................................... 52.2.2 Generating IP Cores (Quartus Prime Pro Edition).............................................7

2.3 Upgrading IP Cores............................................................................................... 112.3.1 Migrating IP Cores to a Different Device....................................................... 13

3 Fixed-Point IP Cores Parameters and Signals................................................................ 16

Contents

Fixed-Point IP Cores (ALTERA_FIXED-POINT_FUNCTIONS) User Guide2

1 About Fixed-Point IP CoresThe fixed-point IP cores (ALTERA_FIXED-POINT_FUNCTIONS) allow you to implementsimple fixed-point functions in your FPGA design. These IP cores are fullyparameterizable.

The fixed-point IP cores include functions for:

• Parallel add

• Multiply

• Divide

• Square root

• Simple counter

• Loadable counter

• Integer divide

This IP core targets Arria® 10 devices only.

Feature

• Optimized for Intel® HyperFlex™ FPGA architecture

• Configurable frequency and latency targets for add, multiply, divide, and squareroot functions.

1 About Fixed-Point IP Cores

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

ISO9001:2008Registered

http://www.altera.com/support/devices/reliability/certifications/rel-certifications.html



2 Getting Started

2.1 Installing and Licensing IP Cores

The Quartus® Prime software installation includes the Intel FPGA IP library. This libraryprovides useful IP core functions for your production use without the need for anadditional license. Some IP cores in the library require that you purchase a separatelicense for production use. The OpenCore® feature allows evaluation of any Intel FPGAIP core in simulation and compilation in the Quartus Prime software. Upon satisfactionwith functionality and performance, visit the Self Service Licensing Center to obtain alicense number for any Intel FPGA product.

The Quartus Prime software installs IP cores in the following locations by default:

Figure 1. IP Core Installation Path

intelFPGA(_pro*)

quartus - Contains the Quartus Prime softwareip - Contains the IP library and third-party IP cores

altera - Contains the IP library source code<IP core name> - Contains the IP core source files

Table 1. IP Core Installation Locations

Location Software Platform

<drive>:\intelFPGA_pro\quartus\ip\altera Quartus Prime Pro Edition Windows*

<drive>:\intelFPGA\quartus\ip\altera Quartus Prime Standard Edition Windows

<home directory>:/intelFPGA_pro/quartus/ip/altera Quartus Prime Pro Edition Linux*

<home directory>:/intelFPGA/quartus/ip/altera Quartus Prime Standard Edition Linux

2.2 Design Flow

Use the IP Catalog and parameter editor to define and instantiate complex IP cores.Using the GUI ensures that you set all IP core ports and parameters properly.

If you are an expert user, and choose to configure the IP core directly throughparameterized instantiation in your design, refer to the port and parameter details.The details of these ports and parameters are hidden in the parameter editor.

2 Getting Started






2.2.1 IP Catalog and Parameter Editor

The IP Catalog displays the IP cores available for your project. Use the followingfeatures of the IP Catalog to locate and customize an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for alldevice families. If you have no project open, select the Device Family in IPCatalog.

• Type in the Search field to locate any full or partial IP core name in IP Catalog.

• Right-click an IP core name in IP Catalog to display details about supporteddevices, to open the IP core's installation folder, and for links to IP documentation.

• Click Search for Partner IP to access partner IP information on the web.

The parameter editor prompts you to specify an IP variation name, optional ports, andoutput file generation options. The parameter editor generates a top-level QuartusPrime IP file (.ip) for an IP variation in Quartus Prime Pro Edition projects.

The parameter editor generates a top-level Quartus IP file (.qip) for an IP variationin Quartus Prime Standard Edition projects. These files represent the IP variation inthe project, and store parameterization information.

Figure 2. IP Parameter Editor (Quartus Prime Pro Edition)

View IP Portand Parameter Details

Apply Preset Parameters forSpecific Applications

Specify a Name foryour IP Variation

2 Getting Started


Figure 3. IP Parameter Editor (Quartus Prime Standard Edition)


Specify IP VariationName and Target Device

2.2.1.1 The Parameter Editor

The parameter editor helps you to configure IP core ports, parameters, and output filegeneration options. The basic parameter editor controls include the following:

• Use the Presets window to apply preset parameter values for specific applications(for select cores).

• Use the Details window to view port and parameter descriptions, and click links todocumentation.

• Click Generate ➤ Generate Testbench System to generate a testbench system(for select cores).

• Click Generate ➤ Generate Example Design to generate an example design(for select cores).

• Click Validate System Integrity to validate a system's generic componentsagainst companion files. (Qsys Pro systems only)

• Click Sync All System Infos to validate a system's generic components againstcompanion files. (Qsys Pro systems only)

The IP Catalog is also available in Qsys and Qsys Pro (View ➤ IP Catalog). The QsysIP Catalog includes exclusive system interconnect, video and image processing, andother system-level IP that are not available in the Quartus Prime IP Catalog. Refer toCreating a System with Qsys Pro or Creating a System with Qsys for information onuse of IP in Qsys and Qsys Pro, respectively.

Related Links

• Creating a System with Qsys Pro

• Creating a System with Qsys

2 Getting Started


https://documentation.altera.com/#/link/jbr1437426657605/mwh1409958596582/en-us

https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958596582/en-us

2.2.2 Generating IP Cores (Quartus Prime Pro Edition)

Quickly configure a custom IP variation in the Quartus Prime parameter editor.Double-click any component in the IP Catalog to launch the parameter editor. Theparameter editor allows you to define a custom variation of the selected IP core. Theparameter editor generates the IP variation synthesis and optional simulation files,and adds the .ip file representing the variation to your project automatically.

Figure 4. IP Parameter Editor (Quartus Prime Pro Edition)


Apply Preset Parameters forSpecific Applications

Specify a Name foryour IP Variation

Follow these steps to locate, instantiate, and customize an IP core in the parametereditor:

1. Create or open a Quartus Prime project (.qpf) to contain the instantiated IPvariation.

2. In the IP Catalog (Tools ➤ IP Catalog), locate and double-click the name of theIP core to customize. To locate a specific component, type some or all of thecomponent’s name in the IP Catalog search box. The New IP Variation windowappears.

3. Specify a top-level name for your custom IP variation. Do not include spaces in IPvariation names or paths. The parameter editor saves the IP variation settings in afile named <your_ip>.ip. Click OK. The parameter editor appears.

4. Set the parameter values in the parameter editor and view the block diagram forthe component. The Parameterization Messages tab at the bottom displays anyerrors in IP parameters:

• Optionally, select preset parameter values if provided for your IP core. Presetsspecify initial parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, anddevice-specific features.

• Specify options for processing the IP core files in other EDA tools.

2 Getting Started


Note: Refer to your IP core user guide for information about specific IP coreparameters.

5. Click Generate HDL. The Generation dialog box appears.

6. Specify output file generation options, and then click Generate. The synthesisand/or simulation files generate according to your specifications.

7. To generate a simulation testbench, click Generate ➤ Generate TestbenchSystem. Specify testbench generation options, and then click Generate.

8. To generate an HDL instantiation template that you can copy and paste into yourtext editor, click Generate ➤ Show Instantiation Template.

9. Click Finish. Click Yes if prompted to add files representing the IP variation toyour project.

10. After generating and instantiating your IP variation, make appropriate pinassignments to connect ports.

Note: Some IP cores generate different HDL implementations according to the IPcore parameters. The underlying RTL of these IP cores contains a uniquehash code that prevents module name collisions between different variationsof the IP core. This unique code remains consistent, given the same IPsettings and software version during IP generation. This unique code canchange if you edit the IP core's parameters or upgrade the IP core version.To avoid dependency on these unique codes in your simulation environment,refer to Generating a Combined Simulator Setup Script.

2.2.2.1 IP Core Generation Output (Quartus Prime Pro Edition)

The Quartus Prime software generates the following output file structure for individualIP cores that are not part of a Qsys Pro system.

2 Getting Started


Figure 5. Individual IP Core Generation Output (Quartus Prime Pro Edition)

<Project Directory>

<your_ip>_inst.v or .vhd - Lists file for IP core synthesis

<your_ip>.qip - Lists files for IP core synthesis

synth - IP synthesis files

<IP Submodule>_<version> - IP Submodule Library

sim

<your_ip>.v or .vhd - Top-level IP synthesis file

sim - IP simulation files

<simulator vendor> - Simulator setup scripts<simulator_setup_scripts>

<your_ip> - IP core variation files

<your_ip>.ip - Top-level IP variation file

<your_ip>_generation.rpt - IP generation report

<your_ip>.bsf - Block symbol schematic file

<your_ip>.ppf - XML I/O pin information file

<your_ip>.spd - Simulation startup scripts

*

<your_ip>.cmp - VHDL component declaration

<your_ip>.v or vhd - Top-level simulation file

synth

- IP submodule 1 simulation files

- IP submodule 1 synthesis files

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file

<HDL files>

<HDL files>

<your_ip>_tb - IP testbench system *

<your_testbench>_tb.qsys - testbench system file<your_ip>_tb - IP testbench files

your_testbench> _tb.csv or .spd - testbench file

sim - IP testbench simulation files * If supported and enabled for your IP core variation.

<your_ip>.qgsimc - Simulation caching file (Qsys Pro)

<your_ip>.qgsynthc - Synthesis caching file (Qsys Pro)

Table 2. Files Generated for IP Cores

File Name Description

<your_ip>.ip Top-level IP variation file that contains the parameterization of an IP core inyour project. If the IP variation is part of a Qsys Pro system, the parametereditor also generates a .qsys file.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains localgeneric and port definitions that you use in VHDL design files.

<your_ip>_generation.rpt IP or Qsys Pro generation log file. Displays a summary of the messages duringIP generation.

continued...

2 Getting Started


File Name Description

<your_ip>.qgsimc (Qsys Pro systemsonly)

Simulation caching file that compares the .qsys and .ip files with the currentparameterization of the Qsys Pro system and IP core. This comparisondetermines if Qsys Pro can skip regeneration of the HDL.

<your_ip>.qgsynth (Qsys Prosystems only)

Synthesis caching file that compares the .qsys and .ip files with the currentparameterization of the Qsys Pro system and IP core. This comparisondetermines if Qsys Pro can skip regeneration of the HDL.

<your_ip>.qip Contains all information to integrate and compile the IP component.

<your_ip>.csv Contains information about the upgrade status of the IP component.

<your_ip>.bsf A symbol representation of the IP variation for use in Block Diagram Files(.bdf).

<your_ip>.spd Required input file for ip-make-simscript to generate simulation scripts forsupported simulators. The .spd file contains a list of files you generate forsimulation, along with information about memories that you initialize.

<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IPcomponents you create for use with the Pin Planner.

<your_ip>_bb.v Use the Verilog blackbox (_bb.v) file as an empty module declaration for useas a blackbox.

<your_ip>_inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this fileinto your HDL file to instantiate the IP variation.

<your_ip>.regmap If the IP contains register information, the Quartus Prime software generatesthe .regmap file. The .regmap file describes the register map information ofmaster and slave interfaces. This file complements the .sopcinfo file byproviding more detailed register information about the system. This file enablesregister display views and user customizable statistics in System Console.

<your_ip>.svd Allows HPS System Debug tools to view the register maps of peripherals thatconnect to HPS within a Qsys Pro system.During synthesis, the Quartus Prime software stores the .svd files for slaveinterface visible to the System Console masters in the .sof file in the debugsession. System Console reads this section, which Qsys Pro queries for registermap information. For system slaves, Qsys Pro accesses the registers by name.

<your_ip>.v <your_ip>.vhd HDL files that instantiate each submodule or child IP core for synthesis orsimulation.

mentor/ Contains a script msim_setup.tcl to set up and run a simulation.

aldec/ Contains a Riviera*-PRO script rivierapro_setup.tcl to setup and run asimulation.

/synopsys/vcs

/synopsys/vcsmx

Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file toset up and run a VCS MX* simulation.

/cadence Contains a shell script ncsim_setup.sh and other setup files to set up andrun an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule.

<IP submodule>/ For each generated IP submodule directory, Qsys Pro generates /synthand /sim sub-directories.

2 Getting Started


2.3 Upgrading IP Cores

Any IP variations that you generate from a previous version or different edition of theQuartus Prime software, may require upgrade before compilation in the currentsoftware edition or version.The Project Navigator displays a banner indicating the IP upgrade status. ClickLaunch IP Upgrade Tool or Project ➤ Upgrade IP Components to upgradeoutdated IP cores.

Figure 6. IP Upgrade Alert in Project Navigator

Icons in the Upgrade IP Components dialog box indicate when IP upgrade isrequired, optional, or unsupported for an IP variation in the project. Upgrade IPvariations that require upgrade before compilation in the current version of theQuartus Prime software.

Note: Upgrading IP cores may append a unique identifier to the original IP core entityname(s), without similarly modifying the IP instance name. There is no requirement toupdate these entity references in any supporting Quartus Prime file, such as theQuartus Prime Settings File (.qsf), Synopsys* Design Constraints File (.sdc), orSignal Tap File (.stp), if these files contain instance names. The Quartus Primesoftware reads only the instance name and ignores the entity name in paths thatspecify both names. Use only instance names in assignments.

Table 3. IP Core Upgrade Status

IP Core Status Description

IP Upgraded

Indicates that your IP variation uses the latest version of the IP core.

IP Upgrade Optional

Indicates that upgrade is optional for this IP variation in the current version of theQuartus Prime software. Optionally, upgrade this IP variation to take advantage of thelatest development of this IP core. Retain previous IP core characteristics by declining toupgrade. Refer to the Description for details about IP core version differences. If you donot upgrade the IP, the IP variation synthesis and simulation files remain unchanged, andyou cannot modify parameters until upgrading.

continued...

2 Getting Started


IP Core Status Description

IP Upgrade Required

Indicates that you must upgrade the IP variation before compiling in the current versionof the Quartus Prime software. Refer to the Description for details about IP core versiondifferences.

IP Upgrade Unsupported

Indicates that Quartus Prime software does not support upgrade of the IP variation dueto incompatibility in the current software version. The Quartus Prime software promptsyou to replace the unsupported IP core with equivalent IP core from the IP Catalog. Referto the Description for details about IP core version differences and links to Release Notes.

IP End of Life

Indicates that Intel designates the IP core as end-of-life status. You may or may not beable to edit the IP core in the parameter editor. Support for this IP core discontinues infuture releases of the Quartus Prime software.

IP Upgrade Mismatch Warning

Provides warning of non-critical IP core differences in migrating IP to another devicefamily.

Follow these steps to upgrade IP cores:

1. In the latest version of the Quartus Prime software, open the Quartus Primeproject containing an outdated IP core variation. The Upgrade IP Componentsdialog box automatically displays the status of IP cores in your project, along withinstructions for upgrading each core. To access this dialog box manually, clickProject ➤ Upgrade IP Components.

2. To upgrade one or more IP cores that support automatic upgrade, ensure that youturn on the Auto Upgrade option for the IP core(s), and click PerformAutomatic Upgrade. The Status and Version columns update when upgrade iscomplete. Example designs provided with any Intel FPGA IP core regenerateautomatically whenever you upgrade an IP core.

3. To manually upgrade an individual IP core, select the IP core and click Upgrade inEditor (or simply double-click the IP core name). The parameter editor opens,allowing you to adjust parameters and regenerate the latest version of the IP core.

2 Getting Started


Figure 7. Upgrading IP Cores

Runs “Auto Upgrade” on all Outdated CoresOpens Editor for Manual IP Upgrade Upgrade Details

Generates/Updates Combined Simulation Setup Script for all Project IP

Note: IP cores older than Quartus Prime software version 12.0 do not supportupgrade. Intel verifies that the current version of the Quartus Primesoftware compiles the previous two versions of each IP core. The Intel FPGAIP Core Release Notes reports any verification exceptions for Intel IP cores.Intel does not verify compilation for IP cores older than the previous tworeleases.

Related Links

Intel FPGA IP Core Release Notes

2.3.1 Migrating IP Cores to a Different Device

Migrate an IP variation when you want to target a different (often newer) device. MostIntel FPGA IP cores support automatic migration. Some IP cores require manual IPregeneration for migration. A few IP cores do not support device migration, requiringyou to replace them in the project. The Upgrade IP Components dialog boxidentifies the migration support level for each IP core in the design.

2 Getting Started


http://www.altera.com/literature/rn/rn_ip.pdf

1. To display the IP cores that require migration, click Project ➤ Upgrade IPComponents. The Description field provides migration instructions and versiondifferences.

2. To migrate one or more IP cores that support automatic upgrade, ensure that theAuto Upgrade option is turned on for the IP core(s), and click PerformAutomatic Upgrade. The Status and Version columns update when upgrade iscomplete.

3. To migrate an IP core that does not support automatic upgrade, double-click theIP core name, and click OK. The parameter editor appears. If the parameter editorspecifies a Currently selected device family, turn off Match project/default,and then select the new target device family.

4. Click Generate HDL, and confirm the Synthesis and Simulation file options.Verilog HDL is the default output file format. If you specify VHDL as the outputformat, select VHDL to retain the original output format.

5. Click Finish to complete migration of the IP core. Click OK if the software promptsyou to overwrite IP core files. The Device Family column displays the new targetdevice name when migration is complete.

6. To ensure correctness, review the latest parameters in the parameter editor orgenerated HDL.

Figure 8. IP Core Device Migration

Upgrade in Editor(no Auto-Upgrade)

Migration Success Migration Details

Note: IP migration may change ports, parameters, or functionality of the IPvariation. These changes may require you to modify your design or to re-parameterize your IP variant. During migration, the IP variation's HDLgenerates into a library that is different from the original output location ofthe IP core. Update any assignments that reference outdated locations. If asymbol in a supporting Block Design File schematic represents yourupgraded IP core, replace the symbol with the newly generated<my_ip>.bsf. Migration of some IP cores requires installed support for theoriginal and migration device families.

2 Getting Started


Related Links

Intel FPGA IP Release Notes

2 Getting Started


http://www.altera.com/literature/rn/rn_ip.pdf

3 Fixed-Point IP Cores Parameters and SignalsEach IP core allows you to specify width, which is the total number of bits that makeup the fixed-point number. Specifying a sign uses one of the bits.

Table 4. Performance Tab ParametersEach IP core allows you to view resource usage in the IP Parameter Editor GUI. The parallel add, multiply,divide, integer divide and square root IP cores allow you adjust your implementation based on your chosenfrequency or latency target. The parallel add, multiply, divide, and qquare root IP cores allow you to designatesome of the bits to represent a fixed-point fraction.

Parameter Description

Goal Select Frequency, Latency, or Combined performancetarget

Target Enter the frequency in MHz at which you expect thisfunction to run. The IP core determines the amount ofpipelining from this frequency and the target device family.

Check Performance Click Check Performance to view the resource usage.

Parallel Add

This IP core calculates the sum of the inputs.

Table 5. Parallel Add Parameters


Input data widths

Input name Autogenerated name of this input to the generated IP core.

Width The width of this fixed-point data interface.

Fraction The number of fraction bits in this fixed-point data interface.

Sign The signedness of this fixed-point data interface.

+ Click + to add more inputs; click - to remove inputs.

Output data widths

Automatic output type Always turn on automatic output type to allow the IP coreto determine the output format based on the input andoperation.Width

Fraction

Sign

Options

Disable adder word growth The addition and or subtraction logic in the IP core normallyallows for word growth. To disable word growth turn on thisoption.

Generate an enable port Turn on if you want the function to have an enable signal.

3 Fixed-Point IP Cores Parameters and Signals






Table 6. Parallel Add Signals

Signal Direction Description

clk Input Clock.

reset Input Reset.

a0 Input Input a0.

a1 Input Input a1.

result Output The parallel add result.

Multiply

This IP core multiplies the two inputs.

Table 7. Multiply Parameters


Complex Data You can configure a multiplier to operate on complex valuedinputs and optionally use the Karatsuba method formultiplication of complex numbers. Complex valued inputsand outputs are concatenated real and imaginary values ofdata format you specify. The real part occupies the lowerbits of the input or output bus. Complex multiplicationrequires four multiplications and two additions.

Karatsuba complex multiplicaiton The Karatsuba option reduces the number of multipliers tothree, increases the number of adders to five.

Input data widths

Width The width of this fixed-point data interface

Fraction The number of fraction bits in this fixed-point data interface

Sign The signedness of this fixed-point data interface

Output data widths

Automatic output type Always turn on automatic output type to allow the IP coreto determine the output format based on the input andoperation.Width

Fraction

Sign

Options


If the IP core cannot represent the product of the inputs in the output format youchose, the result is undefined.

Table 8. Multiply Signals


clk Input Clock.

reset Input Reset.

continued...




a Input Input a.

b Input Input b.

result Output The multiply result.

Divide

This IP core produces the result of the first input, numerator, divided by the secondinput, denominator. The Divide IP core has a fixed-point output. You can control thenumber of significant bits in the output by adjusting the output data format. If youreduce the number of bits in the output, the divider uses fewer resources.

The LSB in the divider's output is faithfully rounded. Use the Integer Divide IP core toobtain true equivalence to a truncating CPU integer divider. The faithfully roundedresult has an accuracy of one unit in the last place, where one unit in the last place isthe weight of the LSB. For example, if the output format has zero fraction bits, theweight of the LSB is 2^0=1. If the result is 3.2, the IP core can either return 3 or 4,where both results are equally valid.

Table 9. Divide Parameters


Input data widths


Fraction The number of fraction bits in this fixed-point data interface.Divide IP core only.


Output data widths

Automatic output type Turn on to allow the IP core to determine the output formatbased on the input and operation.


Fraction The number of fraction bits in this fixed-point data interface.Divide IP core only.

Options


Table 10. Divide Signals


clk Input Clock.

reset Input Reset.

numerator Input Numerator.

denominator Input Denominator.

result Output The division result.



Square Root

The output is faithfully rounded. The faithfully rounded result has an accuracy of oneunit in the last place, where one unit in the last place is the weight of the LSB. Forexample, if the output format has zero fraction bits, the weight of the LSB is 2^0=1.If the result is 3.2, the IP core can either return 3 or 4, where both results are equallyvalid.

Table 11. Square Root Parameters


Input data widths


Fraction The number of fraction bits in this fixed-point data interface


Output data widths



Fraction The number of fraction bits in this fixed-point data interface.


Options


Table 12. Square Root Signals


clk Input Clock.

reset Input Reset.

radical Input

result Output The square root result.

Integer Divide

This IP core produces the result of the first input, numerator, divided by the secondinput, denominator. The Divide IP core has a fixed-point output. You can control thenumber of significant bits in the output by adjusting the output data format. If youreduce the number of bits in the output, the divider uses fewer resources.

The Integer Divide IP core offers true equivalence to a truncating CPU integer divider.

Table 13. Integer Divide Parameters


Input data widths



continued...




Output data widths



Options


Table 14. Integer Divide Signals


clk Input Clock.

reset Input Reset.

numerator Input Numerator.

denominator Input Denominator.

result Output The division result.

Simple Counter

This IP core maintains a counter and produces the counter value each cycle.The valueof the counter increments by the positive step value every cycle for which the enableinput is high.

The counter limit is its rollover value. The IP core sizes a counter to accommodate avalue one less than the limit you specify. For example, a limit of 65,536 specifies a 16-bit counter. If the start value is 0 and the step value is 1, the counter rolls over from65,535 to 0.

The limit must be equal to start plus an integer multiple of step.

Table 15. Simple Counter Parameters


Start value The counter initialises to this value on reset and whenincrementing a step reaches the Limit. The Start valuemust be greater than zero.

Step The increment that the IP core applies on each cycle whenthe counter's enable input is high. The simple counter's stepmust be positive. Step must be greater than zero.

Limit The counter counts up to one step away from this value. Ifadding the step value to the counter reaches the limit, thecounter returns to Start value. Limit must be greater thanor equal to Start.



Table 16. Simple Counter Signals


clk Input Clock.

rst Input Reset.

en Input Enable.

value Output

Loadable Counter

This IP core maintains a counter and produces the counter value each cycle.The valueof the counter increments by the step value every cycle for which the enable input ishigh.

The counter limit is its rollover value. The IP core sizes a counter to accommodate avalue one less than the limit you specify. For example, a limit of 65,536 specifies a 16-bit counter. If the start value is 0 and the step value is 1, the counter rolls over from65,535 to 0.

The limit must be equal to start plus an integer multiple of step.

Table 17. Loadable Counter Parameters


Start value The counter initializes to this value on reset and whenincrementing a step reaches the Limit.

Step The increment that the IP core applies on each cycle whenthe counter's enable input is high..

Limit The counter counts up or down to one step away from thisvalue. If adding the step value to the counter reaches thelimit, the counter returns to Start value.

Output data widths

Width The width of this fixed-point data interface. The width of thecounter and its Start, Step, and Limit inputs.


Table 18. Loadable Counter Signals


clk Input Clock.

rst Input Reset.

en Input Enable.

sload Input When sload is high, the IP corereplaces the counter's internal start,step, and limit values by values fromthe corresponding input signals.

step Input

start Input

limit Input

value Output



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