finl digital qb.doc

Format: QP09 KCE/DEPT.OF ECE

UNIT-I MINIMIZATION TECHNIQUES AND LOGIC GATESPART A (2 MARKS)

1. Prove the boolean theorems: x+x=x , x.x=x . (AU AM 2015)x + x = (x + x) 1

= (x + x)(x + x)= x + xx

= x + 0

= x

xx = x by duality.2. What are the dont care minterms. (AU AM 2015) In some applications, the Boolean function for certain combinations of the input variables is not specified. The corresponding minterms (maxterms) are called don't care minterms (maxterms).In K-map , the don't care minterms/maxterms are represented by d.

3. Draw the CMOS inverter circuit (AU ND 2014)

4. Convert 0.35 to equivalent Hexa Decimal number (AU MJ 2014) Solution:

0.35 x 16= 5.6 | 5

0.6 x 16= 9.6 | 9

0.6 x 16= 9.6 | 9

=(59)165. State De Morgans theorem.

(AU MJ 2014)-3De Morgan suggested two theorems that form important part of Boolean algebra. They are, 1) the complement of a product is equal to the sum of the complements.

2) The complement of a sum term is equal to the product of the complements. .6. Apply De Morgans theorem to [(A+B)+C] (AU MJ 2014)De Morgans theorem:

Solution:

[(A+B)+C] = [(A+B).C]

= [(A.B).C]

= A.B.C

7. What are Dont care terms?

(AU MJ 2013)In some logic circuits certain input conditions never occur, therefore the corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X or d in the truth tables and are called dont care conditions or incompletely specified functions.

8. What are the advantages of CMOS? (AU MJ 2013) Reduce the complexity of the circuit

Low static power consumption

High noise immunity

High density of logic functions on a chip9. List the names of universal gates. What are its advantages? (AU ND 2013)-2 The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application.10. What is Prime Implicant? (AU ND 2013)-2 A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map,so it can not be conbined with any other minterm or group11. State Distributive Law.

(AU ND 2013) The distributive property states that AND ing several variables and OR ing the result with single variable is equivalent to OR ing the single variable with each of the several variables and then AND ing the sums. This distributive property is 12. Simplify the given Boolean expression F =x+xy+xz+xyz (AU ND 2012)F = x+x(y+ z+zy) = x+(y+ z+yz)

(A+AB=A+B)

= x+y+z(1+y)

= x+y+z

(1+A=1)

13. Implementation the given function using NAND gates F() = m(0,6) (AU ND 2012)

14. What is a totem output?

(AU ND 2011) Apushpulloutput is a type ofelectronic circuitthat uses a pair of active devices that alternately supply current to, or absorb current from a connected load.15. Define fan in and fan out characteristics of digital logic families. (AU AM 2011) Fan in: Fan in is the number of inputs connected to the gate without any degradation in the voltage level.

Fan out: It is the maximum number of inputs of the same family that the gate can drive maintaining its output levels within the specified limits.16. Convert : (a) (520)10 (b) (1101.1101)2. (AU ND 2010)Solution:

(a) (100001000)2 (b) (13.13)10.17. Draw an active-high tri-state buffer and write its truth table. (AU AM 2010)

18. Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1. (AU ND 2009)

ab+ab'+a'b+a'b'

=a(b+b')+a'(b+b')

=a+a'=1

You know that x+ x' =119. What is syndrome? (AU ND 2009) If the check bits do not match the stored parity, they generate the unique pattern, called a syndrome that can be used to identify the bit that is in error.20. Show that a positive logic NAND gate is a negative logic NOR gate. (AU MJ 2009)

Positive NAND

Input

Output

0,0

1

0,1

1

1,0

1

1,1

0

Negative NOR

Input

Output

0,0

1

0,1

1

1,0

1

1,1

0

Output is the same.PART B1. (i) With suitable examples, explain the conversion of standards forms to canonical forms of Boolean expression.

(5) (AU AM 2015)Answer Key:

Simplification of the Boolean Expression

(3) Boolean Law

(2)(ii) Implement the given Boolean function F=xy+xy+yz using with NAND gate and inverter gates.

(6)Answer Key:


(3) Boolean Law

(3)(iii) Verify, whether or not EXOR operation is commutative and assosiative.(5)Answer Key:


(3) Boolean Law

(2)2. (i) Show the five variable Karnaugh map and explain the minimization technique.Answer Key:

(8) (AU AM 2015) K-map Implementation

(5) Simplify the Boolean Expression

(5) (ii) Simplify the following expression using K-map method.

(8)

F(A,B,C,D) = (0,2,3,5,7,8,9,10,11,13,15).Answer Key:

K-map Implementation


(4)3. (i) Convert the following function into Product of Maxterms

(8) (AU ND 2014)F(A,B,C)=(A+B)(B+C) (A+C)Answer Key:


(4) Boolean Law

(4) (ii) Using quine mcclusky method simplify the given function

F(A,B,C,D)=m(0,2,3,5,7,,11,13,14)Answer Key:

Arrange all minterms according to the number of 1s &

Combine the minterms into a group of two.

(2) Combine the minterm pairs into groups of four

(2) Collect all non checked form

(2) Prepare the PI table and obtain the EPIs.

(2)4. (i) Draw the multiple level two input NAND circuit for the following expression F=(AB+CD)E+B(A+B)

(4) (AU ND 2014)Answer Key:


(2) Boolean Law

(2)5. (ii) Draw and explain tri-state TTL inverter circuit diagram and explain its operationAnswer Key:

(12) Explanation

(6)

Circuit Diagram

(6)

6. (i) Given Y(A,B,C,D)=m(0,1,3,5,6,7,10,14,15), draw the K map and obtain the simplified expression. Relize the minimum expression using basic gates.

(8) (AU MJ 2014)Answer Key:


(4) Simplification of the Boolean Expression

(4)(ii) Implement the expression Y(A,B,C)=m(0,2,4,5,6), Using only NOR-NOR logic. Answer Key:

(4) K-map Implementation

(2) Simplification of the Boolean Expression using NOR-NOR logic

(2)(iii) Implement EXOR gate using only NAND gates. Answer Key:

(4) Explanation

(2)

Circuit Diagram

(2)7. Simplify the following function using Tabulation method Y(A,B,C,D)= m(0,1,2,5,6,7,8,9,10,14) and implement using only nand gates.

(16)(AU MJ 2014)Answer Key:

Arrange all minterms according to the number of 1s(2) Combine the minterms into a group of two.




(4)8. (i) Simplify xy + x z + yz.

(6) (AU ND 2013)Answer Key:


(3) Boolean Law

(3)(ii) Simplify the following expression using K-map method.

Y = (7,9,10,i 1,12,13,14,15).

(10)

Answer Key:


(6) Simplification of the Boolean Expression

(4)9. (i) Write short notes on dont care conditions

(6)(AU ND 2013)Answer Key:

Explanation

(4)

Example

(2)

(ii) Explain about NAND and NOR implementations

(10)

Answer Key:

Explanation

(6)

Logic Diagram

(4)

10. Simplify the given Boolean function intoProduct of sum form and implement if using basic gates.

F(A,B,C,D)=(0,1,2,5,8,9,10)

(16) (AU MJ 2013)

Answer Key:

K-map & Simplification

(8)

Logic Diagram

(8)

11. Minimize the given switching function Quine-Mcclusky method.

f(x1, x2, x3, x4 )=(0,5,7,8,9,10,11,14,15).

(16) (AU MJ 2013)

Answer Key:

Arrange all minterms according to the number of 1s(2) Combine the minterms into a group of two.




(4)12. (i) Express the Boolean function as

(1) POS form

(2) SOP form

D = (A + B) (B + C)

(4) (AU AM 2010)

Answer Key:

Change POS form

(2) Change SOP form

(2)(ii) Minimize the given terms M (0, 1, 4, 11, 13, 15) + d (5, 7, 8) using Quine-McClusky methods and verify the results using K-map methods

(12) Answer Key:

Minimization using K-map

(2) Arrange all minterms according to the number of 1s(2) Combine the minterms into a group of two



(2) Prepare the PI table and obtain the EPIs

(2)13. (i)Implement the following function using NOR gates. Output = 1 when the inputs are m(0,1,2,3,4) = 0 when the inputs are m(5,6,7)




(2) Logic Diagram

(3)(ii) Discuss the general characteristic of TTL and CMOS logic families(8)

Answer Key:

TTL Characteristiscs

(4) CMOS logic Characteristics

(4)14. (i) Express the Boolean function F = XY + XZ in product of Maxterm.(6) (AU ND 2009)Answer Key:

General form

(2) Simplification

(4)(ii)Reduce the following function using K-map technique )

f (A, B, C, D) = (0, 3, 4, 7, 8, 10, 12, 14) + d (2, 6) .

(10)

Answer Key:

K-map

(6)

Simplification

(4) 15. Simplify the following Boolean function by using Quine Mcclusky method

F(A,B,C,D)= (0, 2, 3, 6, 7, 8, 10, 12, 13).

(16)(AU ND 2009) Answer Key:

Arrange all minterms according to the number of 1s(2) Combine the minterms into a group of two




(4)16. (i)Express the Boolean function F=A+BC in a sum of minterms

(06) (AU AM 2011)

Answer Key:

Simplification of Boolean Expression

(3)

Boolean Law

(3)

(ii)Simplify the Boolean function using K-map F(w,x,y,z)= (0,1,2,4,5,6,8,9,12,13,14)

(10) (AU AM 2011)

Answer Key:



(5)17. (i)Simplify the following Boolean function by using a Quine-McCluskey method. F(A,B,C,D)- m(0,2,3,6,7,8,10,12,13)


Arrange all minterms according to the number of 1s(2) Combine the minterms into a group of two



(2)(ii)Draw the schematic and explain the operation of a CMOS inverter.Also explain its characteristics.

(08) Answer Key:

Circuit diagram

(3)

Explanation

(3) Characteristics

(2) UNIT-II COMBINATIONAL CIRCUITS PART A (2 MARKS)

1. What do you mean by weighted code ?

(AU AM 2015) In weighed codes, each digit position of the number reperents a specific weight for example in decimal code, if number is 567 the weight of 5 is 100, weight of 6 is 10 and weight of 7 is 1. In weighed binary codes each digit has weight 8,4,2 or 1.2. Draw the symbol and truth table for JK flip flop.

(AU AM 2015)

JKQn+1

0

0

1

10

1

0

1Qn

0

1

Qn

3. Draw the logic circuit for a 2bit comparator.

(AU MJ 2014)

4. What is priority encoder?

(AU MJ 2014) Apriority encoderis a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of apriority encoderis the binary representation of the original number starting from zero of the most significant input bit.5. Enumerate some of the combinational circuits.

(AU ND 2013) The list of the combinational circuits are

1. Encoder

5. Adder

2. Decoder

6. Substractor3. Multiplexer

7. Code converters

4. Demultiplexer

8. Comparator6. List out various applications of Multiplexer.

(AU ND 2013) Some of the applications of multiplexer are as follows:

1. It is used as selector to select one out of many data inputs.

2. They are used in A/D and D/A converter.

3. They are in Time and Frequency multiplexing systems.

4. They are used in data acquisition systems.7. Design Half substractor using basic gates.

(AU MJ 2013)

8. Draw the logic diagram of a 4 line to 1 line Multiplexer.

(AU MJ 2013)

9. Draw the logic diagram of serial adder.

(AU ND 2012)

10. Design a three bit even parity generator.

(AU ND 2012)Logic diagram:

Truth table:Sl.No.MessageParity

10000

20011

30101

40110

51001

61010

71100

81111

11. Implement the following function using a multiplexer F(A,B,C)=(1,3,5,6)Form the above given problem, n=3 i.e., number of variables 3.

(AU ND 2011)

Total no.of inputs = 2n-1

= 23-1 = 4 I0I1I2I3

0123

4567

01AA

A

A

12. Write down the truth table of a full subtractor.

(AU ND 2011)D=Bin +(A+B);

Bout =B+Bin +B BinINPUTSOUTPUTS

ABBinDBout

00000

00111

01011

01101

10010

10100

11000

11111

13. Write the logic expression for the difference and borrow of a half subtractor.

Logic equations are:

(AU AM 2011) 14. Design a single bit magnitude comparator to compare two words A and B. (AU AM 2011)

15. Distinguish between a decoder and demux.

(AU ND2010)DecoderDemultiplexer

1. Decoder has many inputs to many output devices.1. Demultiplexer has one input to many output devices.

2. There are no selection lines2. The selection of specific output line is controlled by the value of selection lines.

16. Write an expression for borrow and difference in a full Subtractor circuit. Logic equations are:

(AU AM 2010)

17. Draw the circuits diagram for 4 bit Odd parity generator.

(AU AM 2010) The function of the 4 bit odd parity generator is P= (AB)(CD)

18. Suggest a solution to overcome the limitations on the speed of an Adder.(AU ND 2009) It is possible to increase speed of adder by eliminating inter-stage carry delay. This method utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be generated.19. What is the difference between half adder and full adder?

(AU MJ 2009)Half adderFull adder

2 inputs & 2 outputs3 inputs & 2 outputs

It performs half addition. So the output is 22

Sum=AB+AB=A+B

Carry=ABIt performs three inputs double the half adder.

Sum=C in+ (A + B)

Carry=AB+BCin+CinA

20. Differentiate a decoder from a demultiplexer.

(AU ND 2009)DecoderDemuliplexer

Many inputs to many outputs device.One input to many outputs device.

They are no selection linesSelection of specific output line is controlled by the value of selection line.

PART B

1. (i) Deisgn and implement an 8x1 multiplexer using suitable gates.(8) (AU AM 2015)Answer Key:

Explanation

(4) Block Diagram Explanation

(4) Block Diagram

(4) 2. (i) Design a 4 bit decimal adder using 4 bit binary adders.

(8)(AU ND 2014) Answer Key:

Explanation

(4) Block Diagram of 4 bit decimal adder

(4) (ii) Implement the following boolean functions using multiplexers(8) F(A,B,C,D)=m(0,1,3,4,8,9,15)Answer Key:


(4) Simplify the Boolean Expression using multiplexers(4)3. (i) Design a 4bit magnitude comparator with 3 outputs : A>B,A=B,A

finl digital qb.doc

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