figures ch 11 - crc press ch 11.pdfe1_err e2_err e4_err e8_err mr3_err mr5_err mr6_err mr7_err...

Chapter 11 Additional Design Examples 1

Verilog HDL:Digital Design and Modeling

Chapter 11

Additional Design Examples

Additional Figures


Page 602

a

y1 y2 y30 0 0

b1 0 0

c1 1 0

d1 1 1

e0 1 1

f0 0 1

Figure 11.1 State diagram for a Johnson counter with a nonsequential countingsequence. There are two unused states, y1 y2 y3 = 010 and 101.

Page 603

0 0 0 1 1 1 10y2y3

y1

0 1 0 0 –

1 1 – 0 1

0 1 3 2

4 5 7 6

Dy1

0 0 0 1 1 1 10y2y3

y1

0 0 0 0 –

1 1 – 1 1

0 1 3 2

4 5 7 6

0 0 0 1 1 1 10y2y3

y1

0 0 0 1 –

1 0 – 1 1

0 1 3 2

4 5 7 6

Dy2

Dy3

Figure 11.2 Input maps for the Johnson counter of Figure 11.1 using D flip-flops. The unused states are y1 y2 y3 = 010 and 101.


Page 603

Dy1 = y3'

Dy2 = y1

Dy3 = y2 (11.1)

y1

D

>

δ Y λ

y2

D

>

y3

D

>

+Clock

–y3 +y1

+y1 +y2

+y2

–y3

inst1

inst2

inst3+y3

Figure 11.3 Logic diagram for the Johnson counter of Figure 11.1 using D flip-flops.


Page 607

CTR3

2

1

0

>rst_n

SRG3

2

1

0

>rst_n

–rst_n

–shftr[0]

–clk

+clk

+sngl_1

–shftr[1]–shftr[2]

+dbl_1

+shftr[2]

+shftr[1]

+shftr[0]

inst1

inst2

inst3

inst4

inst5

inst6

inst5

ctr[0]

ctr[1]

ctr[2]

net1

net2

serial_in

shftr_clk

+ctr[2]+ctr[1]+ctr[0]

Figure 11.8 Logic diagram for the counter-shifter.


Page 611

Table 11.1 Functions for the Universal Shift Register

Function Function Code Shift Amount (right/left)NOP (No operation) 00 00Shift right 01 01Shift left 10 10Load 11 11

Universal

Shift Register

shift_amt [1:0]

clk

rst_n

data_in [7:0]

fctn [1:0]

q [7:0]

(a)

data_in [7] data_in [0]

q [7] q [0]

7 6 5 4 3 2 1 0

(b)

Figure 11.14 Universal shift register.


18

m1, m2, ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ , mm p1, p2, ⋅ ⋅ ⋅ , pk

Code word (n bits)

Message word Parity check word(k bits)(m bits)

Code word X = x1, x2, ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ , xm, xm + 1, ⋅ ⋅ ⋅ , xn

Figure 11.18 Code word of n bits containing m message bits and k parity check bits.

Page 621

p1, p2, m3, p4, m5, m6, m7, p8, m9, m10, m11, m12

where m3, m5, m6, m7, m9, m10, m11, m12 are the message bits and p1, p2, p4, p8 are the parity check bits for groups E1, E2, E4, E8, respectively, as shown below.

Group E1 = p1 m3 m5 m7 m9 m11Group E2 = p2 m3 m6 m7 m10 m11Group E4 = p4 m5 m6 m7 m12Group E8 = p8 m9 m10 m11 m12


Page 622

p1 p2 m3 p4 m5 m6 m7

Message to be sent 0 1 1 0

Code word sent 0 0 0 1 1 1 0Code word received 0 0 0 1 0 1 0

Group E1 = p1 m3 m5 m7 = 0 0 0 0 = Error = 1Group E2 = p2 m3 m6 m7 = 0 0 1 0 = No error = 0Group E4 = p4 m5 m6 m7 = 1 0 1 0 = Error = 1

22 21 20

Groups E4 E2 E1Syndrome word 1 0 1


Page 623

Table 11.2 Examples of Single Error Correction and Double Error Detection

Code Word Format Syndrome Code WordParity

SingleError

DoubleErrorp1 p2 m3 p4 m5 m6 m7 pcw E4E2E1

Sent 0 0 1 1 0 0 0 1Received 0 0 0 1 0 0 0 1 0 1 1 Bad Yes No

Sent 0 0 0 1 1 1 0 0Received 0 1 0 1 1 1 0 0 0 1 0 Bad Yes No

Sent 1 0 0 1 1 0 1 1Received 1 1 0 1 0 0 1 1 1 1 1 Good No Yes

Sent 0 0 1 1 0 0 0 1Received 0 0 1 1 0 1 1 1 0 1 1 Good No Yes

Sent 0 0 1 1 0 0 0 1Received 0 0 1 1 0 0 0 0 0 0 0 Bad No No

01234567

DX +m3

Data bus reg

Data bus

p1

m3

p4

m5

m6

m7

p20

1

2

2k+1

2k+1

2k+1

+p1+m3+m5+m7

+p2+m3+m6+m7

+p4+m5+m6+m7

+m5

+m6

+m7

Syndrome word Valid data

Figure 11.20 Hamming code error detection and correction.


Page 625

DX 4:16

0

1

2

3

0

1

2

3

4

5

6

7

8

9

10

11

12

m3m5m7m9m11

m3m6m7m10m11

m5m6m7m12

m9m10m11m12

p1

p2

p4

p8

mr3mr5mr7

mr11

mr3mr6mr7mr10mr11

mr9

mr5mr6mr7mr12

mr9mr10mr11mr12

e1_err

e2_err

e4_err

e8_err

mr3_err

mr5_err

mr6_err

mr7_err

mr9_err

mr10_err

mr11_err

mr12_err

mr3

mr5

mr6

mr7

mr9

mr10

mr11

mr12

mv3

mv5

mv6

mv7

mv9

mv10

mv11

mv12

e1_err

e2_err

e4_err

e8_err

task pbit_generate

task error_inject

define error bits

decoder

error correction logic

Figure 11.21 Logic diagram for the Hamming code error detection and correctioncircuit of Examlple 11.2.


Page 626

Bit position = 11 10 9 8 7 6 5 4 3 2 1 0Data = m3 m5 m6 m7 m9 m10 m11 m12 p1 p2 p4 p8

The statement error_inject (11) passes the constant 11 to the task as the bit_number. Then the statement

bit_position = 1' b1 << bit_number

shifts a 1 bit eleven bit positions to the left to location m3. The message bit m3 is ex-clusive-ORed with the 1 bit as shown below, thereby inverting m3. The message con-taining the error is then passed back to the task invocation as the received message, which is then corrected by the error correction logic. In a similar manner, errors are in-jected into message bits m7, m9, and m12.

Data = m3 m5 m6 m7 m9 m10 m11 m12 p1 p2 p4 p8

XOR = 1 0 0 0 0 0 0 0 0 0 0 0Received

message =m3 ' m5 m6 m7 m9 m10 m11 m12 p1 p2 p4 p8


Page 631

Multiplier

i + k + 1 i + k i + k – 1 . . . i + 1 i i – 1

0 0 1 1 1 0. . .

k consecutive 1s

In the sequential add-shift method, the multiplicand would be added k times to the shifted partial product. The number of additions can be reduced by the following property of binary strings:

2i + k – 2i = 2i + k – 1 + 2i + k – 2 + ⋅ ⋅ ⋅ 2i + 1 + 2i (11.2)

The right-hand side of the equation is a binary string that can be replaced by the dif-ference of two numbers on the left-hand side of the equation. Thus, the k consecutive 1s can be replaced by the following string:

Multiplier

i + k + 1 i + k i + k – 1 . . . i + 1 i i – 1

0 +1 0 0 –1 0. . .

k – 1 consecutive 0s

Addition of themultiplicand

Subtraction of themultiplicand


Page 632

2i + k

2i + 4

25 24 23 222i

21 20

Multiplier 0 1 1 1 1 0 +30

k = 4

The validity of Equation 11.2 can be verified using the multiplier of +30 shown above.

2i + k 2i = 2i + k – 1

25 – 21 = 24 + 23 + 22 + 21

32 – 2 = 16 + 8 + 4 + 230 = 30

Thus, the multiplier 011110 (+30) can be regarded as the difference of two numbers: 32 – 2, as shown below.

0 1 0 0 0 0 0 (32)–) 0 0 0 0 0 1 0 (2)

0 0 1 1 1 1 0 (30)

The product can be generated by one subtraction in column 2i and one addition in col-umn 2i + k, as shown below; that is, by adding 32 and subtracting 2. In this case, adding 25 times the multiplicand and subtracting 21 times the multiplicand yields the appro-priate result.

26 25 24 23 22 21 20

Standard multiplier 0 0 +1 +1 +1 +1 0← k = 4 →

Recoded multiplier 0 +1 0 0 0 –1 0 ←k – 1=3→


Page 633

Table 11.3 Booth Multiplier Recoding Table

MultiplierBit i Bit i – 1 Version of Multiplicand0 0 0 × multiplicand0 1 +1 × multiplicand1 0 –1 × multiplicand1 1 0 × multiplicand

Standard sequential add-shiftMultiplicand 0 0 1 1 0 1 0 1 +53Multiplier ×) 0 0 0 1 1 1 1 0 +30

0 0 0 0 0 0 0 00 0 1 1 0 1 0 1

0 0 1 1 0 1 0 10 0 1 1 0 1 0 1

0 0 1 1 0 1 0 10 0 0 0 0 0 0 0

0 0 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 1 1 0 0 0 1 1 0 1 1 0 +1590

Page 634Booth algorithmMultiplicand 0 0 1 1 0 1 0 1 +53Recoded multiplier ×) 0 0 +1 0 0 0 –1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1 0 0 1 0 1 10 0 0 0 0 1 1 0 1 0 10 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 +1590


Page 634

Multiplicand 0 1 1 0 1 +13Multiplier ×) 1 0 1 0 0 –12

–156

Booth algorithmMultiplicand 0 1 1 0 1 +13Recoded multiplier ×) –1 +1 –1 0 0

0 0 0 0 0 0 0 0 0 01 1 1 1 0 0 1 10 0 0 1 1 0 11 1 0 0 1 11 1 0 1 1 0 0 1 0 0 –156

-----------------------------------------------------------------------------------------------------

Page 634Multiplicand 0 1 1 1 1 +15Multiplier ×) 0 0 0 1 1 0 +3

+45

Page 635Booth algorithmMultiplicand 0 1 1 1 1 +15Recoded multiplier ×) 0 0 +1 0 –1

1 1 1 1 1 1 0 0 0 10 0 0 0 1 1 1 10 0 0 0 1 0 1 1 0 1 +45


Page 635

Multiplicand 1 0 1 1 0 1 –19Multiplier ×) 0 0 1 1 1 0 +14

–266

Booth algorithmMultiplicand 1 0 1 1 0 1 –19Recoded multiplier ×) 0 +1 0 0 –1 0

0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 1 11 0 1 1 0 11 0 1 1 1 1 0 1 1 0 –266

----------------------------------------------------------------------------------------------------

Multiplicand 1 0 0 1 1 –13Multiplier ×) 1 1 0 0 1 0 –7

+91

Page 635

Booth algorithmMultiplicand 1 0 0 1 1 –13Recoded multiplier ×) 0 –1 0 +1 –1

0 0 0 0 0 0 1 1 0 11 1 1 1 1 0 0 1 10 0 0 1 1 0 10 0 0 1 0 1 1 0 1 1 +91

Page 636


Page 636

Multiplicand 0 1 0 0 1 1 +19Multiplier ×) 1 1 0 1 0 1 0 –11

–209

Booth algorithmMultiplicand 0 1 0 0 1 1 +19Recoded multiplier ×) 0 –1 +1 –1 +1 –1

1 1 1 1 1 0 1 1 0 10 0 0 0 1 0 0 1 11 1 1 0 1 1 0 10 0 1 0 0 1 11 0 1 1 0 11 1 0 0 1 0 1 1 1 1 –209

----------------------------------------------------------------------------------------------Page 637

Multiplicand 0 1 1 1 +7Multiplier ×) 0 1 0 1 0 +5

+35

Booth algorithmMultiplicand 0 1 1 1 +7Recoded multiplier ×) +1 –1 +1 –1

pp1 1 1 1 1 1 0 0 1pp2 0 0 0 0 1 1 1 0pp3 1 1 1 0 0 1 0 0pp4 0 0 1 1 1 0 0 0

0 0 1 0 0 0 1 1 +35

a_nega_ext_nega_ext_pos


Page 642

b1 0 1

c0 1 1

dz1

0 0 0

a

y1 y2 y3 0 0 1

ez2

1 1 1

z1↑t1↓t3 z2 ↑t1↓t

x1

x1'

x1' x1'

x1 x1

Figure 11.29 State diagram for the Moore machine of Section 11.6.

Moorestructural

synchronoussequentialmachine

clkx1

set1_nset2_nset3_n

rst1_nrst2_nrst3_n

y[1:3]

y_n[1:3]

z1

z2

Figure 11.30 Block diagram for the Moore machine of Section 11.6.


Page 643

y3

D

>

S

R

y2

D

>

S

R

y1

D

>

S

R

+clk

–set3_n

–set1_n

–set2_n

net1

inst10

–rst1_n

–rst2_n

–rst3_n

net2net3

net5

net6

net7

net9net11

inst1

inst2inst3

inst4

inst5

inst6

inst7inst8

inst9inst11

inst12

inst14

–y2+y3–x1–y1+y2+x1

+y1

inst13 +z1

+z2

+y1

–y1

+y2

–y2

+y3

–y3

net10

inst13

inst14

Figure 11.31 Logic diagram for the Moore machine of Figure 11.29.


Page 650

a

y1 y2 0 0

z1

b0 1

c1 0

x1

x2

x2

x1

x1

x2

Figure 11.36 State diagram for the Mealy pulse-mode machine of Section 11.7.

Page 651

y1

y2 0

0 r r

1

1 R –

0 1

2 3

y1

y2 0

0 r S

1

1 R –

0 1

2 3

y1

y2 0

0 S s

1

1 S –

0 1

2 3

y1

y2 0

0 r R

1

1 r –

0 1

2 3

x1 x2Inputs

Latches

y1

y2

Figure 11.37 Input maps for the Mealy pulse-mode machine of Figure 11.36.


Page 652

y1

D

>

S

R

y2

D

>

S

R

–set_n

+x1+x2

+y2

+y1

–x1

–x2

–rst_n

+z1

+y1

+y2

inst1

inst2

inst3 inst4

inst5

inst6

inst7

inst8

inst9

inst10

inst11

net1

net2

net3net4

net5

net8

net9

net6

inst1

Ly1

Ly2

Figure 11.39 Logic diagram for the Mealy pulse-mode machine of Figure 11.36.


Page 657

a

y1 y2 y31 0 0

z1

b0 1 0

c0 0 1

x1

x1'

x1'x1

x1'x1

z1

Figure 11.44 State diagram for the Mealy one-hot machine of Section 11.8.


Page 658

0 0 0 1 1 1 10y2y3

y1

0 – x1 – 0

1 x1' – – –

0 1 3 2

4 5 7 6

0 0 0 1 1 1 10y2y3

y1

0 – 0 – x1'

1 x1 – – –

0 1 3 2

4 5 7 6

0 0 0 1 1 1 10y2y3

y1

0 – x1' – x1

1 0 – – –

0 1 3 2

4 5 7 6

Dy1

Dy2

Dy3

Dy1 = y3 x1 + y1 x1'

Dy2 = y1 x1 + y2 x1'

Dy3 = y2 x1 + y3 x1'

(a)

0 0 0 1 1 1 10y2y3

y1

0 – x1 – 0

1 x1 – – –

0 1 3 2

4 5 7 6

z1

z1 = y2 ' x1

(b)

Figure 11.45 (a) Input maps and (b) output map for the Mealy one-hot machine of Figure 11.44.


Page 659

y1

D

>

S

R

y2

D

>

S

R

y3

D

>

S

R

–set_n_y1

+y3+x1

+y1–x1

+y2

+clk

–rst_n_y1y2

+z1

+y1

+y2

+y3

inst1

inst2

inst3inst4

inst5

inst6

inst7inst8

inst9

inst10

inst11inst12

inst13

net1

net2

net3

net5

net6

net7

net9

net10

net11

–rst_n_y1

–set_n_y1y2

Figure 11.46 Logic diagram for the Mealy one-hot machine of Figure 11.44.


Page 665

a

y1 y2 y31 0 0

z1

b0 1 0

c0 0 1

z1

x1

x1'

x1'x1

x1'x1

Figure 11.51 State diagram for a Mealy one-hot sequential machine.


Page 670

Operand B Operand A

Result

CinCout Decimal arithmetic element

Figure 11.56 Decimal arithmetic element.

Page 67268 0110 1000

+ ) 35 0011 0101103 1 ← 1101

1 ← 1010 01100110 00110000

0001 0000 0011

96 1001 0110+ ) 93 1001 0011

189 1 ← 0010 100101101000

0001 1000 1001


Page 673

76 0111 0110– ) 42 +) 0101 1000

34 1 ← 11101 ← 1101 0110

0110 01000011

+ 0011 0100

76 0111 0110– ) 87 +) 0001 0011

–11 (89) 0 ← 1000 1001

– 1000 1001


Page 674

Table 11.5 Nines Complementer

Subtrahend 9s Complement

b3 b2 b1 b0 f3 f2 f1 f00 0 0 0 1 0 0 10 0 0 1 1 0 0 00 0 1 0 0 1 1 10 0 1 1 0 1 1 00 1 0 0 0 1 0 10 1 0 1 0 1 0 00 1 1 0 0 0 1 10 1 1 1 0 0 1 01 0 0 0 0 0 0 11 0 0 1 0 0 0 0

9s complementer

b[3:0]

m

f [3:0]

Figure 11.57 Block diagram for a 9s complementer.


Page 675

f0 = b0 ⊕ m

f1 = b1

f2 = m' b2 + m(b2 ⊕ b1)

f3 = m' b3 + m b3' b2' b1' (11.6)

+b[0]+m

+b[1]

–m+b[2]

+b[3]–b[3]

–b[2]

–b[1]

inst1

inst2

inst3 inst4 inst5

inst6

inst7

inst8

net2

net3 net4

net6

net7

+f[0]

+f[1]

+f[2]

+f[3]

Figure 11.58 Logic diagram for a 9s complementer.


Page 680

a[0]a[1]a[2]a[3]

b[0]b[1]b[2]b[3]

m

bcd[0]0

1

2

3

cout

cin

A

B

Adder

0

1

2

3

cout

cin

A

B

Adder

9s f [0]f [1]f [2]f [3]

0

0

bcd[1]

bcd[2]

bcd[3]

sum[0]

sum[1]

sum[2]

sum[3]

cout3

net3

net4

inst1

inst2

inst3

inst4inst5

inst6

aux_cy

a[4]a[5]a[6]a[7]

b[4]b[5]b[6]b[7]

bcd[4]0

1

2

3

cout

cin

A

B

Adder

0

1

2

3

cout

cin

A

B

Adder

9s f [4]f [5]f [6]f [7]

0

0

bcd[5]

bcd[6]

bcd[7]

sum[4]

sum[5]

sum[6]

sum[7]

cout7

net9

net10

inst7

inst8

inst9

inst10inst11

inst12

cout

0

0

Figure 11.62 Logic diagram for a BCD adder/subtractor.


Page 686

Memory data bus

3 2 1 0Ibufr A Ibufr B

A full B full

IPC 00 01 10 11

Mux arrayS0S1

IPC 1IPC 2

3 2 1 0Opcode

IR

3 2 1 0

Figure 11.67 Instruction buffer for 2- and 4-byte instructions.


Page 687

Ifetch Decode Execute Store






Ifetch Decode Execute Store Ifetch Decode Execute Store

One clock cycle

Figure 11.68 Example of a 4-stage pipeline.

Iunit Decode Eunit Store

Interstage buffers

Figure 11.69 Four stages of a pipeline showing the interstage storage buffers.


Page 689

where RRR specifies one of eight registers(0 – 7) for opnd A, opnd B, and Dst.

Op Code Opnd A Opnd B Dst

nnnn RRR RRR RRR

12 9 8 6 5 3 2 0

Op Code Opnd A Dst

1110 (Load) 0 Memory address 0 RRR

12 9 8 7 4 3 2 0

Op Code Opnd A Dst

1111 (Store) 00 RRR Memory address

12 9 8 7 6 4 3 0

Figure 11.70 Instruction format for the pipelined RISC processor.


Page 690

icache iunit decode eunit dcache

0

31

0

15

ir

pc

instruction

iu_pc

13

5

decoder

clk

dcaddr

ctrl

dcaddr

opnda

dst

opndbalu

01234567

regfile

dst

rslt

4

8

eu_dcaddr

eu_dcenbl

eu_result

dc_dataout

11

4

3

3

3

3

opcode

8

8

rst_n

13iu_instr

amux

bmuxmux

du_opcodeopcode

du_dstin

du_addrin

du_opnda_addr

du_opndb_addr

4

eu_reg_wr_vld

opcode_out

>

>

>

>

> >

>

>

8>

>

>

+1

1

eu_load_op1

clkrst_n

regfile0:7_out

eu_dst

eu_rdwr

Figure 11.71 Architecture for the pipelined RISC processor of Section 11.10.


Page 691

icacheicache_tb

iunitiunit_tb

decodedecode_tb

euniteunit_tb

regfileregfile_tb

dcachedcache_tb

structuralsystem_top_tb

structural risc_cpu_top

structural system_top

structural risc_cpu_topclk

rst_neu_dcaddr

eu_result

eu_rdwr


clk rst_n

iunitiunit_tb

decodedecode_tb

euniteunit_tb

regfileregfile_tb

iu_pcdc_dataout

icache dcache

instruction

eu_dcenbl


risc risc risc risc risc risc

risc risc risc risc

risc

risc

risc risc

risc

Figure 11.72 Structural block diagram for the pipelined RISC processor of Section 11.10.


Page 692

Table 11.7 Instruction Cache Contents

Address Operation Op Code Opnd A Opnd B Dst00000 LD 1110 0 0000 Not used 000000001 LD 1110 0 0001 Not used 000100010 LD 1110 0 0010 Not used 001000011 LD 1110 0 0011 Not used 001100100 LD 1110 0 0100 Not used 010000101 LD 1110 0 0101 Not used 010100110 LD 1110 0 0110 Not used 011000111 LD 1110 0 0111 Not used 011101000 ADD 0001 000 001 00001001 SUB 0010 111 110 00101010 AND 0011 010 101 01001011 OR 0100 011 100 01101100 XOR 0101 100 100 10001101 INC 0110 101 000 10101110 DEC 0111 110 000 11001111 NOT 1000 111 000 11110000 NEG 1001 000 000 00010001 SHR 1010 001 000 00110010 SHL 1011 010 000 01010011 ROR 1100 011 000 01110100 ROL 1101 100 000 10010101 ST 1111 00 000 Not used 100010110 ST 1111 00 001 Not used 100110111 ST 1111 00 010 Not used 101011000 ST 1111 00 011 Not used 101111001 ST 1111 00 100 Not used 110011010 ST 1111 00 101 Not used 110111011 ST 1111 00 110 Not used 111011100 ST 1111 00 111 Not used 111111101 NOP 0000 000 000 00011110 NOP 0000 000 000 00011111 NOP 0000 000 000 000


Page 693

Table 11.8 Data Cache Contents

Address Data

SRC

0000 0000 00000001 0010 00100010 0100 01000011 0110 01100100 1000 10000101 1010 10100110 1100 11000111 1111 1111

DST

1000 0000 00001001 0000 00001010 0000 00001011 0000 00001100 0000 00001101 0000 00001110 0000 00001111 0000 0000

Table 11.9 Register FileContents before Execution

Address Data000 0000 0000001 0010 0010010 0100 0100011 0110 0110100 1000 1000101 1010 1010110 1100 1100111 1111 1111

Table 11.10 Register FileContents after Execution

Address Data000 1101 1110001 0001 1001010 0000 0000011 0111 0111100 0000 0000101 1010 1011110 1100 1011111 0000 0000


Page 694

instruction(To iunit)

pc(From iunit)

0

31

13 instruction

risc_pc5

Figure 11.73 Instruction cache for the pipelined RISC processor.


Page 695

clk

rst_n

instruction

pc

(From icache)

(To icache)

(To decode)>ir

13

5

13

ir

pc>

+1

clk

rst_n

instruction

iu_pc

iu_instr

Figure 11.74 Instruction unit for the pipelined RISC processor.


Page 696

clk

rst_n instr

(From iunit)

(To eunit)>opcode

13

4 du_opcode

decoder

(To eunit)>dcaddr 4 du_dcaddr

(To eunit)>opnda 3 du_opnda_addr

(To eunit)>opndb 3 du_opndb_addr

(To eunit)> dst 3 du_dst

iu_instr

opcode

dcaddr

opnda

opndb

dst

Figure 11.75 Decode unit for the pipelined RISC processor.


Page 697

clk

rst_n

>opcode4du_opcode

ctrl

(From decode)

>dcaddr4du_addrin

(From decode)3du_opnda_addr

> rslt3du_opndb_addr

> dst3du_dstin

(From decode)

(From decode)

(From decode)

alu

muxb

muxa

regfile0:7_out 8(From regfile)

opcode_out

eu_load_op1(To regfile)

eu_dcenbl

eu_rdwr

eu_reg_wr_vld

1

1

1

(To dcache:2 ports)

(To regfile)

eu_dcaddr(To dcache)

eu_result

(To dcache)(To regfile)

eu_dst(To regfile)

8

4

3

opcode

dcaddrin

(8 ports) regfile0:7

opnda_addr

opndb_addr

dstin

dcenblrdwr

reg_wr_vld

load_op

dcaddr

rslt

dst

Figure 11.76 Execution unit for the pipelined RISC processor.


Page 698

clk

rst_n

eu_rslt(From eunit)

8(8 ports: To eunit)

8 regfile0:7_out

eu_reg_wr_vld 1

eu_load_op 1

eu_dst 3

dcdataout 8

(From eunit)

(From eunit)

(From eunit)

(From dcache)

0

7

reg_wr_vld

load_op

dst

rslt

dcdataout

regfile0:7

Figure 11.77 Register file for the pipelined RISC processor.


Page 699

(To regfile)8dc_dataout

risc_dcenbl 1

risc_rdwr 1

risc_dcaddr 4

risc_rslt 8

(From eunit)

(From eunit)

(From eunit)

(From eunit)

0

15

dcdataout

dcdatain

dcenbl

rdwr

dcaddr

Figure 11.78 Data cache for the pipelined RISC processor.


Page 715

Table 11.11 Instructions for the Execution Unit

Instruction Functionnop No operation is performedadd Operand A plus operand Bsub Operand A minus operand Band Operand A AND operand Bor Operand A OR operand Bxor Operand A exclusive-OR operand Binc Increment operand A by 1dec Decrement operand A by 1not Form the 1s complement of operand Aneg Form the 2s complement of operand Ashr Shift right logical operand Ashl Shift left logical operand Aror Rotate right operand Arol Rotate left operand Ald Load register file from memoryst Store register file to memory


Page 716

muxa[0]s0s1s2

d0

d7

.

.

.

.

.

.

opnda_addr

regfile0[0]

regfile7[0]

oprnd_a[0]

muxa[7]s0s1s2

d0

d7

.

.

.

.

.

.

opnda_addr

regfile0[7]

regfile7[7]

oprnd_a[7]

... reg [7:0] oprnd_a

muxb[0]s0s1s2

d0

d7

.

.

.

.

.

.

opndb_addr

regfile0[0]

regfile7[0]

oprnd_b[0]

muxb[7]s0s1s2

d0

d7

.

.

.

.

.

.

opndb_addr

regfile0[7]

regfile7[7]

oprnd_b[7]

... reg [7:0] oprnd_b

Figure 11.93 Multiplexer array input to the execution unit ALU.


Page 728

MUXs0

d0d1

01234567

DX 3:8

+dst[0]

+dst[1]

+dst[2]

0

1

2

>En

Rst>

d0

d7

regfile7

d1d2d3d4d5d6

>En

Rst>

d0

d7

regfile0

d1d2d3d4d5d6

.

.

.

regfile_sel

reg_mux_sel

+load_op

+rslt[7:0]+dcdataout[7:0]

+reg_wr_vld

reg_data_in[7:0]

–rst_n

+clk

regfile0_enblEnbl

Figure 11.98 Register file and the associated control logic.


Page 739

structural risc_cpu_topclk

rst_neu_dcaddr

eu_result

eu_rdwr

iunitiunit_tb

decodedecode_tb

euniteunit_tb

regfileregfile_tb

iu_pcdc_dataout

instruction

eu_dcenbl

risc risc risc risc

Figure 11.107 Structural organization of the RISC CPU top level.

Page 742

structuralsystem_top_tb


clk rst_n

icache dcache


risc

risc risc

Figure 11.109 Structural organization

figures ch 11 - crc press ch 11.pdfe1_err e2_err e4_err e8_err mr3_err mr5_err mr6_err mr7_err...

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