figure 1: ml300 cpu table 1: ml300 cpu virtex-ii pro based … · 2020-06-30 · figure 2: ml300...
TRANSCRIPT
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ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
Port
SerialPorts
CPU TraceConnector
BDMConnector
Display
PS/2
Parallel
BP
Bridge
CardBus B
PCI4451PCI to
1394IEEE
Phy
TFT
Board Block Diagramand Table of Contents
Sheet 1: Block Diagram and Table of Contents
SystemACE
CardBus A
PowerBoardConnector
Audio
Codec
Sheet 6: BOM (1 of 4)
Sheet 10: Net Classes (1 of 2)Sheet 9: BOM (4 of 4)Sheet 8: BOM (3 of 4)Sheet 7: BOM (2 of 4)
Sheet 11: Net Classes (2 of 2)
Sheet 2: Clocking Diagram
Sheet 19: FPGA Bank 7 - DDR + Parallel Port
Sheet 25: FPGA Bypass Caps
Sheet 41: SPI EEPROM
Sheet 43: Ethernet Power
Sheet 51: CardBus connectorsSheet 52: PCI Bus TerminationSheet 53: CardBus power supply
Sheet 3: Configuration/Debug Diagram
Sheet 29: DDR Control Signal Registers
General
PurposeLEDs/BTNs
Virtex-II Pro
Infiniband Gig-E Serial
Virtex-II Pro Based
Block Diagram
Figure 1: ML300 CPU
Sheet 4: FPGA Banking Diagram
Sheet 50: PCI to Carbus converter
Table 1: ML300 CPU
Virtex-II Pro Based
Table of Contents
128 MB DDR SDRAM Discretes
CardBus
ATAFiberHSSCD2(Dual) (Quad) (Dual)
8 MGTs
Ethernet
SPI
IIC
ScreenTouch
Sheet 5: Index of Primary Component
Sheet 12: FPGA Bank 0 - Ethernet Phy, PS/2 Ports, Gig-E ClockSheet 13: FPGA Bank 1 - System Clock, PMC Gen Purp, SysACE Clk
Sheet 15: FPGA Bank 3 - PMC Gen Purp, Audio, PCI, IICSheet 14: FPGA Bank 2 - PMC Gen Purp, Audio, PCI, IIC
Sheet 16: FPGA Bank 4 - TFT, Serial Ports, Uer MGT ClockSheet 17: FPGA Bank 5 - System ACE, CPU Trace, HSSDC2 ClockSheet 18: FPGA Bank 6 - CPU Debug, GP Buttons, DDR
Sheet 20: FPGA Configuration and Miscellaneous
Sheet 21: FPGA MGT Bottom - Serial ATA and HSSDC2Sheet 22: FPGA MGT Top - Gigabit Ethernet FiberSheet 23: Gig Ethernet Fiber TransceiverSheet 24: MGT Linear Regulators
Sheet 27: System ACE - Configuration and StorageSheet 28: DDR Clock Replicator
Sheet 30: DDR Memory Components
Sheet 31: DDR Termination - 1 of 2 (Address and Control)
Sheet 33: DDR Switching RegulatorSheet 34: DDR Bypass Capacitors and Placement DiagramSheet 35: Illumination LEDs and Placement DiagramSheet 36: Serial Transceivers and PortsSheet 37: PS/2 Level Shifter and PortsSheet 38: Parallel Port Clamp DiodeSheet 39: Parallel Transceiver, Port and LEDsSheet 40: IIC Bus - Temp, Power Monitor, EEPROM and Trimpot
Sheet 42: Ethernet Phy and Port
Sheet 44: Level Shifter for TFT, JTAG and Bus ErrorSheet 45: Audio Codec and Input Audio JacksSheet 46: Audio Power Amps and Output Audio JackSheet 47: PCI Clamp DiodesSheet 48: PMC Clamp DiodesSheet 49: PMC Connectors and Mounting Holes
Sheet 54: IEEE1394 (FireWire) Phy and Connector
PMC 32/33Sheet 55: Power Supply HeaderSheet 56: Net Class Routing Rules
Sheet 32: DDR Termination - 2 of 2 (Data, Strobe, Mask and Clk)
Sheet 26: Configuration/Debug Connectors - JTAG, Trace, Debug
1 56
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ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
CLK0
FBIN
+-- +
+-
SCREEN
DCM DCM
0P2P4P5S6P7S
0S1P3P4S6S7P
Clock Distribution Diagram
BP
3S 1S
SYSTEMACE
X0Y0 X1Y0
2S
Virtex-II Pro Based
Clocking Distribution Diagram
Figure 2: ML300 CPU
SystemClock100MHz
U16
Fiber125MHz
User CLKSMA Conn
Gig-E
Infiniband
PS/2 #1
PS/2 #2
SYSACECLOCK33MHz
ENET10/100
PHY
SPI
IICBUS
TFT
TOUCH
AC97
DISPLAY
CLKFX
DCMX0Y1
CLKDV
CLK2X
INFB
CLK0
DCMX1Y1
200MHz
33MHz
300MHz
100MHz
Notes:1. Internal clocking structure is design dependent
PHY_TX_CLK(2.5 OR 25MHz)PHY_RX_CLK
DDR_RES_CK_N
DDR_RES_CK
DDR_RES_CK (Feedback)
SYSACE_CLK_OE_N
PCI/PMC_FB
CardBus
PMC_Conn4
PCI/PMC
12.88MHz
DDR PLL
PCIBRIDGE FIREWIRE
24.576MHzX501
24.576MHzX601
25MHzX401
X102
X101
X104OE
156.25MHz
X103
BANK 5 - 2.5V BANK 4 - 2.5V
BANK 3 - 3.3V
BANK 2 - 3.3V
BANK 6 - 2.5V
BANK 0 - 2.5V BANK 1 - 3.3V
5P
D14C14 B14 B13 C13 D13
F13
G13
IIC_SCL
N6
E13
TOUCH_DCLK
M6
AUDIO_BIT_FPGA_CLK
SPI_CLK
W5
TFT_FPGA_CLK
Y13
AC6
AC14 AD13 AE13AD14AE14
PS_2_1_CLK_OUT
PS_2_1_CLK_IN
U22
U21
E16
D16
PS_2_2_CLK_OUT
PS_2_2_CLK_INC15
D15
B19
F18
562
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ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
U28
(2.5V Interface)
2.5V
FPGA_TCKFPGA_TMSFPGA_TDIFPGA_TDO
FPGA_PROG
43
17
5
BP
JTAG / System ACE / Debug Diagram
33
6 2
0
3.3V2.5V 2.5V
CPU_TRSTCPU_HALT
AC24
AE26
AD25
AD26
AC25
AC26
AB23
AB24
CPU_TCKCPU_TMSCPU_TDI
363432
282624
17191121
38
CPU_TDO
AD23
System ACE
U2
U1
P115
TS6TS5TS4TS3
TS2ETS1ETS20TS1O
2.5V
2.5V
30
Figure 3: ML300 CPU
2.5V
(2.5V Interface)
P114
P109
CPU_TMS
CPU_TDI
P6P4P10P8
JTAG_SRC_SELECT
Sys ACEReset
Sys ACECFG Addr
10198
10297
TCKTMSTDITDO
CFG_TCKCFG_TMSCFG_TDOCFG_TDI
CFG_PROGCFG_INIT
VCCIO
MPUIFaceA0
A1
A2
87
86
88
80858281
7978
G8F7H20H7
D22AD6
TCKTMSTDITDO
PROGINIT
2.5V
Sys ACEMPUIFace
Bank 5
2.5V
XC2VP7FF672
BANK 5
2.5V
2.5VBANK 6
TS1O
TS20
TS1E
TS2E
TS3
TS4
TS6
TS5
TRC_CLK
AC20AB20AA20AC21AD21AA19
0
1
0
1
0
1U28
0
1
CPU_TCKCPU_TMSCPU_TDICPU_TDOCPU_TRST
CPU_HALT_N
TRC_CLK
CPU_TCKCPU_TMSCPU_TDICPU_TRST
CPU_HALT_NCPU_TDO
7934
111
15
6
7
Virtex-II Pro Based
LOGICAL Configuration Diagram
TFT_FPGA_HSYNCH
PC4_TCK
CPU_TCK
PC4_TMS
PC4_TDI
SYSACE_TSTTDO
JTAG_SRC_SELECT
SYSACE_TSTTDO
563
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ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
FPGA Banking
Bank 1
Bank 2
Bank 3
Bank 4 Bank 5
Bank 6
Bank 7
Audio
IIC
BP
MGT BLOCKS
MISC FPGA Pins
FPGA Bankout Diagram
Virtex-II Pro Based
TouchScrn
Figure 4: ML300 CPU
PCI
Page 42-43
Ethernet
Page 37
PS/2
Parallel PortPage 38-39
CPU Debug
Page 55Buttons
DDR Memory
Page 26
SysACE CPU TracePage 26Page 27
SPI
Serial
TFT
PMC/GPIOPage 48-49
Banks 0 and 1 - Page 22Banks 4 and 5 - Page 21
Page 20
Bank 0Page 12Page 13
Page 14
Page 15
Page 16 Page 17
Page 18
Page 19
Page 47-52
Page 45-46
Page 40
Page 55
Page 44/55 Page 41
Page 36
Page 28-34
4 55
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Date:
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Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
RefDes Page Description
Virtex-II Pro Based
RefDes Page Description
P107 36 DB9 Serial Port
J104 49 PMC Connector #1J105 49 PMC Connector #2J106 49 PMC Connector #4 DS401 35 Round LED Blue Illumination
DS402 35 Round LED Blue IlluminationDS403 35 Round LED Blue IlluminationDS404 35 Round LED Blue IlluminationDS405 35 Round LED Blue IlluminationDS406 35 Round LED Blue Illumination
DS407 39 LED0603 Yellow Par Port DirectionDS408 39 LED0603 Yellow Par Port User Def 3DS409 39 LED0603 Yellow Par Port User Def 1DS410 39 LED0603 Yellow Par Port NWaitDS411 39 LED0603 Yellow Par Port InterruptDS412 39 LED0603 Green Par Port Data0DS413 39 LED0603 Yellow Par Port NAStrobeDS414 39 LED0603 Yellow Par Port NinitDS415 39 LED0603 Yellow Par Port User Def 2DS416 39 LED0603 Yellow Par Port NDStrobeDS417 39 LED0603 Yellow Par Port NwriteDS418 39 LED0603 Yellow Par Port High DrainDS419 39 LED0603 Green Par Port Data1
DS421 39 LED0603 Green Par Port Data3DS422 39 LED0603 Green Par Port Data4DS423 39 LED0603 Green Par Port Data5DS424 39 LED0603 Green Par Port Data6DS425 39 LED0603 Green Par Port Data7DS426 42 LED0603 Green Ethernet Link Speed
RefDes Page Description
U15 29 SSTV16857 DDR Register
U27 44 74ALVC164245 TFT Level Shifter
U51 47 QS32X2245 PCI Clamp DiodeU52 47 QS32X2245 PCI Clamp DiodeU53 47 QS316211 PCI Clamp DiodeU58 53 TPS2216A PCMCIA Power Regulator
U251 40 MAX1617 FPGA IIC Temp SensorU252 40 LM76CNM_3 IIC Ambient Temp SensorU253 40 24LC32A IIC EEPROMU254 41 25LC160_SN SPI EEPROM
U270 36 MAX3388E UART TransceiverU271 36 MAX3388E UART Transceiver
U501 46 LM4835 Audio AmplifierU502 40 DS1845 IIC Audio Volume Trimpot
U912 48 QS32X2245 PMC Clamp Diode
U914 48 QS32X2245 PMC Clamp Diode
Index of Parts
BP
U14 29 SSTV16857 DDR Register
U19 37 74C914 PS/2 BufferU20 38 QS34XV245 Par Port Clamp Diode
U1 12-22 XC2VP7-FF672
U26 42 LXT971_LQFP64 Ethernet Phy
U28 44 74ALVC164245 TFT Level Shifter
U50 47 QS32X2245 PCI Clamp Diode
U60 26 74ALVC157A JTAG/Trace MUX
U101 24 LT1963-25EQ MGT VCC Linear Reg
U500 45 AD1885 Audio Codec
U601 50 PCI4451GFN PCMCIA to PCI Bridge Oscillator Index (X*)
J2 16 SMA User Clock N-side
J103 55 HDR 2x25 Power Connector
J101 55 HDR 2x32 Digital Connector #1
J204 26 HDR 1x2 JTAG MUX Select
J505 46 Audio Left Speaker JackJ506 46 Audio Right Speaker Jack
U4 13 PCI VCCO Linear Regulator
U2 27 System ACE
P101 39 DB25 Parallel Port
P102 23 GIGE-R14K-ST11 Quad Fiber XCVR
P108 54 1394A Firewire Connector
P110 51 FCI71240-340CA Cardbus TopP110 51 FCI71240-340CA Cardbus Bottom
P113 27 System ACE Compact Flash
P116 46 Stereo Jack Headphone/Line OutP117 45 Stereo Jack Microphone InP118 45 Stereo Jack Line In
LED Index (DS*)
DS101 20 LED0603 Blue Done LED
DS427 35 Round LED Blue IlluminationDS428 35 Round LED Blue IlluminationDS429 35 Round LED Blue Illumination
DS203 27 LED0603 Red INIT LED
DS201 27 LED0603 Red System ACE ErrorDS202 27 LED0603 Green System ACE Status
DS103 35 Dual LED PLB Bus ErrorDS102 35 Dual LED OPB Bus Error
RefDes Page Description
J1 16 SMA User Clock P-side
RefDes Page Description
Table 2: ML300 CPU
Part Index
U16 28 CDCV857 DDR Clock Replicator
J102 55 HDR 2x32 Digital Connector #2
DS420 39 LED0603 Green Par Port Data2
X102 13 Half Size Osc System Clock 100MHz
X401 42 MA506 Ethenet Clock 25MHzX501 45 MA506 Audio Clock 24.576MHz
DS430 35 Round LED Blue Illumination
U6 30 HYB25D256800AT-7 DDR ChipU7 30 HYB25D256800AT-7 DDR ChipU8 30 HYB25D256800AT-7 DDR ChipU9 30 HYB25D256800AT-7 DDR Chip
U3 24 LT1963ES8 MGT VTT Linear Regulator
U21 39 SN74LVC161284DGGR Par Port XCVRU22 39 SN74CBT16210DGGR Par Port LED Buf
U59 54 TSB41AB1 IEE1394 (Firewire) Phy
U255 40 MAX6683 IIC Power MonitorU256 40 MAX6652 IIC Power Monitor
U1001 33 ML6554 DDR Switching Regulator
Port Index (P*)
P103 42 RJ45 Ethernet Port w/LEDs
P104 37 Shielded Minidin-6 PS/2 Port
P106 36 DB9 Serial PortP105 37 Shielded Minidin-6 PS/2 Port
P119 21 Serial ATA Connector (Host)P120 21 Serial ATA Connector (Device)
P114 26 HDR 2x8 CPU Debug ConnectorP115 26 HDR 2mm 2x7 JTAG Connector
P111 21 HSSCD2 (Infiniband) MGT ConnectorP112 21 HSSCD2 (Infiniband) MGT Connector
P109 26 Trace/Debug Connector (Mictor-38)
X101 12 EG2121/LV1145B Gig-E Clock 125MHz
X104 13 Half Size Osc SysACE Clock 33MHz
X601 54 MA506 Firewire Clock 24.576 MHz
X103 17 EG2121/LV1145B S-ATA/HSSCD2 Clock. 156.25MHz
IC Index (U*) Header Index (J*)
Diodes/Transistors (D*/Q*)
D604 47 Clamp Diode VCC Diode
U913 48 QS32X2245 PMC Clamp Diode
U802 48 QS32X2245 PMC Clamp Diode
D801 48 Clamp Diode VCC DiodeD901 48 Clamp Diode VCC DiodeD902 48 Clamp Diode VCC DiodeD903 48 Clamp Diode VCC Diode
D601 47 Clamp Diode VCC Diode
Q101 20 Re-drive FPGA Done for LED
D605 54 Fire Wire VCC Diode
D603 47 Clamp Diode VCC DiodeD602 47 Clamp Diode VCC Diode
Q103 13 System ACE Clock OE FET
Q403 37 Dual FET for PS/2 TransceiversQ404 37 Dual FET for PS/2 Transceivers
Q401 35 Re-drive Illum Signals for LEDsQ402 35 Re-drive Illum Signals for LEDs
Q405 35 Re-drive Illum Signals for LEDs
5 56
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Date:
Title:
Ver:A
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C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
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|================================================================================================|| QTY | REFDES | FREQUENCY | MANUFACTURE PN | MANUFACT | DESCRIPTION |
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| QTY| REFDES | PKG | MANUFACTURE PN | MANUFACTURE | DESCRIPTION |
BP
Bill of MaterialsPage 1 of 4
| 1 | U253 | SOIC8 | 24LC32A/SN | Microchip | IC, Memory, IIC EPROM, 32K |
| 1 | U254 | SOIC8 | 25LC160/SN | Microchip | IC, Memory, SPI EPROM, 16K |
| 1 | U255 | 10_UMAX | MAX6683AUB | Maxim | IC, Logic, System Monitor, 1.8V, 2.5V, 5V |
| 1 | U256 | 10_UMAX | MAX6652AUB | Maxim | IC, Logic, System Monitor, 12V, 2.5V, 3.3V |
| 2 | U270,U271 | TSSOP24 | MAX3388ECUG | Maxim | IC, Analog, RS-232 Level Translator |
| 1 | U500 | LQFP48 | AD1885JST | Analog | IC, Logic, AC97 Audio Codec, SMD |
| 1 | U501 | TSSOP28 | LM4835MTE | National | IC, Analog, Audio Amplified, 1W |
| 1 | U502 | TSSOP14 | DS1845E-010/T&R | Dallas Semi | IC, Analog, Potentiometer, IIC controlled, dual |
| 1 | U601 | S-PBGA-N256 | PCI4451GFN | TI | IC, Logic, PCI to PCMCIA / CardBus Bridge |
| 1 | P102 | | R14K-ST11 | Stratos Lightwave | IC, Optical Transceiver, Gigabit Etherent, 4X |
| 1 | U252 | SOP8 | LM76CNM-3 | National | IC, Linear, IIC Temperature Sensor |
| 1 | U251 | QSOP16 | MAX1617AMEE | Maxim | IC, Linear, IIC Remote Diode Temperature Sensor |
| 1 | U101 | 5-DD | LT1963EQ-25 | Linear Tech | IC, Linear, Voltage Reg, 1.5A, 2.5V, LDO |
| 1 | U60 | TSSOP16 | SN74LVC157APWR | TI | IC QUAD, 2-1 DATA SEL/MUX |
| 1 | U59 | S-PQFP-G48 | TSB41AB1PHP | TI | IC, Logic, IEEE-1394a PHY |
| 1 | U58 | DAP32 | TPS2216ADAP | TI | IC, Analog, Power Switch for PCMCIA |
| 1 | U53 | TSSOP56 | QS316211PA | IDT | IC, Logic, Quickswitch, 24 bit |
| 7 | U50,U51,U52,U802,U912,U913,U914 | QVSOP40 | QS32X2245Q2 | IDT | IC, Logic, Quickswitch, 16 bit |
| 2 | U27,U28 | TSSOP48 | SN74ALVC164245DGGR | TI | IC, Logic, Transceiver, 16 bit |
| 1 | U26 | LQFP64 | DJLXT971ALCA4834105 | Intel | IC, Logic, Ethernet PHY |
| 1 | U22 | TSSOP48 | SN74CBTD16210DGGR | TI | IC, Logic, Bus Switch, 20 bit, Level Translator |
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| 1 | U21 | TSSOP48 | SN74LVC161284DGGR | TI | IC, Logic, IEEE-1284 Driver & Level Translator |
| 1 | U20 | MILLIPAQ80 | QS34XV245Q3 | IDT | IC, Logic, Quickswitch, 32 bit |
| 1 | U19 | SOIC14 | DM74AS1034AM | National | IC, Logic, Hex Driver |
| 1 | U16 | TSSOP48 | CDCV857DGGR | TI | IC, Analog, Phase Lock Loop |
| 2 | U14,U15 | TVSOP48 | SN74SSTV16857DGVR | TI | IC, Logic, 14 bit register, SSTL2, Dual Phase Clock |
| 4 | U6,U7,U8,U9 | TSOP_66 | HYB25D256800AT-7 | Infineon | IC, Memory, DDR SDRAM, 256Mbit |
| 1 | U2 | TQFP144 | XCCACE-TQ144I | Xilinx | IC, Logic, SystemACE |
| 1 | U3 | LINEAR_SO8 | LT1963ES8 | Linear Tech | IC, Linear, Voltage Reg, 1.5A, Adjustable, LDO |
| 1 | U4 | LINEAR_SO8 | LT1763CS8 | Linear Tech | IC, Linear, Voltage Reg, 500mA, Adjustable, LDO |
| 11 | DS407,DS408,DS409,DS410,DS411,DS413,DS414,DS415,DS416,DS417,DS418 | 0603 | SML-LX0603YW-TR | Lumex | LED, Yellow, SMD |
| 5 | Q101,Q103,Q401,Q402,Q405 | SOT23 | BSS138 | Fairchild | Diode, SMD |
| 2 | Q403,Q404 | SOT363 | MMDT3904-7 | Diodes Inc | Transistor, Dual NPN |
| 1 | U1 | FF672 | XC2VP7-6FF672C | Xilinx | IC, FPGA, XC2VP7-6FF672C |
| 10 | DS202,DS412,DS419,DS420,DS421,DS422,DS423,DS424,DS425,DS426 | 0603 | SML-LX0603GW-TR | Lumex | LED, Green, SMD |
| 2 | DS201,DS203 | 0603 | SML-LX0603IW-TR | Lumex | LED, Red, SMD |
| 2 | DS102,DS103 | LED_DUAL | LNJ115W8PRA | Panasonic | LED, Dual Red/Green, SMD |
| 11 | DS101,DS401,DS402,DS403,DS404,DS405,DS406,DS427,DS428,DS429,DS430 | 0603 | LTST-C190CBKT | Lite-On | LED, BLUE, SMD |
| 1 | D605 | MELF | 1N5819M-13 | Diodes Inc | Diode, SMD |
| 8 | D601,D602,D603,D604,D801,D901,D902,D903 | SOD-323 | 1N4148WS-7 | Diodes Inc | Diode, SMD |
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| SEMICONDUCTORS ||================================================================================================================================================================================|
| OSCILATORS / CRYSTALS |
| 1 | X104 | 33.000 MHz | EH1325HSTS-33.000M | Ecliptek | Oscillator, TH, Half Size |
| 1 | X401 | 25.000 MHZ | MA-506 25.000M-C0 | Epson | Crystal, 25.000 MHz, MA_506 |
| 2 | X501,X601 | 24.576 MHZ | MA-506 24.576M-C0 | Epson | Crystal, 24.576 MHz, MA_506 |
| 1 | X103 | 156.250 MHZ | LV11B004-156.25M | Pletronics | Oscillator, SMT |
| 1 | X102 | 100.000 MHZ | EH1325HSTS-100.000M | Ecliptek | Oscillator, TH, Half Size |
| 1 | X101 | 125.000 MHZ | LV11B003-125.0M | Pletronics | Oscillator, SMT |
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ML300 CPU - BOM
Page 1 of 4
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Title:
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1234
D
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A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
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| QTY | REFDES | VALUE | TOL | VOLT | KIND | PKG | MANUFACTURE PN | MANUFACTURE|
| 205 | C9,C11,C12,C13,C17,C20,C22,C23,C102,C105,C193,C194,C195,C196,C215,C216,C217,C218,C219, | | | | | | | || | C220,C221,C222,C223,C224,C225,C226,C227,C228,C229,C250,C252,C253,C254,C255,C280,C281,C301, | | | | | | | || | C302,C303,C304,C305,C306,C307,C308,C309,C310,C311,C312,C313,C314,C315,C325,C326,C327,C328, | | | | | | | || | C329,C330,C331,C332,C333,C334,C341,C342,C343,C344,C345,C347,C348,C349,C350,C351,C353,C354, | | | | | | | || | C355,C357,C358,C359,C360,C361,C362,C363,C364,C365,C511,C513,C520,C521,C523,C524,C529,C530, | | | | | | | || | C531,C535,C536,C541,C676,C677,C679,C680,C681,C690,C693,C697,C698,C701,C702,C703,C704,C705, | | | | | | | || | C706,C707,C708,C709,C710,C711,C712,C713,C714,C715,C716,C717,C718,C719,C720,C721,C722,C723, | | | | | | | || | C724,C725,C726,C727,C728,C729,C730,C731,C732,C733,C734,C735,C736,C737,C738,C739,C740,C741, | | | | | | | || | C742,C743,C744,C745,C746,C747,C748,C749,C750,C751,C752,C753,C754,C755,C756,C757,C758,C759, | | | | | | | || | C760,C761,C762,C763,C764,C765,C766,C767,C768,C769,C770,C771,C772,C773,C774,C801,C802,C803, | | | | | | | || | C804,C805,C806,C807,C808,C809,C1004,C1005,C1011,C1013,C1014,C1015,C1016,C1017,C1018,C1019, | | | | | | | || | C1020,C1021,C1022,C1023,C1024,C1025,C1026,C1027 | 0.1UF | +80/-20 | 16V | CERAMIC | 0402 | ECJ-0EF1C104Z | Panasonic |
Bill of Materials
BP
Page 2 of 4
| 1 | C366 | 10PF | 5% | 50V | CERAMIC | 0402 | ECJ-0EC1H100D | Panasonic |
| 2 | C683,C684 | 12PF | 5% | 50V | CERAMIC | 0402 | ECJ-0EC1H120J | Panasonic |
| 2 | C7,C8 | 18PF | 5% | 50V | CERAMIC | 0402 | ECJ-0EC1H180J | Panasonic |
| 2 | C509,C510 | 22PF | 5% | 50V | CERAMIC | 0402 | ECJ-0EC1H220J | Panasonic |
| 2 | C1006,C1007 | 30PF | 5% | 50V | CERAMIC | 0402 | ECU-E1H300JCQ | Panasonic |
| 1 | C685 | 220PF | 5% | 50V | CERAMIC | 0402 | ECJ-0EC1H221J | Panasonic |
| 4 | C4,C6,C514,C515 | 270PF | 5% | 50V | CERAMIC | 0603 | ECJ-1VC1H271J | Panasonic |
| 2 | C507,C508 | 470PF | 10% | 25V | CERAMIC | 0402 | ECJ-0EB1E471K | Panasonic |
| 11 | C14,C15,C24,C25,C101,C104,C687,C692,C694,C695,C1010 | 1000PF | 10% | 50V | CERAMIC | 0402 | ECJ-0EB1H102K | Panasonic |
| 3 | C1,C2,C3 | 1000PF | 10% | 2000V | CERAMIC | 1812 | 1808B102K202NT | Novacap |
| 1 | C251 | 2200PF | 10% | 25V | CERAMIC | 0402 | C0402C222K3RACTU | Kemet |
| 1 | C518 | 47000PF | 10% | 10V | CERAMIC | 0402 | ECJ-0EB1A473K | Panasonic |
| 2 | C539,C540 | 68000PF | 10% | 10V | CERAMIC | 0402 | ECJ-0EB1A683K | Panasonic |
| 31 | C5,C26,C112,C113,C114,C115,C116,C117,C118,C119,C156,C157,C158,C159,C160,C161,C164,C165, | | | | | | | || | C166,C167,C168,C169,C172,C173,C176,C177,C686,C688,C689,C691,C696 | 0.01UF | 10% | 16V | CERAMIC | 0402 | C0402C103K4RACTU | Kemet |
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 12 | C270,C271,C272,C273,C274,C275,C276,C277,C278,C279,C678,C682 | 0.22UF | 10% | 10V | CERAMIC | 0603 | ECJ-1VB1A224K | Panasonic |
| | C142,C143,C144,C145,C146,C147,C148,C149,C150,C151,C152,C153,C154,C155 | | | | | | | || 32 | C120,C121,C122,C123,C124,C125,C126,C127,C128,C129,C130,C131,C132,C133,C134,C135,C140,C141, | 0.22UF | 10% | 25V | CERAMIC | 0805 | ECJ-2YB1E224K | Panasonic |
| 2 | C532,C533 | 0.33UF | 10% | 35V | TANT | A | T491A334K035AS | Kemet |
| 2 | C10,C19 | 1UF | +80/-20 | 10V | CERAMIC | 0603 | ECJ-1VF1A105Z | Panasonic |
| 7 | C516,C517,C525,C526,C527,C534,C538 | 1UF | 10% | 20V | TANT | A | T491A105K020AS | Kemet |
| 12 | C775,C776,C777,C778,C779,C780,C781,C783,C784,C785,C786,C1012 | 4.7UF | 10% | 16V | TANT | A | T491A475K016AS | Kemet |
| 8 | C180,C181,C182,C183,C184,C185,C186,C187 | 22UF | 12% | 6.3V | CERAMIC | 1206 | C1206C226Z9VACTU | Kemet |
| 2 | C103,C106 | 10UF | +80/-20 | 6.3V | CERAMIC | 0805 | ECJ-2FF0J106Z | Panasonic |
| 23 | C16,C18,C21,C189,C230,C231,C317,C318,C319,C320,C321,C322,C323,C324,C335,C336,C337,C338, | 10UF | 20% | 10V | TANT | A | ECS-T1AY106R | Panasonic || | C339,C340,C346,C352,C1028 | | | | | | | |
| 5 | C512,C519,C522,C528,C537 | 10UF | 20% | 16V | TANT | B | ECS-T1CX106R | Panasonic |
| 3 | C674,C796,C797 | 10UF | 20% | 20V | TANT | C | ECS-T1DC106R | Panasonic |
| 1 | C356 | 22UF | 20% | 6.3V | TANT | A | ECS-T0JY226R | Panasonic |
| 6 | C188,C192,C197,C673,C675,C795 | 33UF | 20% | 10V | TANT | B | ECS-T1AX336R | Panasonic |
| 1 | C191 | 100UF | 20% | 10V | TANT | D | ECS-T1AD107R | Panasonic |
| 5 | C1001,C1002,C1003,C1008,C1009 | 220UF | 20% | 6.3V | TANT | D | EEJ-L0JD227R | Panasonic |
| 2 | C542,C543 | 220UF | 10% | 10V | TANT | X | T491X227K010AS | Kemet |
| 5 | C501,C502,C503,C504,C506 | 0.33UF | 10% | 16V | CERAMIC | 0805 | ECJ-2YB1C334K | Panasonic |
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 8 | C787,C788,C789,C790,C791,C792,C793,C794 | 47UF | 20% | 6.3V | TANT | B | ECS-T0JX476R | Panasonic ||--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|================================================================================================================================================================================|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
ML300 CPU - BOM
Page 2 of 4
|================================================================================================================================================================================|| CAPACITORS |
|================================================================================================================================================================================|
7 55
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
|================================================================================================================================================================================|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| QTY| REFDES | VALUE | TOL| WATT | PKG | MANUFACTURE PN | MANUFACTURE |
Bill of Materials
BP
Page 3 of 4
| 5 | RP601,RP602,RP604,RP605,RP606 | 4.7K | 5% | 1/16W | 8PIN | EXB-E10C472J | Panasonic |
| 2 | RP401,RP402 | 4.7K | 5% | 1/16W | 8PIN | 742C083472JTR | CTS |
| 17 | RP329,RP330,RP331,RP336,RP338,RP339,RP340,RP341,RP344,RP345,RP346,RP349,RP352,RP355,RP358,RP365,RP603 | 47R | 5% | 1/16W | 8PIN | EXB-E10C470J | Panasonic |
| | RP914 | 22R | 5% | 1/16W | 8PIN | 742C083220JTR | CTS || | RP327,RP328,RP332,RP347,RP348,RP350,RP351,RP353,RP354,RP356,RP357,RP359,RP360,RP361,RP362,RP363,RP910, | | | | | | || 35 | RP302,RP303,RP304,RP308,RP311,RP315,RP316,RP317,RP318,RP319,RP320,RP321,RP322,RP323,RP324,RP325,RP326, | | | | | | |
| 15 | R134,R135,R136,R137,R138,R139,R140,R141,R168,R226,R227,R451,R623,R627,R640 | 0R | 5% | 1/16W | 0402 | ERJ-2GE0R00X | Panasonic |
| 2 | R533,R534 | 0R | 5% | 1/10W | 0805 | ERJ-6GEY0R00V | Panasonic |
| 11 | R449,R452,R453,R454,R455,R456,R457,R458,R459,R460,R461 | 20.0R | 1% | 1/16W | 0402 | ERJ-2RKF20R0X | Panasonic |
| 7 | R301,R306,R311,R312,R313,R314,R319 | 22.1R | 1% | 1/16W | 0402 | ERJ-2RKF22R1X | Panasonic |
| 8 | R108,R172,R173,R219,R307,R308,R438,R1007 | 25.5R | 1% | 1/16W | 0402 | ERJ-2RKF25R5X | Panasonic |
| 1 | R181 | 26.1R | 1% | 1/8W | 0805 | 9C08052A26R1FKHFT | Yageo America |
| 1 | R182 | 38.3R | 1% | 1/8W | 0805 | 9C08052A38R3FKHFT | Yageo America |
| 16 | R302,R303,R304,R305,R309,R310,R315,R316,R317,R318,R440,R442,R445,R446,R447,R448 | 49.9R | 1% | 1/16W | 0402 | ERJ-2RKF49R9X | Panasonic |
| 5 | R184,R186,R220,R625,R626 | 51.1R | 1% | 1/16W | 0402 | ERJ-2RKF51R1X | Panasonic |
| 7 | R183,R185,R268,R630,R631,R635,R636 | 56.2R | 1% | 1/16W | 0402 | ERJ-2RKF56R2X | Panasonic |
| 11 | R127,R401,R402,R403,R404,R405,R406,R466,R467,R468,R469 | 64.9R | 1% | 1/16W | 0402 | ERJ-2RKF64R9X | Panasonic |
| 16 | R107,R119,R120,R121,R122,R123,R124,R169,R174,R175,R176,R179,R265,R266,R1003,R1004 | 100R | 1% | 1/16W | 0402 | ERJ-2RKF1000X | Panasonic |
| | R436,R437 | 130R | 1% | 1/16W | 0402 | ERJ-2RKF1300X | Panasonic || 23 | R105,R106,R113,R114,R419,R420,R421,R422,R423,R424,R425,R426,R427,R428,R429,R430,R431,R432,R433,R434,R435, | | | | | | |
| 8 | R146,R147,R148,R149,R150,R151,R152,R153 | 180R | 1% | 1/16W | 0402 | 9C04021A1800FLHF3 | Yageo America |
| 3 | R253,R441,R443 | 200R | 1% | 1/16W | 0402 | ERJ-2RKF2000X | Panasonic |
| 1 | R171 | 330R | 1% | 1/16W | 0402 | 9C04021A3300FLHF3 | Yageo America |
| 1 | R166 | 487R | 1% | 1/16W | 0402 | ERJ-2RKF4870X | Panasonic |
| 15 | R167,R213,R214,R215,R216,R269,R535,R536,R629,R638,R639,R643,R644,R645,R1001 | 1.00K | 1% | 1/16W | 0402 | ERJ-2RKF1001X | Panasonic |
| 4 | R412,R413,R416,R417 | 1.80K | 1% | 1/16W | 0402 | 9C04021A1801FLHF3 | Yageo America |
| 1 | R510 | 2.00K | 1% | 1/16W | 0402 | ERJ-2RKF2001X | Panasonic |
| 1 | R637 | 6.34K | 1% | 1/16W | 0402 | ERJ-2RKF6341X | Panasonic |
| 1 | R501 | 6.80K | 1% | 1/16W | 0402 | 9C04021A6801FLHF3 | Phycomp |
| | R833,R945,R946,R947 | 10.0K | 1% | 1/16W | 0402 | ERJ-2RKF1002X | Panasonic || 25 | R170,R222,R223,R224,R225,R250,R251,R252,R254,R255,R407,R408,R415,R418,R513,R619,R620,R621,R622,R641,R642, | | | | | | |
| 10 | R518,R519,R520,R521,R523,R524,R525,R526,R527,R528 | 20.0K | 1% | 1/16W | 0402 | ERJ-2RKF2002X | Panasonic |
| 1 | R450 | 22.1K | 1% | 1/16W | 0402 | ERJ-2RKF2212X | Panasonic |
| 1 | R676 | 43.0K | 1% | 1/16W | 0402 | 9C04021A4302FLHF3 | Yageo America |
| 3 | R514,R515,R516 | 47.0K | 1% | 1/16W | 0402 | 9C04021A4702FLHF3 | Yageo America |
| 4 | R538,R539,R1002,R1005 | 100K | 1% | 1/16W | 0402 | ERJ-2RKF1003X | Panasonic |
| 1 | R634 | 402K | 1% | 1/16W | 0402 | ERJ-2RKF4023X | Panasonic |
| 2 | R512,R633 | 1M | 5% | 1/16W | 0402 | ERJ-2GEJ105X | Panasonic |
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | R439,R444,R462,R463,R464,R465,R491,R495,R496,R498,R499,R503,R504,R505,R506,R507,R508,R509,R624,R628,R647, | | | | | | |
| 1 | R632 | 5.10K | 1% | 1/16W | 0402 | 9C04021A5101FLHF3 | Yageo America |
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|================================================================================================================================================================================|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
ML300 CPU - BOM
Page 3 of 4
|================================================================================================================================================================================|
|================================================================================================================================================================================|| RESISTORS |
| | R659,R675,R702,R1006 | 4.7K | 5% | 1/16W | 0402 | ERJ-2GEJ472X | Panasonic |
| 46 | R125,R129,R133,R180,R208,R209,R210,R211,R212,R217,R218,R221,R260,R261,R262,R263,R264,R409,R410,R411,R414, | | | | | | |
568
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
|=========================================================================| |===================================================================================================|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
|========================================================================================================================|
|================================================================================================================================================================================|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|================================================================================================================================================================================|| QTY| REFDES | VALUE | TOL | PKG | MANUFACTURE PN | MANUFACTURE | |
| 6 | Hardware, Screw, 4-40 x 3/8, Pan Head, SS | MS51957-15 | Olander | | 2 | R531,R532 | DNP | 805 |
| 2 | Hardware, Screw, 2-56 x 3/8, Pan Head, SS | 2C37PPMS | Olander | | 2 | J505,J506 | DNP | SIP2 || 12 | Hardware, Washer, Flat 4-40 SS | 620C4L | Olander | | 3 | E601,E603,E605 | DNP | BOWTIE_OPEN || 6 | Hardware, Washer, Lock, 4-40 SS | 4NSLWS | Olander | | 3 | E602,E604,E606 | DNP | BOWTIE_CLOSED || 6 | Hardware, Nut, 4-40, SS | 4CHNTS | Olander | | 6 | MH1,MH2,MH3,MH4,MH5,MH6 | DNP | JACK_109_280 || 6 | Hardware, Washer, Lock 2-56 SS | 2NSLWS | Olander | | 4 | MH7,MH8,MH9,MH10 | DNP | JACK_116_280 || 6 | Hardware, Washer, Flat 2-56 SS | 620C2 | Olander | | 34 | TP101,TP102,TP104,TP105,TP106,TP107,TP108,TP214,TP215,TP216,TP217, | | |
| QTY | REFDES | MANUFACTURE PN | MANUFACTURE | DESCRIPTION |
| 2 | P106,P107 | 747250-4 | AMP | Connector, DB9, Male |
Bill of Materials
BP
Page 4 of 4
| 1 | ML300_SERNUM_LABEL | | | | | Axiom | Label, Polyimide, ML300 Serial Number |
| 1 | ML300_MACID_LABEL | | | | | Axiom | Label, Polyimide, MAC BASE ADDR |
| 1 | PCB1b | | | | | Axiom | ML300_CPU Printed Circuit Board Assembly |
| 1 | T401 | | | SOIC16 | TG110-S050N2 | Halo | Transformer, Ethernet Pulse |
| 1 | L1001 | 3.3UH | | DO3316 | DO3316P-332 | Coilcraft | Inductor, SMD |
| 8 | FB301,FB302,FB402,FB404,FB602,FB604,FB606,FB607 | 60_OHM | | 1210 | CTCB1210-600S | CTParts | Ferrite Bead, SMD |
| 8 | FB141,FB403,FB405,FB406,FB501,FB502,FB603,FB605 | 125_OHM | | 1812 | CTCB1812-125S | CTParts | Ferrite Bead, SMD |
| 8 | FB133,FB134,FB135,FB136,FB137,FB138,FB139,FB140 | 47UH | 10% | 1210 | ELJ-PA470KF | Panasonic | Inductor, SMD |
| 33 | FB101,FB102,FB103,FB104,FB105,FB106,FB107,FB108,FB109,FB110, | | | | | | |
| 1 | F601 | 1.1A | | 2920 | SMD100-2 | RayChem | Fuse, 1.1A, SMD, Self Healing |
|================================================================================================================================================================================|
|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| | FB131,FB132,FB601 | 1000_OHM | | 0805 | BLM21AH102SN1D | Murata | Ferrite Bead, SMD || | FB121,FB122,FB123,FB124,FB125,FB126,FB127,FB128,FB129,FB130, | | | | | | || | FB111,FB112,FB113,FB114,FB115,FB116,FB117,FB118,FB119,FB120, | | | | | | |
|========================================================================================================================|
| 2 | P119,P120 | 67490-9221 | Molex | Connector, Serial ATA, SMD |
| 3 | P116,P117,P118 | 35RASMT4BHNTR | Switchcraft | Connector, Stereo Phone Jack |
| 1 | P115 | 87333-1420 | Molex | Header, 2X7, 2mm |
| 1 | P114 | PZC08DBAN | Sullins Electric | Header, 2x8, 100mil, right angle |
| 1 | P113a | 7E50-9316-04 | 3M | Ejector, Compact Flash |
| 1 | P113 | N7E50-7516HG-50 | 3M | Connector, Compact Flash, SMD |
| 2 | P111,P112 | 1364532-1 | AMP | Connector, HSSDC2, SMD |
| 2 | P110a, P110b | 73277-101000 | FCI | Connector, PCMCIA SMT Connector |
| 1 | P110 | 71240-340CA | FCI | Connector, Assembly, Dual PCMCIA with Left side eject |
| 1 | P109 | 67089-1 | AMP | Connector, Mictor, Edge Launch, 38 pin |
| 1 | P108 | 53462-0611 | Molex | Connector, IEEE-1394A |
| 2 | P104,P105 | MD-60SM | CUI Inc | Connector, MiniDIN6, Shielded, P/S2 |
| 1 | P103 | 569564-1 | AMP | Connector, RJ45, Thru-Hole |
| 1 | P101 | 745783-4 | AMP | Connector, DB25, Female |
| 1 | J204 | 22-12-2024 | Molex | Header, Right Angle, 2 pin |
| 3 | J104,J105,J106 | 71439-2164 | Molex | Connector, PCI Mezzanine, Main Board |
| 2 | X102a, X104a | 1108800 | Aries | Socket, 8 pin DIP ||========================================================================================================================|
| 1 | J103 | EW-25-11-G-D-400 | Samtec | Connector, Through Hole, Male |
| 2 | J101,J102 | EW-32-11-G-D-400 | Samtec | Connector, Through Hole, Male |
| 2 | J1,J2 | 901-144-8RFX | Amphenol-RF Division | Connector, SMA, Straight |
|========================================================================================================================|
|------------------------------------------------------------------------------------------------------------------------|| 3 | TP1,TP2,TP3 | 10-109-3-1 | Concord Electronics | Testpoint, Turret ||------------------------------------------------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------|
ML300 CPU - BOM
Page 4 of 4
| CONNECTORS |
|================================================================================================================================================================================|
| 1 | PCB1 | | | | | Ambitech | ML300_CPU Printed Circuit Board |
| OTHER |
| 6 | Hardware, Nut, 2-56, SS, Small | 2CSHNS | Olander | | | TP218,TP219,TP220,TP221,TP254,TP255,TP256,TP301,TP302,TP415,TP416, | | |
| QTY| DESCRIPTION | MANU PN | MANU | | QTY| REFDES | STATE | PKG |
|=========================================================================| |===================================================================================================|| HARDWARE | | DO NOT POPULATE PARTS ||=========================================================================| |===================================================================================================|
|=========================================================================| | | TP419,TP421,TP423,TP424,TP425,TP426,TP427,TP501,TP607,TP650,TP1001 | DNP | TESTPOINT ||===================================================================================================|
| 4 | Hardware, Screw, 2-56 x 3/4, Pan Head, SS | 2C75PPMS | Olander | | 8 | R130,R256,R257,R258,R259,R267,R502,R649 | DNP | 402 |
569
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
NET_CLASS IIC_FPGA{NET IIC_FPGA_SCLNET IIC_FPGA_SDA}NET_CLASS IIC_PMC{NET IIC_PMC_SCLNET IIC_PMC_SDA}
NET FPGA_PMC_CONN4_IO35NET FPGA_PMC_CONN4_IO37NET FPGA_PMC_CONN4_IO24NET FPGA_PMC_CONN4_IO26NET FPGA_PMC_CONN4_IO28NET FPGA_PMC_CONN4_IO30NET FPGA_PMC_CONN4_IO23NET FPGA_PMC_CONN4_IO25NET FPGA_PMC_CONN4_IO27NET FPGA_PMC_CONN4_IO29NET FPGA_PMC_CONN4_IO16NET FPGA_PMC_CONN4_IO18NET FPGA_PMC_CONN4_IO20NET FPGA_PMC_CONN4_IO22NET FPGA_PMC_CONN4_IO15NET FPGA_PMC_CONN4_IO17NET FPGA_PMC_CONN4_IO19NET FPGA_PMC_CONN4_IO21NET FPGA_PMC_CONN4_IO10NET FPGA_PMC_CONN4_IO12NET FPGA_PMC_CONN4_IO14{NET_CLASS PMC_FPGA_CONN4
NET FPGA_PMC_CONN4_IO31NET FPGA_PMC_CONN4_IO38NET FPGA_PMC_CONN4_IO36NET FPGA_PMC_CONN4_IO34NET FPGA_PMC_CONN4_IO32NET FPGA_PMC_CONN4_IO45NET FPGA_PMC_CONN4_IO43NET FPGA_PMC_CONN4_IO41NET FPGA_PMC_CONN4_IO39NET FPGA_PMC_CONN4_IO46NET FPGA_PMC_CONN4_IO44NET FPGA_PMC_CONN4_IO42NET FPGA_PMC_CONN4_IO40NET FPGA_PMC_CONN4_IO53NET FPGA_PMC_CONN4_IO51NET FPGA_PMC_CONN4_IO49NET FPGA_PMC_CONN4_IO47NET FPGA_PMC_CONN4_IO54NET FPGA_PMC_CONN4_IO52NET FPGA_PMC_CONN4_IO50NET FPGA_PMC_CONN4_IO48NET FPGA_PMC_CONN4_IO61NET FPGA_PMC_CONN4_IO59NET FPGA_PMC_CONN4_IO57NET FPGA_PMC_CONN4_IO55NET FPGA_PMC_CONN4_IO62NET FPGA_PMC_CONN4_IO60NET FPGA_PMC_CONN4_IO58NET FPGA_PMC_CONN4_IO56NET FPGA_PMC_CONN4_IO13NET FPGA_PMC_CONN4_IO11NET FPGA_PMC_CONN4_IO9}
NET FPGA_PMC_CONN4_IO33
NET_CLASS DDR_ADDR_RES{NET DDR_RES_A06NET DDR_RES_A05NET DDR_RES_A04NET DDR_RES_A03NET DDR_RES_A02NET DDR_RES_A01NET DDR_RES_A00NET DDR_RES_A12NET DDR_RES_A11NET DDR_RES_A10NET DDR_RES_A09NET DDR_RES_A08NET DDR_RES_A07}NET_CLASS DDR_CLK_RES{NET DDR_RES_CK_NNET DDR_RES_CK}NET_CLASS DDR_DATA_RES{NET DDR_RES_DQ03NET DDR_RES_DQ02NET DDR_RES_DQ01NET DDR_RES_DQ00NET DDR_RES_DQ07NET DDR_RES_DQ06NET DDR_RES_DQ05NET DDR_RES_DQ04NET DDR_RES_DQ11NET DDR_RES_DQ10NET DDR_RES_DQ09NET DDR_RES_DQ08NET DDR_RES_DQ15NET DDR_RES_DQ14NET DDR_RES_DQ13NET DDR_RES_DQ12NET DDR_RES_DQ19NET DDR_RES_DQ18NET DDR_RES_DQ17NET DDR_RES_DQ16NET DDR_RES_DQ23NET DDR_RES_DQ22NET DDR_RES_DQ21NET DDR_RES_DQ20NET DDR_RES_DQ27NET DDR_RES_DQ26NET DDR_RES_DQ25NET DDR_RES_DQ24NET DDR_RES_DQ31NET DDR_RES_DQ30NET DDR_RES_DQ29NET DDR_RES_DQ28}
NET_CLASS DDR_DQS_RES{NET DDR_RES_DQS3NET DDR_RES_DQS2NET DDR_RES_DQS1NET DDR_RES_DQS0}NET_CLASS DDR_CNTL_RES{NET DDR_RES_CKENET DDR_RES_RAS_NNET DDR_RES_CAS_NNET DDR_RES_BA1NET DDR_RES_BA0NET DDR_RES_CS_NNET DDR_RES_WE_N}
NET_CLASS DATA{NET_CLASS AUDIO_DIG_FPGA{NET AUDIO_BIT_FPGA_CLKNET AUDIO_FPGA_SYNCHNET AUDIO_FPGA_CS0NET AUDIO_FPGA_SDATA_OUTNET AUDIO_FPGA_SDATA_INNET AUDIO_FPGA_RESET_N}NET_CLASS AUDIO_DIG_PMC{NET AUDIO_PMC_BIT_CLKNET AUDIO_PMC_SYNCHNET AUDIO_PMC_CS0NET AUDIO_PMC_SDATA_OUTNET AUDIO_PMC_SDATA_INNET AUDIO_PMC_RESET_N}NET_CLASS AUDIO_DIG_COMP{NET AUDIO_BIT_CLKNET AUDIO_SYNCHNET AUDIO_SDATA_OUTNET AUDIO_SDATA_INNET AUDIO_RESET_N}NET_CLASS CARDBUSA{NET CARDBUSA_CAD3NET CARDBUSA_CAD2NET CARDBUSA_CAD1NET CARDBUSA_CAD0NET CARDBUSA_CAD15NET CARDBUSA_CAD14NET CARDBUSA_CAD13NET CARDBUSA_CAD12NET CARDBUSA_CAD19NET CARDBUSA_CAD18NET CARDBUSA_CAD17NET CARDBUSA_CAD16NET CARDBUSA_CAD23NET CARDBUSA_CAD22NET CARDBUSA_CAD21NET CARDBUSA_CAD20NET CARDBUSA_CAD27NET CARDBUSA_CAD26NET CARDBUSA_CAD25NET CARDBUSA_CAD24NET CARDBUSA_CAD31NET CARDBUSA_CAD30NET CARDBUSA_CAD29NET CARDBUSA_CAD28NET CARDBUSA_CAD7NET CARDBUSA_CAD6NET CARDBUSA_CAD5NET CARDBUSA_CAD4NET CARDBUSA_CAD11NET CARDBUSA_CAD10NET CARDBUSA_CAD9NET CARDBUSA_CAD8NET CARDBUSA_CTRDYNET CARDBUSA_CDEVSELNET CARDBUSA_CSTOPNET CARDBUSA_CBLOCKNET CARDBUSA_CVS1NET CARDBUSA_CCBE3NET CARDBUSA_CCBE2NET CARDBUSA_CCBE1NET CARDBUSA_CCBE0NET CARDBUSA_CCLKRUNNET CARDBUSA_CIRDYNET CARDBUSA_CCLKNET CARDBUSA_CSERRNET CARDBUSA_CRSTNET CARDBUSA_CVS2NET CARDBUSA_CFRAMENET CARDBUSA_CINTNET CARDBUSA_CGNTNET CARDBUSA_CPERRNET CARDBUSA_CPARNET CARDBUSA_CCD2NET CARDBUSA_CCD1NET CARDBUSA_CSTSCHGNET CARDBUSA_CAUDIONET CARDBUSA_CREQNET CARDBUSA_RSV_A18NET CARDBUSA_RSV_D2NET CARDBUSA_RSV_D14}
NET_CLASS CARDBUSB{NET CARDBUSB_CAD3NET CARDBUSB_CAD2NET CARDBUSB_CAD1NET CARDBUSB_CAD0NET CARDBUSB_CAD15NET CARDBUSB_CAD14NET CARDBUSB_CAD13NET CARDBUSB_CAD12NET CARDBUSB_CAD19NET CARDBUSB_CAD18NET CARDBUSB_CAD17NET CARDBUSB_CAD16NET CARDBUSB_CAD23NET CARDBUSB_CAD22NET CARDBUSB_CAD21NET CARDBUSB_CAD20NET CARDBUSB_CAD27NET CARDBUSB_CAD26NET CARDBUSB_CAD25NET CARDBUSB_CAD24NET CARDBUSB_CAD31NET CARDBUSB_CAD30NET CARDBUSB_CAD29NET CARDBUSB_CAD28NET CARDBUSB_CAD7NET CARDBUSB_CAD6NET CARDBUSB_CAD5NET CARDBUSB_CAD4NET CARDBUSB_CAD11NET CARDBUSB_CAD10NET CARDBUSB_CAD9
NET CARDBUSB_CTRDYNET CARDBUSB_CDEVSELNET CARDBUSB_CSTOPNET CARDBUSB_CBLOCKNET CARDBUSB_CVS1NET CARDBUSB_CCBE3NET CARDBUSB_CCBE2NET CARDBUSB_CCBE1NET CARDBUSB_CCBE0NET CARDBUSB_CCLKRUNNET CARDBUSB_CIRDYNET CARDBUSB_CCLKNET CARDBUSB_CSERRNET CARDBUSB_CRSTNET CARDBUSB_CVS2NET CARDBUSB_CFRAMENET CARDBUSB_CINTNET CARDBUSB_CGNTNET CARDBUSB_CPERRNET CARDBUSB_CPARNET CARDBUSB_CCD2NET CARDBUSB_CCD1NET CARDBUSB_CSTSCHGNET CARDBUSB_CAUDIONET CARDBUSB_CREQNET CARDBUSB_RSV_A18NET CARDBUSB_RSV_D2NET CARDBUSB_RSV_D14}NET_CLASS CPU_DEBUG{NET CPU_HALT_NNET CPU_TDONET CPU_TCKNET CPU_TMSNET CPU_TDINET CPU_TRST}NET_CLASS DDR_ADDR_FPGA{NET DDR_FPGA_A06NET DDR_FPGA_A05NET DDR_FPGA_A04NET DDR_FPGA_A03NET DDR_FPGA_A02NET DDR_FPGA_A01NET DDR_FPGA_A00NET DDR_FPGA_A12NET DDR_FPGA_A11NET DDR_FPGA_A10NET DDR_FPGA_A09NET DDR_FPGA_A08NET DDR_FPGA_A07}
NET_CLASS DDR_CLK_FPGA{NET DDR_FPGA_CK_NNET DDR_FPGA_CK}NET_CLASS DDR_DM_FPGA{NET DDR_FPGA_DM3NET DDR_FPGA_DM2NET DDR_FPGA_DM1NET DDR_FPGA_DM0}NET_CLASS DDR_DATA_FPGA{NET DDR_FPGA_DQ03NET DDR_FPGA_DQ02NET DDR_FPGA_DQ01NET DDR_FPGA_DQ00NET DDR_FPGA_DQ07NET DDR_FPGA_DQ06NET DDR_FPGA_DQ05NET DDR_FPGA_DQ04NET DDR_FPGA_DQ11NET DDR_FPGA_DQ10NET DDR_FPGA_DQ09NET DDR_FPGA_DQ08NET DDR_FPGA_DQ15NET DDR_FPGA_DQ14NET DDR_FPGA_DQ13NET DDR_FPGA_DQ12NET DDR_FPGA_DQ19NET DDR_FPGA_DQ18NET DDR_FPGA_DQ17NET DDR_FPGA_DQ16NET DDR_FPGA_DQ23NET DDR_FPGA_DQ22NET DDR_FPGA_DQ21NET DDR_FPGA_DQ20NET DDR_FPGA_DQ27NET DDR_FPGA_DQ26NET DDR_FPGA_DQ25NET DDR_FPGA_DQ24NET DDR_FPGA_DQ31NET DDR_FPGA_DQ30NET DDR_FPGA_DQ29NET DDR_FPGA_DQ28}NET_CLASS DDR_DQS_FPGA{NET DDR_FPGA_DQS3NET DDR_FPGA_DQS2NET DDR_FPGA_DQS1NET DDR_FPGA_DQS0}
{NET DDR_FPGA_CKENET DDR_FPGA_RAS_NNET DDR_FPGA_CAS_NNET DDR_FPGA_BA1NET DDR_FPGA_BA0NET DDR_FPGA_CS_NNET DDR_FPGA_WE_N}NET_CLASS DDR_ADDR_MEM{NET DDR_MEM_A06NET DDR_MEM_A05NET DDR_MEM_A04NET DDR_MEM_A03NET DDR_MEM_A02NET DDR_MEM_A01NET DDR_MEM_A00NET DDR_MEM_A12NET DDR_MEM_A11NET DDR_MEM_A10NET DDR_MEM_A09NET DDR_MEM_A08NET DDR_MEM_A07}NET_CLASS DDR_DM_MEM{NET DDR_MEM_DM3NET DDR_MEM_DM2NET DDR_MEM_DM1NET DDR_MEM_DM0}
NET_CLASS DDR_DATA_MEM{NET DDR_MEM_DQ07NET DDR_MEM_DQ06NET DDR_MEM_DQ05NET DDR_MEM_DQ04NET DDR_MEM_DQ03NET DDR_MEM_DQ02NET DDR_MEM_DQ01NET DDR_MEM_DQ00NET DDR_MEM_DQ15NET DDR_MEM_DQ14NET DDR_MEM_DQ13NET DDR_MEM_DQ12NET DDR_MEM_DQ11NET DDR_MEM_DQ10NET DDR_MEM_DQ09NET DDR_MEM_DQ08NET DDR_MEM_DQ23NET DDR_MEM_DQ22NET DDR_MEM_DQ21NET DDR_MEM_DQ20NET DDR_MEM_DQ19NET DDR_MEM_DQ18NET DDR_MEM_DQ17NET DDR_MEM_DQ16NET DDR_MEM_DQ31NET DDR_MEM_DQ30NET DDR_MEM_DQ29NET DDR_MEM_DQ28NET DDR_MEM_DQ27NET DDR_MEM_DQ26NET DDR_MEM_DQ25NET DDR_MEM_DQ24}NET_CLASS DDR_DQS_MEM{NET DDR_MEM_DQS3NET DDR_MEM_DQS2NET DDR_MEM_DQS1NET DDR_MEM_DQS0}NET_CLASS DDR_CNTL_MEM{NET DDR_MEM_RAS_NNET DDR_MEM_CAS_NNET DDR_MEM_CKENET DDR_MEM_BA1NET DDR_MEM_BA0NET DDR_MEM_CS_NNET DDR_MEM_WE_N}NET_CLASS DDR_CLK_MEM{NET DDR_MEM_CK1_NNET DDR_MEM_CK1NET DDR_MEM_CK0_NNET DDR_MEM_CK0NET DDR_MEM_CK3_NNET DDR_MEM_CK3NET DDR_MEM_CK2_NNET DDR_MEM_CK2NET DDR_MEM_CK5_NNET DDR_MEM_CK5NET DDR_MEM_CK4_NNET DDR_MEM_CK4NET DDR_PLL_FB_IN_NNET DDR_PLL_FB_IN}NET_CLASS DDR_CLK_PLL{NET DDR_PLL_CK2_NNET DDR_PLL_CK2NET DDR_PLL_CK1_NNET DDR_PLL_CK1NET DDR_PLL_CK0_NNET DDR_PLL_CK0NET DDR_PLL_CK5_NNET DDR_PLL_CK5NET DDR_PLL_CK4_NNET DDR_PLL_CK4NET DDR_PLL_CK3_NNET DDR_PLL_CK3NET DDR_PLL_FB_OUT_NNET DDR_PLL_FB_OUT}
NET_CLASS DDR_ADDR_REG{NET DDR_REG_A06NET DDR_REG_A05NET DDR_REG_A04NET DDR_REG_A03NET DDR_REG_A02NET DDR_REG_A01NET DDR_REG_A00NET DDR_REG_A12NET DDR_REG_A11NET DDR_REG_A10NET DDR_REG_A09NET DDR_REG_A08NET DDR_REG_A07}NET_CLASS DDR_CNTL_REG{NET DDR_REG_CKENET DDR_REG_RAS_NNET DDR_REG_CAS_NNET DDR_REG_BA1NET DDR_REG_BA0NET DDR_REG_CS_NNET DDR_REG_WE_N}
BPPage 1 of 2
Net ClassesPage 1 of 2
NET_CLASS DDR_CNTL_FPGA
NET CARDBUSB_CAD8
ML300 CPU - Net Classes
5510
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
NET_CLASS PCI_FPGA_CONN{NET PCI_FPGA_AD06NET PCI_FPGA_AD04NET PCI_FPGA_AD03NET PCI_FPGA_AD01NET PCI_FPGA_AD07NET PCI_FPGA_CBE0NET PCI_FPGA_AD05NET PCI_FPGA_M66ENNET PCI_FPGA_AD11NET PCI_FPGA_AD12NET PCI_FPGA_AD08NET PCI_FPGA_AD13NET PCI_FPGA_AD14NET PCI_FPGA_AD15NET PCI_FPGA_AD10NET PCI_FPGA_AD19NET PCI_FPGA_CBE2NET PCI_FPGA_AD16NET PCI_FPGA_AD17NET PCI_FPGA_AD20NET PCI_FPGA_AD21NET PCI_FPGA_AD22NET PCI_FPGA_AD18NET PCI_FPGA_AD31NET PCI_FPGA_AD26NET PCI_FPGA_AD27NET PCI_FPGA_AD28NET PCI_FPGA_PMC_GNTNET PCI_FPGA_PMC_REQNET PCI_FPGA_AD29NET PCI_FPGA_AD30NET PCI_FPGA_PRS2NET PCI_FPGA_BM3NET PCI_FPGA_BUS_RSTNET PCI_FPGA_BM4NET PCI_FPGA_AD24NET PCI_FPGA_AD25NET PCI_FPGA_AD23NET PCI_FPGA_CBE3NET PCI_FPGA_INTCNET PCI_FPGA_INTBNET PCI_FPGA_PRS1NET PCI_FPGA_INTDNET PCI_FPGA_SB0NET PCI_FPGA_SDONENET PCI_FPGA_CBE1NET PCI_FPGA_PARNET PCI_FPGA_CB_GNTNET PCI_FPGA_CB_REQNET PCI_FPGA_GBL_RST
NET PCI_FPGA_PMC_TDINET PCI_FPGA_INTANET PCI_FPGA_PMC_TMSNET PCI_FPGA_AD02NET PCI_FPGA_ACK64NET PCI_FPGA_AD00NET PCI_FPGA_REQ64NET PCI_FPGA_DEVSELNET PCI_FPGA_PERRNET PCI_FPGA_LOCKNET PCI_FPGA_SERRNET PCI_FPGA_FRAMENET PCI_FPGA_TRDYNET PCI_FPGA_IRDYNET PCI_FPGA_STOP}NET_CLASS CLK_27MHZ_COMP{NET FPGA_PMC_CONN4_IO61NET PCI_PORT_CLK_PMCNET PCI_PORT_CLK_CB}NET_CLASS CLK_27MHZ_FPGA{NET PCI_PORT_CLK_PMCNET PCI_PORT_CLK_CB}
NET_CLASS PCI_PORT_CONN{NET PCI_PORT_AD06NET PCI_PORT_AD04NET PCI_PORT_AD03NET PCI_PORT_AD01NET PCI_PORT_AD07NET PCI_PORT_CBE0NET PCI_PORT_AD05NET PCI_PORT_M66ENNET PCI_PORT_AD11NET PCI_PORT_AD12NET PCI_PORT_AD08NET PCI_PORT_AD13NET PCI_PORT_AD14NET PCI_PORT_AD15NET PCI_PORT_AD10NET PCI_PORT_AD19NET PCI_PORT_CBE2NET PCI_PORT_AD16NET PCI_PORT_AD17NET PCI_PORT_AD20NET PCI_PORT_AD21NET PCI_PORT_AD22NET PCI_PORT_AD18NET PCI_PORT_AD31NET PCI_PORT_AD26NET PCI_PORT_AD27NET PCI_PORT_AD28NET PCI_PORT_PMC_GNTNET PCI_PORT_PMC_REQNET PCI_PORT_AD29NET PCI_PORT_AD30NET PCI_PORT_PRS2NET PCI_PORT_BM3NET PCI_PORT_BUS_RSTNET PCI_PORT_BM4NET PCI_PORT_AD24NET PCI_PORT_AD25NET PCI_PORT_AD23NET PCI_PORT_CBE3NET PCI_PORT_INTCNET PCI_PORT_INTBNET PCI_PORT_PRS1NET PCI_PORT_INTDNET PCI_PORT_SBONET PCI_PORT_SDONENET PCI_PORT_CBE1NET PCI_PORT_PARNET PCI_PORT_CB_GNTNET PCI_PORT_CB_REQNET PCI_PORT_GBL_RSTNET PCI_PORT_PMC_TRSTNET PCI_PORT_PMC_TCKNET PCI_PORT_PMC_TDONET PCI_PORT_PMC_TDINET PCI_PORT_INTANET PCI_PORT_PMC_TMSNET PCI_PORT_AD02NET PCI_PORT_ACK64NET PCI_PORT_AD00NET PCI_PORT_REQ64NET PCI_PORT_DEVSELNET PCI_PORT_PERRNET PCI_PORT_LOCKNET PCI_PORT_SERRNET PCI_PORT_FRAMENET PCI_PORT_TRDYNET PCI_PORT_IRDYNET PCI_PORT_STOP
NET_CLASS ENET_PHY_COMP{NET PHY_TX_ER_TMPNET PHY_TX_CLK_TMPNET PHY_COL_TMPNET PHY_CRS_TMPNET PHY_RXD3_TMPNET PHY_RXD2_TMPNET PHY_RXD1_TMPNET PHY_RXD0_TMPNET PHY_RX_DV_TMPNET PHY_RX_CLK_TMPNET PHY_RX_ER_TMP}
NET_CLASS ENET_PHY{NET PHY_RXD3NET PHY_RXD2NET PHY_RXD1NET PHY_RXD0NET PHY_RX_DVNET PHY_RX_CLKNET PHY_RX_ERNET PHY_SLEEPNET PHY_PAUSENET PHY_PWRDNNET PHY_MDIONET PHY_MDCNET PHY_COLNET PHY_CRSNET PHY_MDINTNET PHY_RESETNET PHY_SLW0NET PHY_SLW1NET PHY_TX_ERNET PHY_TX_CLKNET PHY_TX_ENNET PHY_TXD0NET PHY_TXD1NET PHY_TXD2NET PHY_TXD3}NET_CLASS PMC_PMC_CONN4{NET PMC_CONN4_IO21NET PMC_CONN4_IO19NET PMC_CONN4_IO17NET PMC_CONN4_IO15NET PMC_CONN4_IO22NET PMC_CONN4_IO20NET PMC_CONN4_IO18NET PMC_CONN4_IO16NET PMC_CONN4_IO29NET PMC_CONN4_IO27NET PMC_CONN4_IO25NET PMC_CONN4_IO23NET PMC_CONN4_IO30NET PMC_CONN4_IO28NET PMC_CONN4_IO26NET PMC_CONN4_IO24NET PMC_CONN4_IO37NET PMC_CONN4_IO35NET PMC_CONN4_IO33NET PMC_CONN4_IO31NET PMC_CONN4_IO38NET PMC_CONN4_IO36NET PMC_CONN4_IO34NET PMC_CONN4_IO32NET PMC_CONN4_IO45NET PMC_CONN4_IO43NET PMC_CONN4_IO41NET PMC_CONN4_IO39NET PMC_CONN4_IO46NET PMC_CONN4_IO44NET PMC_CONN4_IO42NET PMC_CONN4_IO40NET PMC_CONN4_IO53NET PMC_CONN4_IO51NET PMC_CONN4_IO49NET PMC_CONN4_IO47NET PMC_CONN4_IO54NET PMC_CONN4_IO52NET PMC_CONN4_IO50NET PMC_CONN4_IO48NET PMC_CONN4_IO61NET PMC_CONN4_IO59NET PMC_CONN4_IO57NET PMC_CONN4_IO55NET PMC_CONN4_IO62NET PMC_CONN4_IO60NET PMC_CONN4_IO58NET PMC_CONN4_IO56NET PMC_CONN4_IO14NET PMC_CONN4_IO12NET PMC_CONN4_IO10NET FPGA_PMC_CONN4_IO13NET PMC_CONN4_IO11NET PMC_CONN4_IO9
NET_CLASS PS2_1{NET PS2_1_DATA_OUTNET PS2_1_DATA_INNET PS2_1_CLK_OUTNET PS2_1_CLK_IN}NET_CLASS PS2_2{NET PS2_2_DATA_OUTNET PS2_2_DATA_INNET PS2_2_CLK_OUTNET PS2_2_CLK_IN}
{NET SYSACE_CFA05NET SYSACE_CFA04NET SYSACE_CFA03NET SYSACE_CFA02NET SYSACE_CFA01NET SYSACE_CFA00NET SYSACE_CFA10NET SYSACE_CFA09NET SYSACE_CFA08NET SYSACE_CFA07NET SYSACE_CFA06NET SYSACE_CFD04NET SYSACE_CFD03NET SYSACE_CFD02NET SYSACE_CFD01NET SYSACE_CFD00NET SYSACE_CFD09NET SYSACE_CFD08NET SYSACE_CFD07NET SYSACE_CFD06NET SYSACE_CFD05NET SYSACE_CFD15NET SYSACE_CFD14NET SYSACE_CFD13NET SYSACE_CFD12NET SYSACE_CFD11NET SYSACE_CFD10NET SYSACE_CFCD1NET SYSACE_CFCD2NET SYSACE_CFREGNET SYSACE_CFWAITNET SYSACE_CFRDBSYNET SYSACE_CFWENET SYSACE_CFDE}NET_CLASS SYSACE_MPU{NET SYSACE_MPA03NET SYSACE_MPA02NET SYSACE_MPA01NET SYSACE_MPA00NET SYSACE_MPA06NET SYSACE_MPA05NET SYSACE_MPA04NET SYSACE_MPD04NET SYSACE_MPD03NET SYSACE_MPD02NET SYSACE_MPD01NET SYSACE_MPD00NET SYSACE_MPD09NET SYSACE_MPD08NET SYSACE_MPD07NET SYSACE_MPD06NET SYSACE_MPD05NET SYSACE_MPD15NET SYSACE_MPD14NET SYSACE_MPD13NET SYSACE_MPD12NET SYSACE_MPD11NET SYSACE_MPD10NET SYSACE_MPBRDYNET SYSACE_MPIRQNET SYSACE_MPCENET SYSACE_MPWENET SYSACE_MPDE}
NET_CLASS SYSACE_JTAG_2V5{NET SYSACE_TSTTDONET SYSACE_TSTTMS_2V5NET SYSACE_TSTTCK_2V5NET SYSACE_TSTTDI_2V5}NET_CLASS SYSACE_JTAG_3V3{NET SYSACE_TSTTMS_3V3NET SYSACE_TSTTCK_3V3NET SYSACE_TSTTDI_3V3}NET_CLASS TFT_CNTL_FPGA{NET TFT_FPGA_DPSNET TFT_FPGA_DENET TFT_FPGA_VSYNCNET TFT_FPGA_HSYNCNET TFT_FPGA_CLK}NET_CLASS TFT_CLR_FPGA{NET TFT_FPGA_B5NET TFT_FPGA_B4NET TFT_FPGA_B3NET TFT_FPGA_B2NET TFT_FPGA_B1NET TFT_FPGA_B0NET TFT_FPGA_G5NET TFT_FPGA_G4NET TFT_FPGA_G3NET TFT_FPGA_G2NET TFT_FPGA_G1NET TFT_FPGA_G0NET TFT_FPGA_R5NET TFT_FPGA_R4NET TFT_FPGA_R3NET TFT_FPGA_R2NET TFT_FPGA_R1NET TFT_FPGA_R0}NET_CLASS TFT_CNTL_LCD{NET TFT_LCD_DPSNET TFT_LCD_DENET TFT_LCD_VSYNCNET TFT_LCD_HSYNCNET TFT_LCD_CLK}NET_CLASS TFT_CLR_LCD{NET TFT_LCD_B5NET TFT_LCD_B4NET TFT_LCD_B3NET TFT_LCD_B2NET TFT_LCD_B1NET TFT_LCD_B0NET TFT_LCD_G5NET TFT_LCD_G4NET TFT_LCD_G3NET TFT_LCD_G2NET TFT_LCD_G1NET TFT_LCD_G0NET TFT_LCD_R5NET TFT_LCD_R4NET TFT_LCD_R3NET TFT_LCD_R2NET TFT_LCD_R1NET TFT_LCD_R0}NET_CLASS CPU_TRACE{NET TS6NET TS5NET TS4NET TS3NET TS2ENET TS1ENET TS2ONET TS1ONET TRC_CLK}
BPPage 2 of 2
Page 2 of 2Net Classes
NET PCI_FPGA_PMC_TRSTNET PCI_FPGA_PMC_TCKNET PCI_FPGA_PMC_TDO
}
}
NET_CLASS SYSACE_FLASH
ML300 CPU - Net Classes
11 55
0402
VCC2V5
VCC2V5
0402
0805 0402 0402
0402
PKG_TYPE=FF672PARTS=1LEVEL=STD
B24_PAD001_IO_L01N_0_VRP_0A24_PAD002_IO_L01P_0_VRN_0D21_PAD003_IO_L02N_0C21_PAD004_IO_L02P_0E20_PAD005_IO_L03N_0D20_PAD006_IO_L03P_0_VREF_0F19_PAD007_IO_L05_0_No_PairE19_PAD008_IO_L06N_0E18_PAD009_IO_L06P_0D19_PAD010_IO_L07N_0C19_PAD011_IO_L07P_0B19_PAD012_IO_L08N_0A19_PAD013_IO_L08P_0G18_PAD014_IO_L09N_0F18_PAD015_IO_L09P_0_VREF_0D18_PAD016_IO_L37N_0C18_PAD017_IO_L37P_0G17_PAD018_IO_L38N_0H16_PAD019_IO_L38P_0F17_PAD020_IO_L39N_0F16_PAD021_IO_L39P_0
E17_PAD022_IO_L43N_0D17_PAD023_IO_L43P_0G16_PAD024_IO_L44N_0G15_PAD025_IO_L44P_0E16_PAD026_IO_L45N_0D16_PAD027_IO_L45P_0_VREF_0F15_PAD028_IO_L67N_0E15_PAD029_IO_L67P_0D15_PAD030_IO_L68N_0C15_PAD031_IO_L68P_0H15_PAD032_IO_L69N_0H14_PAD033_IO_L69P_0_VREF_0
G14_PAD034_IO_L73N_0F14_PAD035_IO_L73P_0E14_PAD036_IO_L74N_0_GCLK7PD14_PAD037_IO_L74P_0_GCLK6SC14_PAD038_IO_L75N_0_GCLK5PB14_PAD039_IO_L75P_0_GCLK4S
C17_VCCO_0C20_VCCO_0H17_VCCO_0H18_VCCO_0J14_VCCO_0J15_VCCO_0J16_VCCO_0
MGT 6
MGT 4
V2P7_BANK0FF672
(DIE DOWN)
VCC2V5
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
EG2121CA/LV1145B
NCA
GNDB
P
GNDAN
VCC
NCB
OEA
OEB
OSC
Should be routed differentially,and their tracelengths matched.
When the traces need to deviate
width should be modified, tomaintain a controlled impedance.
away from eachother, the trace
FPGA
C101, C102 and C103 should
BP
EthernetPhy
Matched Trace LengthsDifferential Pair
These Traces are should be routed as
Test Clock using LineSim
adjacent to X101
PS/2, Ethernet
2VP7 Bank 0Ethernet and PS/2
ML300 CPU - V2P7 Bank 0
Total tracelength GIGE_CLK_P = GIGE_CLK_N
GIGE_CLK_P and GIGE_CLK_N
placement is not critical.
R107 should be Placed immediatelyadjacent to the FPGA. R105 andR107 are for DC Current, so
be Placed immediately
NOTE: 62.5MHz osc is ideal for GIG-E125MHz osc must divide by 2 internally
100 Ohm differential signals.
PS/2Ports
PLB and OPBBus Error
These resistor provide for LVPECL to LVDSConversion, so use for the ED2121 CA OSC.DNP when using the LV1145B, as is an LVDSdifferential oscillator, and doesn't need.
These resistor should beplaced close to the FPGA
R107R106 R105
SYSACE_CLK_OE_NPLB_BUS_ERROROPB_BUS_ERROR
CASE_LIGHT
PHY_MDIO
SPI_DATA_CS_N
2
7
4
35
6
9
1
8
X101125MHZ
12 55
FPGA_GPIO_10FPGA_GPIO_[00:31]
GIGE_CLK_N
PS2_1_DATA_OUT
B24A24D21C21E20D20F19E19E18D19C19B19A19G18F18D18C18G17H16F17F16
E17D17G16G15E16D16F15E15D15C15H15H14
G14F14E14D14C14B14
C17C20H17H18J14J15J16
U1DEVICE=XC2VP7-6FF672C
12
R106
130R
1
2
C1011000PF
2
10.1UFC102
PHY_SLW1
PHY_MDC
PHY_RX_ERPHY_TX_ER
PHY_TXD1PHY_TXD0
PHY_TXD2PHY_TXD3PHY_COLPHY_CRSPHY_MDINTPHY_RESETPHY_SLW0
2
1 C10310UF
12
R107
100R
PHY_RXD2PHY_RXD1PHY_RXD0PHY_RX_DVPHY_RX_CLK
PHY_TX_CLKPHY_TX_EN
PHY_RXD3
21130R
R105
FPGA_PWR_SIG_N
PS2_1_DATA_IN
PS2_1_CLK_INPS2_2_DATA_OUT
PS2_1_CLK_OUT
PS2_2_CLK_OUTPS2_2_DATA_IN
PS2_2_CLK_IN
GIGE_CLK_P
B
0402
VCC2V5
0402
0402
VCC2V5
VCC3V3
0402
0402
VCC3V3
VCC3V3
0402
0402
0402
0402
VCC5
0402
GND
OE
OUT
VCC
OSC
G
S
D
GND
OE
OUT
VCC
OSC
PKG_TYPE=FF672PARTS=1LEVEL=STD
B13_PAD040_IO_L75N_1/GCLK3PC13_PAD041_IO_L75P_1/GCLK2SD13_PAD042_IO_L74N_1/GCLK1PE13_PAD043_IO_L74P_1/GCLK0SF13_PAD044_IO_L73N_1G13_PAD045_IO_L73P_1
H13_PAD046_IO_L69N_1/VREF_1H12_PAD047_IO_L69P_1C12_PAD048_IO_L68N_1D12_PAD049_IO_L68P_1E12_PAD050_IO_L67N_1F12_PAD051_IO_L67P_1D11_PAD052_IO_L45N_1/VREF_1E11_PAD053_IO_L45P_1G12_PAD054_IO_L44N_1G11_PAD055_IO_L44P_1D10_PAD056_IO_L43N_1E10_PAD057_IO_L43P_1
F11_PAD058_IO_L39N_1F10_PAD059_IO_L39P_1H11_PAD060_IO_L38N_1G10_PAD061_IO_L38P_1C9_PAD062_IO_L37N_1D9_PAD063_IO_L37P_1F9_PAD064_IO_L09N_1/VREF_1G9_PAD065_IO_L09P_1A8_PAD066_IO_L08N_1B8_PAD067_IO_L08P_1C8_PAD068_IO_L07N_1D8_PAD069_IO_L07P_1E9_PAD070_IO_L06N_1E8_PAD071_IO_L06P_1F8_PAD072_IO_L05_1/No_PairD7_PAD073_IO_L03N_1/VREF_1E7_PAD074_IO_L03P_1C6_PAD075_IO_L02N_1D6_PAD076_IO_L02P_1A3_PAD077_IO_L01N_1/VRP_1B3_PAD078_IO_L01P_1/VRN_1C7_VCCO_1H9_VCCO_1C10_VCCO_1H10_VCCO_1J11_VCCO_1J12_VCCO_1J13_VCCO_1
V2P7_BANK1FF672
(DIE DOWN)
MGT 7
MGT 9
SHDN
INOUT
ADJ
NC
GND_7
GND_3
GND_6
LT1763CS8
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
The Clock line to the Cardbus PCI4451
R108
FPGA
This resistor should
the Oscillatorsbe placed close to
BP
2VP7 Bank 1
placed close to the FPGAThese resistor should be
The clock signal should go to the FPGA,
so should be thick or a planeVCC3_PCI is a power line
Needed to prevent 3.3Von a 2.5V FPGA IO pin
be placed close tothe Oscillators
This resistor should
OSC
FPGA
PCI4451
PMC General Purpose IO
PMC General Purpose IO
ML300 CPU - V2P7 Bank 1
(R173)
R172
(R175)
(R176)
R179
R174
G13D13
and then terminate at the parallel Rsas shown below (Ref des for the SystemClock are shown, for System Ace, theyare shown in parentheses)
For DIP8 oscillators for System Clock andSys ACE Clock, series R (R172 and R173,respectively) should be immediately adj.to the output pin, and parallel Rs(R179/R174 and R176/R175, respectively)should be immediately adjacent to the FPGA.
R108
(R108) and the PMC Connectors (R1007)should have their Series Rs immediatelyadjacent to the FPGA.
The Feebackpath for Cardbus (to D13) shouldgo half way to the PCI4451, before comingback to the FPGA. The length to the PCI4451should equal the feedback loop.
The Cardbus layout is shown below.
5513
5
8 1
2
4
736
U4
21
38.3R
0805
R182
12
R181
0805
26.1R
2
1 04020.1UFC801
PCI_PORT_CLK_PMC_TMPPCI_PORT_CLK_CB_TMP
B13C13D13E13F13G13
H13H12C12D12E12F12D11E11G12G11D10E10
F11F10H11G10C9D9F9G9A8B8C8D8E9E8F8D7E7C6D6A3B3C7H9C10H10J11J12J13
U1DEVICE=XC2VP7-6FF672C
PCI_PORT_CLK_PMC
FPGA_PMC_CONN4_IO61PCI_PORT_CLK_CB
SYSACE_CLK
SYSACE_CLK
SYSACE_CLK_OE_N
4
1
5
8
X102100MHZ
FPGA_PMC_CONN4_IO[0:63]FPGA_PMC_CONN4_IO34
FPGA_PMC_CONN4_IO44FPGA_PMC_CONN4_IO46FPGA_PMC_CONN4_IO48FPGA_PMC_CONN4_IO50FPGA_PMC_CONN4_IO35FPGA_PMC_CONN4_IO37
FPGA_PMC_CONN4_IO51FPGA_PMC_CONN4_IO62FPGA_PMC_CONN4_IO60FPGA_PMC_CONN4_IO59FPGA_PMC_CONN4_IO57FPGA_PMC_CONN4_IO58FPGA_PMC_CONN4_IO55FPGA_PMC_CONN4_IO53FPGA_PMC_CONN4_IO49FPGA_PMC_CONN4_IO56FPGA_PMC_CONN4_IO45
FPGA_PMC_CONN4_IO47FPGA_PMC_CONN4_IO43FPGA_PMC_CONN4_IO41FPGA_PMC_CONN4_IO39FPGA_PMC_CONN4_IO54FPGA_PMC_CONN4_IO52
FPGA_PMC_CONN4_IO33FPGA_PMC_CONN4_IO31FPGA_PMC_CONN4_IO30FPGA_PMC_CONN4_IO42FPGA_PMC_CONN4_IO28FPGA_PMC_CONN4_IO40FPGA_PMC_CONN4_IO38FPGA_PMC_CONN4_IO36
PCI_FPGA_PMC_TMS
1
2
3
Q103BSS138
4
1
5
8
X10433.000MHZ
214.70K
R180
CLK_100MHZ_OSC
1 2
R17325.5R
2125.5RR172
21
25.5R
R108
1 2R1007
25.5R
SYSACE_CLK_OE
12
R175
100R
21100R
R174
12
R176
100R
21100R
R179
12
R1006
4.70K
2
1 C19733UF
NC
VCC3_PCI
PKG_TYPE=FF672PARTS=1LEVEL=STD
C4_PAD079_IO_L01N_2/VRP_2D3_PAD080_IO_L01P_2/VRN_2A2_PAD081_IO_L02N_2B1_PAD082_IO_L02P_2C2_PAD083_IO_L03N_2C1_PAD084_IO_L03P_2D2_PAD085_IO_L04N_2/VREF_2D1_PAD086_IO_L04P_2E4_PAD087_IO_L05N_2E3_PAD088_IO_L05P_2E2_PAD089_IO_L06N_2E1_PAD090_IO_L06P_2G6_PAD091_IO_L43N_2G5_PAD092_IO_L43P_2G4_PAD093_IO_L44N_2G3_PAD094_IO_L44P_2F1_PAD095_IO_L45N_2G1_PAD096_IO_L45P_2H6_PAD097_IO_L46N_2/VREF_2H5_PAD098_IO_L46P_2H4_PAD099_IO_L47N_2H3_PAD100_IO_L47P_2H2_PAD101_IO_L48N_2H1_PAD102_IO_L48P_2J7_PAD103_IO_L49N_2J6_PAD104_IO_L49P_2J5_PAD105_IO_L50N_2J4_PAD106_IO_L50P_2J3_PAD107_IO_L51N_2J2_PAD108_IO_L51P_2K6_PAD109_IO_L52N_2/VREF_2K5_PAD110_IO_L52P_2K4_PAD111_IO_L53N_2K3_PAD112_IO_L53P_2J1_PAD113_IO_L54N_2K1_PAD114_IO_L54P_2K7_PAD115_IO_L55N_2L8_PAD116_IO_L55P_2L7_PAD117_IO_L56N_2M7_PAD118_IO_L56P_2L6_PAD119_IO_L57N_2L5_PAD120_IO_L57P_2L4_PAD121_IO_L58N_2/VREF_2L3_PAD122_IO_L58P_2L2_PAD123_IO_L59N_2L1_PAD124_IO_L59P_2M8_PAD125_IO_L60N_2N8_PAD126_IO_L60P_2M6_PAD127_IO_L85N_2M5_PAD128_IO_L85P_2M4_PAD129_IO_L86N_2M3_PAD130_IO_L86P_2M2_PAD131_IO_L87N_2M1_PAD132_IO_L87P_2N7_PAD133_IO_L88N_2/VREF_2N6_PAD134_IO_L88P_2N5_PAD135_IO_L89N_2N4_PAD136_IO_L89P_2N3_PAD137_IO_L90N_2N2_PAD138_IO_L90P_2G2_VCCO_2J8_VCCO_2K2_VCCO_2K8_VCCO_2L9_VCCO_2M9_VCCO_2N9_VCCO_2
V2P7_BANK2FF672
(DIE DOWN)
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BPPMC GPIO and PCI
ML300 CPU - V2P7 Bank 2
2VP7 Bank 2PMC GPIO and PCI
5514
PCI_FPGA_IDSELFPGA_PMC_CONN4_IO11
FPGA_PMC_CONN4_IO[00:63]FPGA_PMC_CONN4_IO32FPGA_PMC_CONN4_IO26
FPGA_PMC_CONN4_IO24FPGA_PMC_CONN4_IO22
FPGA_PMC_CONN4_IO20FPGA_PMC_CONN4_IO18
FPGA_PMC_CONN4_IO29FPGA_PMC_CONN4_IO16FPGA_PMC_CONN4_IO14
FPGA_PMC_CONN4_IO12FPGA_PMC_CONN4_IO10
FPGA_PMC_CONN4_IO27FPGA_PMC_CONN4_IO25FPGA_PMC_CONN4_IO23FPGA_PMC_CONN4_IO19
FPGA_PMC_CONN4_IO21FPGA_PMC_CONN4_IO17
FPGA_PMC_CONN4_IO15
FPGA_PMC_CONN4_IO13
PCI_FPGA_AD16 210RR168
IIC_FPGA_SCL
PCI_FPGA_FRAMEPCI_FPGA_TRDY
PCI_FPGA_IRDYPCI_FPGA_STOP
PCI_FPGA_M66ENPCI_FPGA_DEVSELPCI_FPGA_PERR
PCI_FPGA_LOCKPCI_FPGA_SERR
PCI_FPGA_SB0PCI_FPGA_SDONE
PCI_FPGA_AD09
PCI_FPGA_CBE1
PCI_FPGA_CBE0
PCI_FPGA_PAR
PCI_FPGA_ACK64
PCI_FPGA_REQ64
AUDIO_FPGA_SDATA_OUTAUDIO_FPGA_SDATA_IN
AUDIO_FPGA_RESET_N
AUDIO_FPGA_CS0AUDIO_FPGA_SYNCH
AUDIO_BIT_FPGA_CLK
PCI_FPGA_AD[00:31]
PCI_FPGA_AD12
PCI_FPGA_AD08
PCI_FPGA_AD07
PCI_FPGA_AD05PCI_FPGA_AD13PCI_FPGA_AD14
PCI_FPGA_AD06PCI_FPGA_AD04PCI_FPGA_AD15PCI_FPGA_AD10PCI_FPGA_AD03PCI_FPGA_AD01PCI_FPGA_AD02
PCI_FPGA_AD11
PCI_FPGA_AD00
2
1 04020.1UFC802
C4D3A2B1C2C1D2D1E4E3E2E1G6G5G4G3F1G1H6H5H4H3H2H1J7J6J5J4J3J2K6K5K4K3J1K1K7L8L7M7L6L5L4L3L2L1M8N8M6M5M4M3M2M1N7N6N5N4N3N2G2J8K2K8L9M9N9
U1DEVICE=XC2VP7-6FF672C
VCC3_PCI
PKG_TYPE=FF672PARTS=1LEVEL=STD
P2_PAD139_IO_L90N_3P3_PAD140_IO_L90P_3P4_PAD141_IO_L89N_3P5_PAD142_IO_L89P_3P6_PAD143_IO_L88N_3P7_PAD144_IO_L88P_3R1_PAD145_IO_L87N_3/VREF_3R2_PAD146_IO_L87P_3R3_PAD147_IO_L86N_3R4_PAD148_IO_L86P_3R5_PAD149_IO_L85N_3R6_PAD150_IO_L85P_3P8_PAD151_IO_L60N_3R8_PAD152_IO_L60P_3T1_PAD153_IO_L59N_3T2_PAD154_IO_L59P_3T3_PAD155_IO_L58N_3T4_PAD156_IO_L58P_3T5_PAD157_IO_L57N_3/VREF_3T6_PAD158_IO_L57P_3R7_PAD159_IO_L56N_3T7_PAD160_IO_L56P_3T8_PAD161_IO_L55N_3U7_PAD162_IO_L55P_3U1_PAD163_IO_L54N_3V1_PAD164_IO_L54P_3U3_PAD165_IO_L53N_3U4_PAD166_IO_L53P_3U5_PAD167_IO_L52N_3U6_PAD168_IO_L52P_3V2_PAD169_IO_L51N_3/VREF_3V3_PAD170_IO_L51P_3V4_PAD171_IO_L50N_3V5_PAD172_IO_L50P_3V6_PAD173_IO_L49N_3V7_PAD174_IO_L49P_3W1_PAD175_IO_L48N_3W2_PAD176_IO_L48P_3W3_PAD177_IO_L47N_3W4_PAD178_IO_L47P_3W5_PAD179_IO_L46N_3W6_PAD180_IO_L46P_3Y1_PAD181_IO_L45N_3/VREF_3AA1_PAD182_IO_L45P_3Y3_PAD183_IO_L44N_3Y4_PAD184_IO_L44P_3Y5_PAD185_IO_L43N_3Y6_PAD186_IO_L43P_3AB3_PAD187_IO_L06N_3AB4_PAD188_IO_L06P_3AC1_PAD189_IO_L05N_3AC2_PAD190_IO_L05P_3AD1_PAD191_IO_L04N_3AD2_PAD192_IO_L04P_3AE1_PAD193_IO_L03N_3/VREF_3AF2_PAD194_IO_L03P_3AC3_PAD195_IO_L02N_3AD4_PAD196_IO_L02P_3AE3_PAD197_IO_L01N_3/VRP_3AF3_PAD198_IO_L01P_3/VRN_3P9_VCCO_3R9_VCCO_3T9_VCCO_3U2_VCCO_3U8_VCCO_3V8_VCCO_3Y2_VCCO_3
V2P7_BANK3FF672
(DIE DOWN)
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
2VP7 Bank 3IIC, Audio, PCI and Touch
IIC, Audio, PMC GPIO,
PCI and TouchScrn
ML300 CPU - V2P7 Bank 3
TouchscreenThe Touchscreen is on the ML300_PWR_IO board,and the connection is shown on page 55.
5515
FPGA_GPIO_09FPGA_GPIO_08FPGA_GPIO_07FPGA_GPIO_06
FPGA_GPIO_05FPGA_GPIO_04FPGA_GPIO_03FPGA_GPIO_02
FPGA_GPIO_01
FPGA_GPIO_00
FPGA_GPIO_[00:31] FPGA_CPU_RESETIIC_FPGA_SDA
TOUCH_CS_N
TOUCH_IRQ_NTOUCH_DOUT
TOUCH_BUSYTOUCH_DINIIC_FPGA_IRQ
TOUCH_DCLKIIC_CRIT_A
IIC_FPGA_WP
PCI_FPGA_CBE3
PCI_FPGA_CBE2
FPGA_PMC_CONN4_IO9
PCI_FPGA_CB_IRQSERPCI_FPGA_CB_SUSPEND
2
1 04020.1UFC803
P2P3P4P5P6P7R1R2R3R4R5R6P8R8T1T2T3T4T5T6R7T7T8U7U1V1U3U4U5U6V2V3V4V5V6V7W1W2W3W4W5W6Y1AA1Y3Y4Y5Y6AB3AB4AC1AC2AD1AD2AE1AF2AC3AD4AE3AF3P9R9T9U2U8V8Y2
U1DEVICE=XC2VP7-6FF672C
PCI_FPGA_CB_REQPCI_FPGA_CB_GNT
PCI_FPGA_PMC_TRSTPCI_FPGA_GBL_RSTPCI_FPGA_PMC_TCK
PCI_FPGA_PMC_TDOPCI_FPGA_PMC_TDI
PCI_FPGA_INTA
PCI_FPGA_INTCPCI_FPGA_INTB
PCI_FPGA_PRS1PCI_FPGA_INTD
PCI_FPGA_PRS2PCI_FPGA_BM3
PCI_FPGA_BUS_RSTPCI_FPGA_BM4
PCI_FPGA_PMC_GNTPCI_FPGA_PMC_REQ
VCC3_PCI
PCI_FPGA_AD[00:31]
PCI_FPGA_AD31PCI_FPGA_AD26PCI_FPGA_AD27PCI_FPGA_AD28PCI_FPGA_AD24
PCI_FPGA_AD25PCI_FPGA_AD23
PCI_FPGA_AD20
PCI_FPGA_AD21
PCI_FPGA_AD18
PCI_FPGA_AD19
PCI_FPGA_AD16PCI_FPGA_AD17
PCI_FPGA_AD30
PCI_FPGA_AD22
PCI_FPGA_AD29
VCC2V5
PKG_TYPE=FF672PARTS=1LEVEL=STD
AC6_PAD199_IO_L01N_4/DOUTAD6_PAD200_IO_L01P_4/INIT_BAB7_PAD201_IO_L02N_4/D0AC7_PAD202_IO_L02P_4/D1AA7_PAD203_IO_L03N_4/D2AA8_PAD204_IO_L03P_4/D3Y8_PAD205_IO_L05_4/No_PairAB8_PAD206_IO_L06N_4/VRP_4AB9_PAD207_IO_L06P_4/VRN_4AC8_PAD208_IO_L07N_4AD8_PAD209_IO_L07P_4/VREF_4AE8_PAD210_IO_L08N_4AF8_PAD211_IO_L08P_4Y9_PAD212_IO_L09N_4AA9_PAD213_IO_L09P_4/VREF_4AC9_PAD214_IO_L37N_4AD9_PAD215_IO_L37P_4Y10_PAD216_IO_L38N_4W11_PAD217_IO_L38P_4AA10_PAD218_IO_L39N_4AA11_PAD219_IO_L39P_4
AB10_PAD220_IO_L43N_4AC10_PAD221_IO_L43P_4Y11_PAD222_IO_L44N_4Y12_PAD223_IO_L44P_4AB11_PAD224_IO_L45N_4AC11_PAD225_IO_L45P_4/VREF_4AA12_PAD226_IO_L67N_4AB12_PAD227_IO_L67P_4AC12_PAD228_IO_L68N_4AD12_PAD229_IO_L68P_4W12_PAD230_IO_L69N_4W13_PAD231_IO_L69P_4/VREF_4
Y13_PAD232_IO_L73N_4AA13_PAD233_IO_L73P_4AB13_PAD234_IO_L74N_4/GCLK3SAC13_PAD235_IO_L74P_4/GCLK2PAD13_PAD236_IO_L75N_4/GCLK1SAE13_PAD237_IO_L75P_4/GCLK0P
W9_VCCO_4AD7_VCCO_4V11_VCCO_4V12_VCCO_4V13_VCCO_4W10_VCCO_4AD10_VCCO_4
V2P7_BANK4FF672
(DIE DOWN)
MGT 16
MGT 18
CON_SMA_ST
0402
CON_SMA_ST
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
J2J1
R120
Should be routed differentially,and their tracelengths matched.
When the traces need to deviate
width should be modified, tomaintain a controlled impedance.
away from eachother, the trace
FPGA
Serial
This resistor should be
Matched Trace Lengths
BP
These Traces are should be routed as 100 Ohm differential signals, 8mil track, 10mil spacing
Total tracelength GIGE_CLK_LVPCL_P + GIGE_CLK_P = GIGE_CLK_LVPCL_N + GIGE_CLK_N
2VP7 Bank 4TFT LCD, Serial and SPI
Ports
To TFT ConnThrough 3.3V
2.5V SPI
ML300 CPU - V2P7 Bank 4
TFT LCD, Serial, SPI
R120 shouldbe placed immediatelyadjacent to the FPGA
USER_MGT_CLK_P and USER_MGT_CLK_N
placed close to the FPGASee figure above.
Level Shifterpage 44
MAX3388Epage 36
25LC160page 41
16 55
USER_MGT_CLK_P
FPGA_GPIO_[00:31]
FPGA_GPIO_12FPGA_GPIO_13
FPGA_GPIO_11
SPI_DATA_OUT
SPI_DATA_INSPI_CLK
1
2
3
4
5
J2
CON_SMA_ST
12
R120
100R
5
4
3
2
1
J1
CON_SMA_ST
TFT_FPGA_CLK
TFT_FPGA_DETFT_FPGA_B5
TFT_FPGA_HSYNCAC6AD6AB7AC7AA7AA8Y8AB8AB9AC8AD8AE8AF8Y9AA9AC9AD9Y10W11
AA10AA11
AB10AC10Y11Y12
AB11AC11AA12AB12AC12AD12W12W13
Y13AA13AB13AC13AD13AE13
W9AD7V11V12V13W10
AD10
U1DEVICE=XC2VP7-6FF672C
TFT_FPGA_R1
TFT_FPGA_VSYNCTFT_FPGA_R0
TFT_FPGA_R3TFT_FPGA_R2
TFT_FPGA_R5TFT_FPGA_R4
TFT_FPGA_B3
TFT_FPGA_B1
TFT_FPGA_G4TFT_FPGA_DPS
TFT_FPGA_G5TFT_FPGA_B0
TFT_FPGA_B2
TFT_FPGA_B4
TFT_FPGA_G0TFT_FPGA_G1TFT_FPGA_G2TFT_FPGA_G3
USER_MGT_CLK_N
RXD1_FPGATXD1_FPGACTS1_FPGARTS1_FPGARXD2_FPGATXD2_FPGACTS2_FPGARTS2_FPGA
0805
VCC2V5VCC2V5
0402
0402
VCC2V5
PKG_TYPE=FF672PARTS=1LEVEL=STD
V14_VCCO_5
AE14_PAD238_IO_L75N_5/GCLK7SAD14_PAD239_IO_L75P_5/GCLK6PAC14_PAD240_IO_L74N_5/GCLK5SAB14_PAD241_IO_L74P_5/GCLK4PAA14_PAD242_IO_L73N_5Y14_PAD243_IO_L73P_5
W14_PAD244_IO_L69N_5/VREF_5W15_PAD245_IO_L69P_5AD15_PAD246_IO_L68N_5AC15_PAD247_IO_L68P_5AB15_PAD248_IO_L67N_5AA15_PAD249_IO_L67P_5AC16_PAD250_IO_L45N_5/VREF_5AB16_PAD251_IO_L45P_5Y15_PAD252_IO_L44N_5Y16_PAD253_IO_L44P_5AC17_PAD254_IO_L43N_5AB17_PAD255_IO_L43P_5
AA16_PAD256_IO_L39N_5AA17_PAD257_IO_L39P_5W16_PAD258_IO_L38N_5Y17_PAD259_IO_L38P_5AD18_PAD260_IO_L37N_5AC18_PAD261_IO_L37P_5AA18_PAD262_IO_L09N_5/VREF_5Y18_PAD263_IO_L09P_5AF19_PAD264_IO_L08N_5AE19_PAD265_IO_L08P_5AD19_PAD266_IO_L07N_5/VREF_5AC19_PAD267_IO_L07P_5AB18_PAD268_IO_L06N_5/VRP_5AB19_PAD269_IO_L06P_5/VRN_5Y19_PAD270_IO_L05_5/No_PairAA19_PAD271_IO_L03N_5/D4AA20_PAD272_IO_L03P_5/D5AC20_PAD273_IO_L02N_5/D6AB20_PAD274_IO_L02P_5/D7AD21_PAD275_IO_L01N_5/RDWR_BAC21_PAD276_IO_L01P_5/CS_B
V16_VCCO_5W17_VCCO_5W18_VCCO_5AD17_VCCO_5AD20_VCCO_5
V15_VCCO_5
V2P7_BANK5FF672
(DIE DOWN)
MGT 19
MGT 21
0402 0402
0402
EG2121CA/LV1145B
NCA
GNDB
P
GNDAN
VCC
NCB
OEA
OEB
OSC
0402
0402
0402
VTTDDR
VTTDDR
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
VTT
When the traces need to deviate
width should be modified, toaway from eachother, the trace
GIGE_CLK_P and GIGE_CLK_N
placement is not critical.
R107 R105R106
FPGACDCV857
must be matched tracelength. The Lengthof the feedback loop (i.e. length from
The Negative DDR Clock signal should berouted s.t. the tracelength matches thatof the positive DDR Clock net, and thelength to the load cap (C366) and term R(R310) match the length of the feedback
FPGA back to FPGA) for the DDR_XXX_CK net
DDR_RES_CK
DDR_FPGA_CK
DDR_RES_CK_N
DDR_FPGA_CK_N
R302
R303
R308
R307
R310
R309
should match the net to DDR Clk Replicator
FPGA
2VP7 Bank 5
BP
System ACE and CPU Debug
Matched Trace Lengths
C104, C105 and C106 should
adjacent to X103be Placed imediately
ML300 CPU - V2P7 Bank 5
R114 are for DC Current, soadjacent to the FPGA. R113 andR119 should be Placed immediately
maintain a controlled impedance.
and their tracelengths matched.Should be routed differentially,
placed close to the FPGAThis resistor should be
R119 R105
See Diagram Below
loop.
See Page 28 for the DDR Clock Replicator
R114
C366
GNDVTT
The Clock traces to the DDR PLL (CDCV857)
These resistor provide for LVPECL to LVDSConversion, so use for the ED2121 CA OSC.DNP when using the LV1145B, as is an LVDSdifferential oscillator, and doesn't need.
System ACE, CPU Debug
17 56
DDR_RES_CK
12
R309
49.9R
DDR_RES_CK_N
2
1 C36610PF
12
49.9R
R310
2
7
4
35
6
9
1
8
X103
156.25MHZ
INFINBAND_CLK_P
CPU_TDO_TMP
12
R114
130R
1
2
C1041000PF
2
10.1UFC105
AE14AD14AC14AB14AA14Y14
W14W15
AD15AC15AB15AA15AC16AB16Y15Y16
AC17AB17
AA16AA17W16Y17
AD18AC18AA18Y18
AF19AE19AD19AC19AB18AB19Y19
AA19AA20AC20AB20AD21AC21
V15V16W17W18
AD17AD20
V14
U1DEVICE=XC2VP7-6FF672C
SYSACE_MPBRDYSYSACE_MPIRQSYSACE_MPCE
SYSACE_MPD07SYSACE_MPD08SYSACE_MPD09SYSACE_MPD10SYSACE_MPD11SYSACE_MPD12SYSACE_MPD13SYSACE_MPD14SYSACE_MPD15SYSACE_MPA04SYSACE_MPA05SYSACE_MPA06
SYSACE_MPD06SYSACE_MPD05SYSACE_MPD04SYSACE_MPD03SYSACE_MPD02SYSACE_MPD01SYSACE_MPD00SYSACE_MPA03SYSACE_MPA02SYSACE_MPA01SYSACE_MPA00SYSACE_MPWE
SYSACE_MPDE12
R119
100R
21130R
R113
2
1 C10610UF
FPGA_GPIO_14FPGA_GPIO_15
CPU_HALT_NCPU_TMS
CPU_TDICPU_TCK
CPU_TRST
INFINBAND_CLK_N
VCC2V5
VCC2V5
PKG_TYPE=FF672PARTS=1LEVEL=STD
AF24_PAD277_IO_L01P_6/VRN_6AE24_PAD278_IO_L01N_6/VRP_6AD23_PAD279_IO_L02P_6AC24_PAD280_IO_L02N_6AE26_PAD281_IO_L03P_6AF25_PAD282_IO_L03N_6/VREF_6AD25_PAD283_IO_L04P_6AD26_PAD284_IO_L04N_6AC25_PAD285_IO_L05P_6AC26_PAD286_IO_L05N_6AB23_PAD287_IO_L06P_6AB24_PAD288_IO_L06N_6Y21_PAD289_IO_L43P_6Y22_PAD290_IO_L43N_6Y23_PAD291_IO_L44P_6Y24_PAD292_IO_L44N_6AA26_PAD293_IO_L45P_6Y26_PAD294_IO_L45N_6/VREF_6W21_PAD295_IO_L46P_6W22_PAD296_IO_L46N_6W23_PAD297_IO_L47P_6W24_PAD298_IO_L47N_6W25_PAD299_IO_L48P_6W26_PAD300_IO_L48N_6V20_PAD301_IO_L49P_6V21_PAD302_IO_L49N_6V22_PAD303_IO_L50P_6V23_PAD304_IO_L50N_6V24_PAD305_IO_L51P_6V25_PAD306_IO_L51N_6/VREF_6U21_PAD307_IO_L52P_6U22_PAD308_IO_L52N_6U23_PAD309_IO_L53P_6U24_PAD310_IO_L53N_6V26_PAD311_IO_L54P_6U26_PAD312_IO_L54N_6U20_PAD313_IO_L55P_6T19_PAD314_IO_L55N_6T20_PAD315_IO_L56P_6R20_PAD316_IO_L56N_6T21_PAD317_IO_L57P_6T22_PAD318_IO_L57N_6/VREF_6T23_PAD319_IO_L58P_6T24_PAD320_IO_L58N_6T25_PAD321_IO_L59P_6T26_PAD322_IO_L59N_6R19_PAD323_IO_L60P_6P19_PAD324_IO_L60N_6R21_PAD325_IO_L85P_6R22_PAD326_IO_L85N_6R23_PAD327_IO_L86P_6R24_PAD328_IO_L86N_6R25_PAD329_IO_L87P_6R26_PAD330_IO_L87N_6/VREF_6P20_PAD331_IO_L88P_6P21_PAD332_IO_L88N_6P22_PAD333_IO_L89P_6P23_PAD334_IO_L89N_6P24_PAD335_IO_L90P_6P25_PAD336_IO_L90N_6P18_VCCO_6R18_VCCO_6T18_VCCO_6U19_VCCO_6U25_VCCO_6V19_VCCO_6Y25_VCCO_6
V2P7_BANK6FF672
(DIE DOWN)0402
0402
0402
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
CPU Trace and DDR2VP7 Bank 6
JTAG/TRC
CPU Trace, DDR
ML300 CPU - V2P7 Bank 6
See Diagram and Notes on previous pagefor details of routing and placement
These resistors should beplaced close to the FPGA
5518
DDR_RES_CK_N
DDR_RES_CK
DDR_FPGA_CK
DDR_FPGA_A[00:12]
DDR_FPGA_A11DDR_FPGA_A10DDR_FPGA_A09DDR_FPGA_A08DDR_FPGA_A07
DDR_FPGA_A12
DDR_FPGA_DQ[00:31]
DDR_FPGA_DQ20
DDR_FPGA_DQ22DDR_FPGA_DQ21
DDR_FPGA_DQ24DDR_FPGA_DQ25
DDR_FPGA_DQ27DDR_FPGA_DQ26
DDR_FPGA_DQ30DDR_FPGA_DQ29DDR_FPGA_DQ28
DDR_FPGA_DQ19DDR_FPGA_DQ18DDR_FPGA_DQ17DDR_FPGA_DQ16
DDR_FPGA_DQ31
DDR_FPGA_DQ23
BANK6_VRPBANK6_VRN
TS6TS5TS4TS3TS2ETS1E
TS2OTS1O
TRC_CLK
FPGA_GPIO_31
FPGA_GPIO_[00:31]FPGA_GPIO_16
FPGA_GPIO_30FPGA_GPIO_29FPGA_GPIO_28FPGA_GPIO_27FPGA_GPIO_26FPGA_GPIO_25FPGA_GPIO_24FPGA_GPIO_23
FPGA_GPIO_21FPGA_GPIO_22
FPGA_GPIO_20FPGA_GPIO_19FPGA_GPIO_18FPGA_GPIO_17
21100RR122
1 2
R30725.5R
2125.5RR308
DDR_FPGA_DQS2
DDR_FPGA_DM2
DDR_FPGA_DQS3DDR_FPGA_DM3
VREF_DDR
1 2
R121100R
AF24AE24AD23AC24AE26AF25AD25AD26AC25AC26AB23AB24Y21Y22Y23Y24
AA26Y26W21W22W23W24W25W26V20V21V22V23V24V25U21U22U23U24V26U26U20T19T20R20T21T22T23T24T25T26R19P19R21R22R23R24R25R26P20P21P22P23P24P25P18R18T18U19U25V19Y25
U1
DEVICE=XC2VP7-6FF672C
DDR_FPGA_CK_N
VCC2V5
VCC2V5
PKG_TYPE=FF672PARTS=1LEVEL=STD
N25_PAD337_IO_L90P_7N24_PAD338_IO_L90N_7N23_PAD339_IO_L89P_7N22_PAD340_IO_L89N_7N21_PAD341_IO_L88P_7N20_PAD342_IO_L88N_7/VREF_7M26_PAD343_IO_L87P_7M25_PAD344_IO_L87N_7M24_PAD345_IO_L86P_7M23_PAD346_IO_L86N_7M22_PAD347_IO_L85P_7M21_PAD348_IO_L85N_7N19_PAD349_IO_L60P_7M19_PAD350_IO_L60N_7L26_PAD351_IO_L59P_7L25_PAD352_IO_L59N_7L24_PAD353_IO_L58P_7L23_PAD354_IO_L58N_7/VREF_7L22_PAD355_IO_L57P_7L21_PAD356_IO_L57N_7M20_PAD357_IO_L56P_7L20_PAD358_IO_L56N_7L19_PAD359_IO_L55P_7K20_PAD360_IO_L55N_7K26_PAD361_IO_L54P_7J26_PAD362_IO_L54N_7K24_PAD363_IO_L53P_7K23_PAD364_IO_L53N_7K22_PAD365_IO_L52P_7K21_PAD366_IO_L52N_7/VREF_7J25_PAD367_IO_L51P_7J24_PAD368_IO_L51N_7J23_PAD369_IO_L50P_7J22_PAD370_IO_L50N_7J21_PAD371_IO_L49P_7J20_PAD372_IO_L49N_7H26_PAD373_IO_L48P_7H25_PAD374_IO_L48N_7H24_PAD375_IO_L47P_7H23_PAD376_IO_L47N_7H22_PAD377_IO_L46P_7H21_PAD378_IO_L46N_7/VREF_7G26_PAD379_IO_L45P_7F26_PAD380_IO_L45N_7G24_PAD381_IO_L44P_7G23_PAD382_IO_L44N_7G22_PAD383_IO_L43P_7G21_PAD384_IO_L43N_7E26_PAD385_IO_L06P_7E25_PAD386_IO_L06N_7E24_PAD387_IO_L05P_7E23_PAD388_IO_L05N_7D26_PAD389_IO_L04P_7D25_PAD390_IO_L04N_7/VREF_7C26_PAD391_IO_L03P_7C25_PAD392_IO_L03N_7B26_PAD393_IO_L02P_7A25_PAD394_IO_L02N_7D24_PAD395_IO_L01P_7/VRN_7C23_PAD396_IO_L01N_7/VRP_7G25_VCCO_7J19_VCCO_7K19_VCCO_7K25_VCCO_7L18_VCCO_7M18_VCCO_7N18_VCCO_7
V2P7_BANK7FF672
(DIE DOWN)
0402
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
VREF
VREF
VREF
VREF
VREF
2VP7 Bank 7DDR and Parallel Port
ML300 CPU - V2P7 Bank 7
DDR and Parallel Port 5519
PP_FPGA_USERDEF3
DDR_FPGA_DQS1DDR_FPGA_DQS0
DDR_FPGA_DM1DDR_FPGA_DM0
DDR_FPGA_RAS_N
DDR_FPGA_CAS_NDDR_FPGA_CKEDDR_FPGA_BA1DDR_FPGA_BA0DDR_FPGA_CS_NDDR_FPGA_WE_N
21100RR124
1 2
R123100R
N25N24N23N22N21N20M26M25M24M23M22M21N19M19L26L25L24L23L22L21M20L20L19K20K26J26K24K23K22K21J25J24J23J22J21J20H26H25H24H23H22H21G26F26G24G23G22G21E26E25E24E23D26D25C26C25B26A25D24C23G25J19K19K25L18M18N18
U1
DEVICE=XC2VP7-6FF672C
DDR_FPGA_DQ[00:31]
DDR_FPGA_DQ15
DDR_FPGA_DQ13DDR_FPGA_DQ12DDR_FPGA_DQ11DDR_FPGA_DQ10DDR_FPGA_DQ09
DDR_FPGA_DQ07
DDR_FPGA_DQ06DDR_FPGA_DQ05DDR_FPGA_DQ04DDR_FPGA_DQ03DDR_FPGA_DQ02
DDR_FPGA_DQ00DDR_FPGA_DQ01
DDR_FPGA_DQ08
DDR_FPGA_DQ14
BANK7_VRPBANK7_VRN
DDR_FPGA_A[00:12]
DDR_FPGA_A01DDR_FPGA_A00
DDR_FPGA_A06
DDR_FPGA_A02DDR_FPGA_A03DDR_FPGA_A04DDR_FPGA_A05
VREF_DDR
PP_FPGA_NWAITPP_FPGA_USERDEF1
PP_FPGA_INTR
PP_FPGA_DATA7PP_FPGA_DATA6PP_FPGA_DATA5PP_FPGA_DATA4PP_FPGA_DATA3PP_FPGA_DATA2PP_FPGA_DATA1
PP_FPGA_NINITPP_FPGA_NASTROBEPP_FPGA_DATA0
PP_FPGA_USERDEF2
PP_FPGA_HDPP_FPGA_NWRITEPP_FPGA_NDSTROBE
PP_FPGA_DIR
VCC1V5
VCC2V5
VCC2V5
VCC5
VCC2V5
VCC2V5
0402
0402
0402 0402
VCC2V5
0402
VCC2V5
0402
PARTS=1LEVEL=STD
PKG_TYPE=FF672
F20_DXPG19_DXN
D5_RSVDE6_VBATT
F7_TMSG8_TCK
AB21_M2
C3_GND
D4_GND
E5_GND
F6_GND
G7_GND
Y7_GND
AA6_GND
AB5_GND
AC4_GND
AD3_GND
C24_GND
D23_GND
E22_GND
F21_GND
G20_GND
K10_GND
K12_GND
K13_GND
K14_GND
K15_GND
K17_GND
L11_GND
L12_GND
L13_GND
L14_GND
L15_GND
L16_GND
M10_GND
M11_GND
M12_GND
M13_GND
M14_GND
M15_GND
M16_GND
M17_GND
N10_GND
N11_GND
N12_GND
N13_GND
N14_GND
N15_GND
N16_GND
N17_GND
P10_GND
P11_GND
P12_GND
P13_GND
P14_GND
P15_GND
P16_GND
P17_GND
R10_GND
R11_GND
R12_GND
R13_GND
R14_GND
R15_GND
R16_GND
R17_GND
T11_GND
T12_GND
T13_GND
T14_GND
T15_GND
T16_GND
U10_GND
U12_GND
U13_GND
U14_GND
U15_GND
U17_GND
Y20_GND
AA21_GND
AB22_GND
AC23_GND
AD24_GND
N1_VCCAUX
P1_VCCAUX
A13_VCCAUX
A14_VCCAUX
AE2_VCCAUX
B25_VCCAUX
N26_VCCAUX
P26_VCCAUX
AE25_VCCAUX
AF13_VCCAUX
AF14_VCCAUX
H8_VCCINT
J9_VCCINT
K9_VCCINT
U9_VCCINT
V9_VCCINT
W8_VCCINT
H19_VCCINT
J10_VCCINT
J17_VCCINT
J18_VCCINT
K11_VCCINT
K16_VCCINT
K18_VCCINT
L10_VCCINT
L17_VCCINT
T10_VCCINT
T17_VCCINT
U11_VCCINT
U16_VCCINT
U18_VCCINT
V10_VCCINT
V17_VCCINT
V18_VCCINT
W19_VCCINT
E21_HSWAP_EN
D22_PROG_B
AC5_PWRDWN_B
AB6_DONE
AC22_M0W20_M1
H20_TDIH7_TDO
W7_CCLK
B2_VCCAUX
V2P7_MISCFF672
(DIE DOWN)
GS
D
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
2VP7 Misc / Config
BP
FPGA_PWRDWN_B
Done LED
Miscellaneous/Config
ML300 CPU - V2P7 Auxiliary
See Page 35 for placement of DS101
These signals (FPGA_DXP, FPGA_DXN)should be routed as differential
much as possible
signals to the MAX11617AMEE (U251),and isolated from other signals as
20 55
21
DS101
BLUE
1 2
3 Q101
BSS138
F20G19
D5E6
F7G8
AB21
C3
D4
E5
F6
G7
Y7
AA6
AB5
AC4
AD3
C24
D23
E22
F21
G20
K10
K12
K13
K14
K15
K17
L11
L12
L13
L14
L15
L16
M10
M11
M12
M13
M14
M15
M16
M17
N10
N11
N12
N13
N14
N15
N16
N17
P10
P11
P12
P13
P14
P15
P16
P17
R10
R11
R12
R13
R14
R15
R16
R17
T11
T12
T13
T14
T15
T16
U10
U12
U13
U14
U15
U17
Y20
AA21
AB22
AC23
AD24
B2
N1
P1
A13
A14
AE2
B25
N26
P26
AE25
AF13
AF14
H8
J9
K9
U9
V9
W8
H19
J10
J17
J18
K11
K16
K18
L10
L17
T10
T17
U11
U16
U18
V10
V17
V18
W19
E21
D22
AC5
AB6
AC22W20
H20H7
W7
U1
DEVICE=XC2VP7-6FF672C
FPGA_TDO
12
R169
100R
FPGA_CCLK1
TP101
2164.9R
R127
12
R171
330R
0402
214.70KR125
FPGA_DONE
FPGA_MODE_2
FPGA_MODE_0FPGA_MODE_1
FPGA_TDI
DONE_LED
1
TP104
1
TP102
12
4.70K
R133
12
R130
DNP
12
R129
4.70K
FPGA_D5_RSVD
FPGA_DXN
FPGA_VBATT
FPGA_DONEFPGA_PROG_B
FPGA_HSWAP
FPGA_DXP
FPGA_TCKFPGA_TMS
VTT_MGT
VTT_MGT
VTT_MGT
GND_MGT
0402GND_MGT
0402
0402
0402
GND_MGT
VTT_MGT
VCCA_MGT
VTT_MGT
VCCA_MGT
VCCA_MGT
VCCA_MGT
VCCA_MGT
VTT_MGT
VTT_MGT
VTT_MGT
VCCA_MGT
VCCA_MGT
VCCA_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
HSSDC2
1364532-2
TX+TX-
GND_4
RX-RX+
GND_1
GND_7
0402
HSSDC2
1364532-2
TX+TX-
GND_4
RX-RX+
GND_1
GND_7
0402
0402
0402
PKG_TYPE=FF672PARTS=1LEVEL=STD
AF21_RXPPAD21AF20_RXNPAD21
AF16_RXPPAD19AF15_RXNPAD19
AF12_TXNPAD18AF11_TXPPAD18
AF10_RXPPAD18AF9_RXNPAD18
AF5_RXPPAD16AF4_RXNPAD16
AF6_TXPPAD16AF7_TXNPAD16
AE15_AVCCAUXRX19
AF17_TXPPAD19AF18_TXNPAD19
AF22_TXPPAD21AF23_TXNPAD21
AD11_GNDA18
AD5_GNDA16
AD16_GNDA19
AE20_AVCCAUXRX21
AD22_GNDA21
AE6_AVCCAUXTX16
AE4_AVCCAUXRX16
AE11_AVCCAUXTX18
AE9_AVCCAUXRX18
AE17_AVCCAUXTX19
AE22_AVCCAUXTX21
AE7_VTTXPAD16
AE5_VTRXPAD16
AE12_VTTXPAD18
AE18_VTTXPAD19
AE23_VTTXPAD21
AE21_VTRXPAD21
AE16_VTRXPAD19
AE10_VTRXPAD18
MGT 21
MGT 19
MGT 18
MGT 16
FF672(DIE DOWN)
V2P7_MGT_BOTTOM
GND_7
HRX+HRX-
GND_4
HTX-HTX+
GND_1
SERIAL_ATA
67490-9221
KEY
GND_7
HRX+HRX-
GND_4
HTX-HTX+
GND_1
SERIAL_ATA
67490-9221
KEY
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
1. Each of the pairs must be 100 ohm controlled differential impedance
1. Each of the pairs must be matched trace length, such that
Silkscreen: "HSSCD2"
NOTES
GIGEX_XX_P + GIGEX_XX_CONN_P = GIGEX_XX_N + GIGEX_XX_CONN_N
3. Put res on transmit lines (TX) near the connector,Caps on receive lines (RX) near the FPGA,
4. Serial ATA Connectors shown flipped to more easilymap to the V2Pro MGT pinout
- track width XX mils- track spacing XX mils
ML300 CPU
V2P7 MGT Bottom
2VP7 MGT BottomHSSCD2 and Serial ATA
Silkscreen: "Serial ATA"
SATA Device (Peripheral)
SATA Host
21 55
1
23
4
56
7
P119
SA1_PORT_RXP
SA1_PORT_RXN
SA1_PORT_TXN
SA1_PORT_TXP
7
65
4
32
1
P120
SA2_PORT_RXN
SA2_PORT_TXN
AF21AF20
AF16AF15
AF12AF11
AF10AF9
AF5AF4
AF6AF7
AE9
AE15
AF17AF18
AF22AF23
AE22
AE4
AE12
AE11
AD11
AE10
AD5
AE6
AE5
AE7
AE16
AE18
AE17
AD16
AE21
AE23
AE20
AD22
U1
XC2VP7-6FF672C
21
C1150.01UF
0402
SA2_PORT_TXP21
0RR141
1 2
C1160.01UF
0402
21C1170.01UF
0402
1 20RR139
21
C1120.01UF
0402
21
C1180.01UF
0402
1 2
C1130.01UF
0402
IB2_PORT_RXPIB2_PORT_RXN
210RR137
IB2_PORT_TXNIB2_PORT_TXP
1
23
5
4
6
7
P111
1 2
C1190.01UF
0402
210RR135
IB1_PORT_RXPIB1_PORT_RXN
IB1_PORT_TXNIB1_PORT_TXP
7
6
4
5
32
1
P112
1 2
C1140.01UF
0402
1
2
0.22UFC122
C0805
1
2
0.22UFC0805
C1231
2
C121
C08050.22UF
1
2
0.22UFC0805
C120
21
1000_OHM
FB107
IND_BLM21A1 2
FB105
1000_OHMIND_BLM21A
AVCC_RX16
2
10.22UF
C0805
C134
1
2
C129
C08050.22UF
2
10.22UF
C0805
C125
2
1 C132
C08050.22UF
1
2
0.22UFC0805
C131
2
1 C133
C08050.22UF
2
1 C126
C08050.22UF
1
2
0.22UFC0805
C130
21
1000_OHM
FB113
IND_BLM21A
1 2
FB112
1000_OHMIND_BLM21A
21
1000_OHM
FB108
IND_BLM21A
1 2
FB116
1000_OHMIND_BLM21A
21
1000_OHM
FB109
IND_BLM21A
1 2
FB111
1000_OHMIND_BLM21A
21
1000_OHM
FB114
IND_BLM21A
1 2
FB115
1000_OHMIND_BLM21A
1 2
FB106
1000_OHMIND_BLM21A
21
1000_OHM
FB110
IND_BLM21A
1 2
FB104
1000_OHMIND_BLM21A
21
1000_OHM
FB101
IND_BLM21A
1 2
FB103
1000_OHMIND_BLM21A
21
1000_OHM
FB102
IND_BLM21A
1 2
R1400R
1 2
R1380R
1 2
R1360R
1 2
R1340R
2
1 C127
C08050.22UF
2
1 C135
C08050.22UF
2
1 C124
C08050.22UF
1
2
0.22UFC0805
C128
AVCC_TX19
AVCC_TX18
AVCC_T16
VTT_TX16
VTT_RX16
VTT_TX18
VTT_RX18
AVCC_RX18
VTT_TX19
VTT_RX19
AVCC_RX19
AVCC_RX21
VTT_RX21
VTT_TX21
AVCC_TX21
SA2_PORT_RXP
VCCA_MGT
VCCA_MGT
VCCA_MGT
VCCA_MGT
PKG_TYPE=FF672PARTS=1LEVEL=STD
A22_TXPPAD4
A17_TXPPAD6
A15_RXNPAD6
A6_TXPPAD9
A4_RXNPAD9
C22_GNDA4
B20_AVCCAUXRX4
B21_VTRXPAD4
B23_VTTXPAD4
B9_AVCCAUXRX7
B12_VTTXPAD7
B6_AVCCAUXTX9
B22_AVCCAUXTX4
B7_VTTXPAD9
B5_VTRXPAD9
B4_AVCCAUXRX9
C5_GNDA9
B18_VTTXPAD6
B17_AVCCAUXTX6
B16_VTRXPAD6
B15_AVCCAUXRX6
C16_GNDA6
B11_AVCCAUXTX7
B10_VTRXPAD7
C11_GNDA7
A23_TXNPAD4
A20_RXNPAD4A21_RXPPAD4
A18_TXNPAD6
A16_RXPPAD6
A12_TXNPAD7
A10_RXPPAD7A9_RXNPAD7
A11_TXPPAD7
A7_TXNPAD9
A5_RXPPAD9
MGT 4
MGT 6
MGT 7
MGT 9
(DIE DOWN)
V2P7_MGT_TOPFF672
GND_MGT
VCCA_MGT
VCCA_MGT
VCCA_MGT
VCCA_MGT
VTT_MGT
VTT_MGT
VTT_MGT
VTT_MGT
VTT_MGT
VTT_MGT
VTT_MGT
VTT_MGT
GND_MGT
GND_MGT
GND_MGT
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
All 0.22UF caps on this page are 0805.
ML300 CPU
V2P7 MGT Top
2VP7 MGT TopGigabit Ethernet Fiber
See Gigabit Ethernet Page (23)
22 55
1
2
0.22UFC0805
C143
2
1 C155
C08050.22UF
211000_OHM
FB121
IND_BLM21A
1 2
FB123
1000_OHM
IND_BLM21A
211000_OHM
FB122
IND_BLM21AVTT_TX6
AVCC_TX7
VTT_TX7
2
10.22UF
C0805
C145
1
2
C141
C08050.22UF
VTT_TX4
2
10.22UF
C0805
C152
2
1 C147
C08050.22UF
1
2
0.22UFC0805
C142
2
1 C146
C08050.22UF
2
1 C153
C08050.22UF
211000_OHM
FB129
IND_BLM21A
1 2
FB125
1000_OHM
IND_BLM21A
1 2
FB118
1000_OHM
IND_BLM21A
1 2
FB131
1000_OHM
IND_BLM21A
211000_OHM
FB127
IND_BLM21A
211000_OHM
FB120
IND_BLM21A
211000_OHM
FB130
IND_BLM21A
1 2
FB126
1000_OHM
IND_BLM21A
1 2
FB119
1000_OHM
IND_BLM21A
1
2
0.22UFC0805
C151 1
2
0.22UFC0805
C150
1 2
FB132
1000_OHM
IND_BLM21A
A23A22
A18A17
A16A15
A12A11
A10A9
A7A6
A5A4
A21A20
C22
B20
B21
B23
B9
B12
B6
B22
B7
B5
B4
C5
B18
B17
B16
B15
C16
B11
B10
C11
U1
XC2VP7-6FF672C
AVCC_TX4
211000_OHM
FB117
IND_BLM21A
2
1 C154
C08050.22UF
GIGE0_RX_P
1 2
FB124
1000_OHM
IND_BLM21A
VTT_RX9
AVCC_RX9
VTT_RX6
VTT_RX4
AVCC_TX6
1
2
0.22UFC0805
C140
211000_OHM
FB128
IND_BLM21A
2
1 C144
C08050.22UF
VTT_RX7
AVCC_TX9
VTT_TX9
1
2
C149
C08050.22UF
1
2
0.22UFC0805
C148
GIGE1_TX_N
GIGE2_TX_N
GIGE0_TX_N
GIGE3_TX_PGIGE3_TX_N
GIGE2_TX_P
GIGE1_TX_P
GIGE0_TX_P
GIGE3_RX_PGIGE3_RX_N
GIGE1_RX_NGIGE1_RX_P
GIGE2_RX_NGIGE2_RX_P
GIGE0_RX_N
AVCC_RX6
AVCC_RX4
AVCC_RX7
0402
0402
0402
0402
0402
0402
0402
GND_MGT
GND_MGT
GND_MGT
GND_MGT
VCC3V3
VCC3V3
0402
0402
VCC3V3
VCC3V3
0402
0402
VCC3V3
VCC3V3
0402
0402
VCC3V3
VCC3V3
R14K-ST11
TX0_D+TX0_GNDTX0_D-TX0_VCC
SD0TX0_DISRX0_D+
RX0_VCCRX0_D-
RX0_GND
TX3_D+TX3_GNDTX3_D-TX3_VCC
SD3TX3_DISRX3_D+
RX3_VCCRX3_D-
RX3_GND
RX2_GNDRX2_D-
RX2_VCCRX2_D+
TX2_DISSD2
TX2_VCCTX2_D-TX2_GNDTX2_D+
RX1_GNDRX1_D-
RX1_VCCRX1_D+
TX1_DISSD1
TX1_VCCTX1_D-
TX1_D+TX1_GND
SIGNAL=GND_MGT;41,42
01
23
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
GND_MGT
0402
0402
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
- track width XX mils- track spacing XX mils
BP
trace length, such thatGIGEX_XX_P + GIGEX_XX_CONN_P =
GIGEX_XX_N + GIGEX_XX_CONN_N
NOTES1. Each of the pairs must be matched
controlled differential impedance2. Each of the pairs must be 100 ohm
V2P7 MGT Top
Gigabit Ethernet Fiber TransceiverMGT Top
Fiber XCVR
4. TxVCC and RxVCC supply filtersdesigned to filter out 50KHz-100KHz
ML300 CPU
3. Put Caps on receive lines (RX)adjacent to the FPGA.
supply to R14K-ST11, a frequency ofof sensitivity for the R14K-ST11
5523
21
1210
47UH
FB139
21
1210
47UH
FB138
21
1210
47UH
FB137
21
1210
47UH
FB136
21
1210
47UH
FB135
21
1210
47UH
FB134
21
1210
47UH
FB133
1 2
FB140
47UH
1210
2
1 C18722UF
1206
1
2 120622UFC182
2
1 C18022UF
1206
GIGE0_TXVCC
GIGE2_RX_CONN_N
GIGE2_RX_CONN_P
GIGE2_TX_N
12
R147
180R
GIGE0_TX_P
GIGE1_TX_P
GIGE2_TX_P
GIGE3_TX_P
GIGE0_TX_N
GIGE1_TX_N
GIGE3_TX_N
GIGE3_RX_CONN_N
GIGE0_RXSD
GIGE1_RXSD
GIGE2_RXSD
GIGE3_RXSD1TP108
1TP107
1TP106
1TP1051
2
0.01UFC167
21
C1760.01UF
0402
1 2
0.01UFC177
0402
1 2
0.01UFC172
0402
21
C1730.01UF
040221
C1680.01UF
0402
1 2
0.01UFC169
0402
1 2
0.01UFC165
0402
21
C1640.01UF
0402
2
1 C1660.01UF
21
302928272625242322
31
403938373635343332
121314151617181920
11
10987654321
P102
GIGE0_RX_N
GIGE0_RX_P
GIGE0_RXVCC
GIGE3_TXVCC
GIGE3_RXVCC
GIGE0_TXVCC
GIGE1_TXVCC
GIGE1_RXVCC
GIGE2_TXVCC
GIGE2_RXVCC
2
1 C1570.01UF
1
2
0.01UFC156
1
2
0.01UFC159
2
1 C1580.01UF
2
1 C1610.01UF
1
2
0.01UFC160
GIGE0_RXVCC
GIGE1_TXVCC
GIGE1_RXVCC
GIGE2_TXVCC
GIGE2_RXVCC
GIGE3_TXVCC
GIGE3_RXVCC
GIGE3_RX_N
GIGE3_RX_P
GIGE1_RX_N
GIGE1_RX_P
GIGE2_RX_N
GIGE2_RX_P
GIGE0_RX_CONN_N
GIGE0_RX_CONN_P
12
180R
R1521
2
R153
180R
12
R150
180R1
2180R
R151
12
180R
R1481
2
R149
180R
GIGE1_RX_CONN_P
GIGE1_RX_CONN_N
GIGE3_RX_CONN_P
21
180R
R146
1
2 120622UFC181
2
1 C18322UF
1206
1
2 120622UFC184
2
1 C18522UF
1206
1
2 120622UFC186
GND_MGT
B
GND_MGT
A
GND_MGT
GND_MGT
GND_MGT
OUT
GND_3
GNDTABSENSE
SHDN
IN
D B
VCC3V3VCCA_MGT
VCC3V3VTT_MGT
SENSE/ADJ
SHDN GND_3
OUTIN
GNDNC
LT1963ES8
GND_MGT
0402
0402
FERRITE_BD
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
MGT Power
MGT VCCA Linear Regulator MGT VTT Linear Regulator
MGT Power Supplies
ML300 CPU
5524
1 2
FB141
2961666671
L1812
21487R
R166
121.00KR167
4 76
8 1
35
2
U3
NC
VTT_MGT_ADJ
2
1 C18833UF
1
2
C191100UF
6
2 4
31
5
U101
LT1963EQ-25
1
2
10UFC189
2
133UFC192
VCC2V5
AAA
A B
VCC1V5
VCC1V5
VCC2V5
VCC1V5
A A A A B
A A A
B
VCC2V5
A
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
Placed as near as possible to U1FPGA BULK CAPs
GB
V2P7 Bypass Capacitors
FPGA BULK CAPs
FPGA VCCO, VCCAUX CAPS, 1 per pinPlaced as near as possible to U1
FPGA VCORE CAPS, 1 per pinPlaced as near as possible to U1
FPGA 3.3V VCCO CAPS, 1 per pinPlaced as near as possible to U1
ML300 CPU V2P7
Bypass Capacitors
5525
2
1
C04020.1UFC733
1
2
C04020.1UFC734 VCC3_PCI
1
2
C7370.1UF
C0402
1
2
C7740.1UF
C0402
2
1
C7180.1UF
C0402
1
2
4.7UFC778
VCC3_PCI
2
147UFC787
2
1 C7774.7UF
1
2
4.7UFC776
2
1 C7754.7UF
1
2
47UFC789
2
1 C7864.7UF
1
2
4.7UFC785
2
1 C7844.7UF
1
2
4.7UFC783
2
1
C7080.1UF
C0402
2
1
C04020.1UFC707
2
1
C7060.1UF
C0402
2
1
C04020.1UFC705
2
1
C7040.1UF
C0402
2
1
C04020.1UFC703
2
1
C7020.1UF
C0402
2
1
C7010.1UF
C0402
1
2
C7150.1UF
C0402
1
2
C04020.1UFC714
1
2
C7130.1UF
C0402
1
2
C04020.1UFC712
1
2
C04020.1UFC711
1
2
C7100.1UF
C0402
1
2
C04020.1UFC709
2
1
C04020.1UFC717
2
1
C04020.1UFC716
2
1
C7320.1UF
C0402
2
1
C04020.1UFC731
2
1
C04020.1UFC730
2
1
C7290.1UF
C0402
2
1
C04020.1UFC728
2
1
C7270.1UF
C0402
1
2
C7260.1UF
C0402
1
2
C7250.1UF
C0402
1
2
C04020.1UFC724
1
2
C7230.1UF
C0402
1
2
C04020.1UFC722
1
2
C7210.1UF
C0402
1
2
C04020.1UFC720
1
2
C7190.1UF
C0402
2
1
C7500.1UF
C0402
2
1
C04020.1UFC749
2
1
C7480.1UF
C0402
2
1
C04020.1UFC747
2
1
C7460.1UF
C0402
2
1
C04020.1UFC745
2
1
C7440.1UF
C0402
2
1
C7430.1UF
C0402
1
2
C7420.1UF
C0402
1
2
C04020.1UFC741
1
2
C7400.1UF
C0402
1
2
C04020.1UFC739
1
2
C04020.1UFC738
1
2
C04020.1UFC736
2
1
C04020.1UFC735
1
2
C7730.1UF
C0402
1
2
C04020.1UFC772
1
2
C7710.1UF
C0402
1
2
C04020.1UFC770
1
2
C7690.1UF
C0402
1
2
C04020.1UFC768
1
2
C7670.1UF
C0402
2
1
C7660.1UF
C0402
2
1
C04020.1UFC765
2
1
C7640.1UF
C0402
2
1
C04020.1UFC763
2
1
C7620.1UF
C0402
2
1
C04020.1UFC761
2
1
C7600.1UF
C0402
2
1
C7590.1UF
C0402
1
2
C7580.1UF
C0402
1
2
C04020.1UFC757
1
2
C7560.1UF
C0402
1
2
C04020.1UFC755
1
2
C04020.1UFC754
1
2
C7530.1UF
C0402
1
2
C04020.1UFC752
2
1
C04020.1UFC751
2
1 C78847UF
1
2
4.7UFC781
2
1 C7794.7UF
1
2
4.7UFC780
2
14.7UFC1012
VCC3V3
0402
0402
VCC2V5
0402
0402
0402
0402
VCC2V5
0402
VCC2V5
VCC2V5
VCC2V5
0402
TSSOP16
Y1
B2Y2
B3Y3
Y4B4
A4
A3
A2
OE
B1
GND
VCC
A/B
A1
0
1
0
1
0
1
0
1
MICTOR 38
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
Trace + Debug
BP
and the Mictor 38:
CPU Debug and Trace
SYSACE_TST Signals convertedto 3.3V using TFT signal
V2P7 Bank 5/6 (17/18)
Level shifter on page 44
ML300 CPU
1. Bussed to include the 2X8 header above.These are the CPU Debug and should be +/- 1250 milsThe Header should be located between the Mictorand FPGA, so the FPGA and Mictor are the endpoints
These are the CPU Trace and should be +/- 50 mils2. Only connected to the Mictor and FPGA.
All matched trace length +/1 1250 milsThere are two sets of signals between the FPGA
Mark Pin 1
Mark Pin 1
Class attribute on TRC_CLK
Mark Pin 1
Silkscreen:
Pin 14 must be removed.
OFF - Trace JTAGON - PC4 JTAG
J204:
All matched trace length +/1 50 mils
FPGA
P114
Mictor(P109)
26 55
038036034032030028026024022020018
014016
012010008006004002
037035033031
025027029
023021019017015013011009007005003001
P109
MTR_038_PLUG_SM
13
12 11
9
7
12
3
56
4
8
10
14
P115
HDR_2X7_2MM
4
67
109
1213
14
11
5
1
15
2
3
8
16
U60
74LVC157A
TRC_CLK
CPU_TRST
CPU_HALT_N
TS1O
21
4.70K
R221
0402
210R
R226
12J204
HDR_1X2_RA
TRC_VSENSE
12
R222
10.0K
2110.0K
R223
12
R224
10.0K
2110.0K
R225
12
R170
10.0K
15
13
1211
9
7
1 2
3
5 6
4
8
10
14
16
P114
HDR_2X8_RA
214.70K
R260
CPU_VCC
1 20RR227
CPU_TRST
CPU_TDICPU_TMSCPU_TCK
CPU_TDO
TS2OTS1ETS2ETS3TS4TS5TS6
CPU_HALT_N
CPU_TMS
CPU_TCK
CPU_TDI
CPU_TDO
PC4_TDI
PC4_TCK
SYSACE_TSTTDO
NC
NC
PC4_TMS
SYSACE_TSTTCK_2V5
SYSACE_TSTTMS_2V5
SYSACE_TSTTDI_2V5
PC4_TMS
PC4_TCK
PC4_TDI
SYSACE_TSTTDO
JTAG_SRC_SELECT
CPU_TMS
CPU_TCK
CPU_TDI
CPU_TDOCPU_TDO_TMP
0402
0402
VCC2V5VCC2V5
VCC2V5
VCC2V5
A
VCC3V3
VCC3V3
VCC2V5
VCC2V5
0402
0402
0402
A
VCC2V5
0402
VCC3V3
VCC3V3
PARTS=1LEVEL=STD
CFD08CFD02CFD09
VCCL_15
MPIRQMPCEMPA06MPA05MPA04MPD15MPD14MPD13MPD12MPD11MPD10MPD09MPD08MPD07MPD06MPD05MPD04MPD03MPD02MPD01MPD00MPA03MPA02MPA01MPA00MPWEMPOE
CFGINIT
CFGPROG
CFGTCK
CFGTDI
CFGTDO
CFGTMS
CFGADDR0
CFGADDR1
CFGADDR2
CLK
STATLED
ERRLED
TSTTDO
TSTTMS
TSTTCK
TSTTDI
CFA07
CFA05
CFWAITCFA02
73_VCCH
92_VCCH
91_GND
100_GND
75_GND
83_GND
64_GND
54_GND
46_GND
GND_120
GND_136
GND_129
GND_144
GND_9
GND_18
GND_26
VCCL_25
MPBRDY
VCCH_109
VCCH_1
VCCL_10
57_VCCL
99_VCCL
94_VCCL
84_VCCL
VCCH_17
55_VCCH
37_VCCH
VCCH_128
CFCD2CFD10
CFCD1CFD03CFD11CFD04CFD12CFD05CFD13CFD06CFD14CFD07CFD15CFCE1CFCE2CFA10
CFD01
CFA00
CFOECFA09CFA08CFWE
CFA06
CFA03
CFREGCFA01
CFD00
CFA04
CFGRSVD
GND_111
CFGMODEPIN
POR_RESET
POR_TEST
GND_35
VCCL_126
RESET_N
POR_BYPASS
GND_110
GND_112
(DIE DOWN)TQFP144SYSTEMACE
3_D0427_D112_D03
49_D1048_D0923_D0247_D0822_D01
20_A0044_REG19_A0118_A0242_WAIT17_A0316_A0415_A0514_A0637_RDY/BSY12_A0736_WE11_A0810_A099_OEI8_A1032_CE27_CE1I31_D156_D0730_D145_D0629_D134_D0528_D12
50_GND
38_VCC13_VCC
46_BVD1
21_D00
45_BVD240_VS2
26_CD1
25_CD2
41_RESET39_CSEL
35_IOWR34_IORD
33_VS124_WP
43_INPACK
1_GND
SHIELD
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
V2P7 Bank 5 (17)
to Power Board
BP
System ACE
System ACESilkscreen"System ACE""Status LED"
Place these
as possible
resistors
System ACEas close to
Silkscreen"System ACE""Error LED"
ML300 CPU
NOTE: See Page 35 formounting locations ofDS201, DS202 and DS203
MUX, thento JTAG andTrace Conns
To LevelShifter and
(Init Signal)
From Power Board
to FPGA
27 55
SYSACE_TSTTDO
SYSACE_TSTTMS_3V3
SYSACE_TSTTCK_3V3
SYSACE_TSTTDI_3V3
3272
4948234722
204419184217161514371236111098
327
316
305
294
28
150
3813
46
21
4540
26
25
4139
3534
332443
52
51
P113
ACEFLASH
7811
15
414243444547484950515253565859606162636566676869707677
787980818285868788
9395969798
101
102
132
135
140141
73
92
91
100
7583645446
120
136
129
14491826
25
39
1091
10
57
99
94
84
17
55
37
128
1312
103104105106107113114115116117118119138121
6
4
123125130131
134
139
3142
5
137
133
111
89
72
74
35
126
33
108
110
112
U2
TQFP144DEVICE=XCCACE-TQ144I
FPGA_TMSFPGA_TDIFPGA_TDOFPGA_TCKFPGA_PROG_B
SYSACE_CFGADDR2
SYSACE_CFGADDR1
SYSACE_CFGADDR0
SYSACE_MPDE
2
1
0.1UF0402
C215
2
1
C216
04020.1UF
12
1.00KR214
0402
12
1.00KR216
0402
12
R215
1.00K
0402
12
1.00KR213
0402
12
R218
4.70K
0402
21DS201
RED
21DS202
GREEN
12
4.70K
R210
0402
12
R211
4.70K
0402
12
4.70K
R209
0402
12
4.70K
R212
0402
12R
ED
DS203
LED0603
12
R208
4.70K
0402
SYSACE_CFGMODEPIN
FPGA_INIT_LED
TFT_FPGA_HSYNC
1 2
R21925.5R
2
1
C219
04020.1UF
2
1
0.1UF0402
C220
2
1
0.1UF0402
C218
2
1
C217
04020.1UF
1
2
10UFC2312
1
C224
04020.1UF
SYSACE_CFDE
SYSACE_CFA00SYSACE_CFD00
SYSACE_CFD10
SYSACE_CFA10
SYSACE_CFD05
SYSACE_CFD01
SYSACE_CFA06
SYSACE_CFCD2
SYSACE_MPA04
SYSACE_MPA00
SYSACE_MPD10
SYSACE_MPD00
SYSACE_MPD05
SYSACE_MPA01
SYSACE_MPA03
SYSACE_MPD07SYSACE_MPD08SYSACE_MPD09
SYSACE_MPD11SYSACE_MPD12SYSACE_MPD13SYSACE_MPD14SYSACE_MPD15
SYSACE_MPA05SYSACE_MPA06SYSACE_MPCESYSACE_MPIRQSYSACE_MPBRDY
SYSACE_STATLED
SYSACE_ERRLED
SYSACE_RESET_N
21100R
R266
SYSACE_CLK
1 2
51.1RR220
12
R265
100R
1 TP218
1 TP217
1 TP220
1 TP219
1 TP2151 TP216SYSACE_CFRDBSY
1
TP221
1TP214
2
1 C23010UF
2
1
0.1UF0402
C227
2
1
C228
04020.1UF
2
1
C229
04020.1UF
2
1
C226
04020.1UF
2
1
0.1UF0402
C225
2
1
0.1UF0402
C223
2
1
0.1UF0402
C222
2
1
C221
04020.1UF
SYSACE_MPD01
SYSACE_MPA02
SYSACE_MPWE
SYSACE_CFD09SYSACE_CFD02SYSACE_CFD08
SYSACE_CFREGSYSACE_CFA01SYSACE_CFA02SYSACE_CFWAITSYSACE_CFA03SYSACE_CFA04SYSACE_CFA05
SYSACE_CFA07SYSACE_CFWESYSACE_CFA08SYSACE_CFA09
SYSACE_CFCE2SYSACE_CFCE1SYSACE_CFD15SYSACE_CFD07SYSACE_CFD14SYSACE_CFD06SYSACE_CFD13
SYSACE_CFD12SYSACE_CFD04
SYSACE_CFD03SYSACE_CFCD1
SYSACE_CFD11
SYSACE_MPD06
SYSACE_MPD04SYSACE_MPD03SYSACE_MPD02
12
R2174.70K
12
R268
56.2R
VCC2V5
VCC2V5
VTTDDR
VTTDDR
VTTDDR
A
VCC2V5
VCC2V5
0402
0402
0402
0402
LEVEL=STD
TSSOP48PARTS=1
1_GND2_Y03_Y04_VDDQ5_Y16_Y17_GND8_GND9_Y210_Y211_VDDQ12_VDDQ13_CLK14_CLK15_VDDQ16_AVDD17_AGND18_GND19_Y320_Y321_VDDQ22_Y423_Y424_GND GND_25
Y9_26Y9_27
VDDQ_28Y8_29Y8_30
GND_31FBOUT_32FBOUT_33VDDQ_34FBIN_35FBIN_36
PWRDWN_37VDDQ_38
Y7_39Y7_40
GND_41GND_42Y6_43Y6_44
VDDQ_45Y5_46Y5_47
GND_48
CDCV857TSSOP48
0402
0402
CTCB1210-600-SSM
CTCB1210-600-SSM
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
The VCC DRR Bypass caps should be placed with oneadjacent to each of the pwr/gnd pins on the CDCV857
Resistors R304 and R305 should beplaced close to U16.35 and U16.36
DDR SDRAM - Clock PLL
placed close to U16.32 and U16.33
All of the CLK pairs should be match tracelength
placed adjacent to FB310 and FB302These Bypass caps should be
ML300 CPUPlace C357 nearVCC_DDRA andGND_VCCA on U16
Resistors R301 and R302 should be
Place C353 Adjacent toR304 and R305
DDR Clock Replicator
DDR_CLK_PLL Class on DDR_PLL_CK0, 3 and 6
signals to FPGASee diagram on Page 17 for routing of clock
5528
1 2
FB302
L1210
21
FB301
L1210
2
1 04020.1UFC357
DDR_PLL_FB_IN_N
1 2
R30622.1R
2122.1RR301
DDR_PLL_FB_OUT_N
DDR_PLL_FB_IN
DDR_PLL_FB_OUT
1
2C3530.1UF
0402
123456789101112131415161718192021222324 25
2627282930313233343536373839404142434445464748
U16
CDCV857DGGR
DDR_RES_CK_NDDR_RES_CK
DDR_PLL_CK6_NDDR_PLL_CK6
DDR_PLL_CK3_N
DDR_PLL_CK0_N
DDR_PLL_CK2DDR_PLL_CK2_N
12
R303
49.9R
2149.9R
R302
2149.9R
R304
12
R305
49.9R
2
1 04020.1UFC363
2
1 04020.1UFC358
2
1 C35622UF
DDR_PLL_CK4DDR_PLL_CK4_N
DDR_PLL_CK0
DDR_PLL_CK1_NDDR_PLL_CK1
DDR_PLL_CK5DDR_PLL_CK5_N
DDR_PLL_CK7DDR_PLL_CK7_N
DDR_PLL_CK8DDR_PLL_CK8_N
DDR_PLL_CK3
DDR_PLL_CK9_NDDR_PLL_CK9
VCC_DDRAGND_DDRA
1
2C3590.1UF
0402
2
1 04020.1UFC360
1
2C3610.1UF
0402
2
1 04020.1UFC365
1
2C3640.1UF
04021
2C3620.1UF
0402
2
1 04020.1UFC354
1
2C3550.1UF
0402
VCC_DDRA
GND_DDRA
VCC2V5
VCC2V5
VCC2V5
VCC2V5VCC2V5
VCC2V5
VCC2V5
VTTDDR
CTS742
CTS742
CTS742
VTTDDR
VCC2V5
CTS742
PARTS=1LEVEL=STD
TVSOP48
Q1Q2Q3Q4
Q6Q7
GND_13
Q8Q9
GND_17
Q10Q11Q12
GND_22
D14
D12D11D10
CLKCLK_N
D7D6
D4D3
VDD_45
D2D1
D13
Q5D5
Q14Q13
D8D9
VDD_37
VDDQ_4VDDQ_9
GNDGND_8
VDDQ_12VDDQ_16VDDQ_21
GND_27GND_36
VDD_28
GND_46
RST_N
VREF
SSTV16857TVSOP48
A
A
EXB-E10C
EXB-E10C
EXB-E10C
PARTS=1LEVEL=STD
TVSOP48
Q1Q2Q3Q4
Q6Q7
GND_13
Q8Q9
GND_17
Q10Q11Q12
GND_22
D14
D12D11D10
CLKCLK_N
D7D6
D4D3
VDD_45
D2D1
D13
Q5D5
Q14Q13
D8D9
VDD_37
VDDQ_4VDDQ_9
GNDGND_8
VDDQ_12VDDQ_16VDDQ_21
GND_27GND_36
VDD_28
GND_46
RST_N
VREF
SSTV16857TVSOP48
CTS742
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
see page 56, Classes 1-8.
3. Series and Parallel termination resistorson this page should be placed as close as
BP
DDR_CNTL_REG Class on DDR_REG_WE_NDDR_CNTL_FPGA Class on DDR_RES_WE_N
DDR SDRAM - Registers
NEED TO CHANGE DDR_REG_WE_NSO ATTRIBUTE IS "CLASS" NOT "DDR"
DDR_ADDR_REG Class on DDR_REG_A00 and A07DDR_ADDR_FPGA Class on DDR_RES_A00 and A07
Registers for DDR SDRAM
ML300 CPU
V2P7 Bank 6/7 (18/19)
on page 31.
NOTES:1. All Traces are 50 ohm Controlled impedance.
possible to the DDR chips.
pins of both of the SSTV16859.
2. Termination Rs to DDR componenets are shown on
4. the 0.1UF caps should be placed at each VCC
5. For details of tracelengths control,
29 56
4321
5678
22RRP362
1256
1011
13
1415
17
181920
22
25
293031
3839
4041
4344
45
4748
26
742
2423
3332
37
49
38
121621
2736
28
46
34
35
U14
SN74SSTV16857DGVR
8 9
10
432 57
1 647RRP329
8 9
10432 57
1 647RRP331
89
10 4 3 25 7
16
RP33047R
2
1 04020.1UFC341
2
1 04020.1UFC343
1
2C3420.1UF
0402
2
1 04020.1UFC345
1
2C3470.1UF
0402
2
1 04020.1UFC348
1
2C3490.1UF
0402
1
2C3440.1UF
0402
1
2
10UFC352
2
1 C34610UF
1256
1011
13
1415
17
181920
22
25
293031
3839
4041
4344
45
4748
26
742
2423
3332
37
49
38
121621
2736
28
46
34
35
U15
SN74SSTV16857DGVR
DDR_RES_A06DDR_RES_A05
NC
NC
DDR_REG_A06
DDR_REG_A00
DDR_REG_WE_N
DDR_MEM_CK5DDR_MEM_CK5_N
DDR_RES_WE_NDDR_FPGA_WE_N
DDR_FPGA_A12
DDR_FPGA_A07
DDR_FPGA_A04
DDR_FPGA_A06
DDR_RES_A00
DDR_FPGA_A00
8765
1234
RP36322R
DDR_RES_A04
DDR_RES_A12
DDR_RES_A03
8765
1234
RP36122R
DDR_RES_A08DDR_RES_A09
4321
5678
22RRP360
8765
1234
RP35922R
DDR_MEM_CK4
DDR_RES_A07
DDR_RES_A01
DDR_REG_BA0DDR_REG_CS_N
DDR_RES_CS_N
DDR_REG_CAS_NDDR_REG_BA1
DDR_RES_RAS_NDDR_REG_CKEDDR_REG_RAS_N
VREF_DDR
DDR_REG_A12DDR_REG_A11DDR_REG_A10DDR_REG_A09DDR_REG_A08DDR_REG_A07
DDR_REG_A05DDR_REG_A04
DDR_REG_A02DDR_REG_A01
DDR_RES_A11DDR_RES_A10
DDR_RES_A02
DDR_REG_A03
VREF_DDR
DDR_RES_CAS_N
DDR_RES_CKE
DDR_RES_BA1
DDR_RES_BA0
DDR_MEM_CK4_N
DDR_FPGA_RAS_NDDR_FPGA_CAS_N
DDR_FPGA_CKE
DDR_FPGA_BA1
DDR_FPGA_CS_NDDR_FPGA_BA0
DDR_FPGA_A08
DDR_FPGA_A01
DDR_FPGA_A11DDR_FPGA_A10DDR_FPGA_A09
DDR_FPGA_A03DDR_FPGA_A02
DDR_FPGA_A05
1
2C3510.1UF
0402
2
1 04020.1UFC350
NCNCNCNCNC
NC
VTTDDRVTTDDRVTTDDR
CTS742
VTTDDR
DQ4
DQ6DQ5
DQ7
A12
CK
VREF
BA1
BA0
WE
DQ1DQ2
A0
A3
A1
A2 A4
A5
A6
AP/A10
A7
A8
A9
A11
DQS
CAS
RAS
CS
CKE
CK
DM
DQ0
DQ3
MT46V32M8
DQ4
DQ6DQ5
DQ7
A12
CK
VREF
BA1
BA0
WE
DQ1DQ2
A0
A3
A1
A2 A4
A5
A6
AP/A10
A7
A8
A9
A11
DQS
CAS
RAS
CS
CKE
CK
DM
DQ0
DQ3
MT46V32M8
DQ4
DQ6DQ5
DQ7
A12
CK
VREF
BA1
BA0
WE
DQ1DQ2
A0
A3
A1
A2 A4
A5
A6
AP/A10
A7
A8
A9
A11
DQS
CAS
RAS
CS
CKE
CK
DM
DQ0
DQ3
MT46V32M8
DQ4
DQ6DQ5
DQ7
A12
CK
VREF
BA1
BA0
WE
DQ1DQ2
A0
A3
A1
A2 A4
A5
A6
AP/A10
A7
A8
A9
A11
DQS
CAS
RAS
CS
CKE
CK
DM
DQ0
DQ3
MT46V32M8
CTS742
CTS742
CTS742
CTS742
EXB-E10C
EXB-E10C
EXB-E10C
EXB-E10C
CTS742
CTS742
CTS742
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
DDR SDRAM - Components
Silkscreen: "DDR SDRAM - 4 of 8x32M"
DDR SDRAM Chips
ML300 CPU
V2P7 Bank 6/7 (18/19)
1. All Traces are 50 ohm Controlled impedance.
3. Series and Parallel termination resistorson this page should be placed as close aspossible to the DDR chips.
4. See page 34 for placement of bypass caps
5. Rest of Data path termination Rs shown on page 32
NOTES:
see page 56, Classes 1-8.2. For details of tracelengths control,
5630
4321
5678
22R
RP356
8 7 6 5
1 2 3 4RP353
22R
8 7 6 5
1 2 3 4RP347
22R
8
9
10
4
3
2
5
7
1
6
47R
RP352
6
1
7
5
2
3
4
10
9
8
RP355
47R
8
9
10
4
3
2
5
7
1
6
47R
RP358
6
1
7
5
2
3
4
10
9
8
RP349
47R
8 7 6 5
1 2 3 4 RP357
22R
4321
5678
22R
RP354
8 7 6 5
1 2 3 4 RP351
22R
4321
5678
22R
RP348
DDR_RES_DQ08
11
2
47
45
44
24
23
22
51
41
40
39
38
2837
36
35
31
30
32
29
8
5
21
26
27
49
46
42
65
59
62
56
U9
HYB25D256800AT-7
56
62
59
65
42
46
49
27
26
21
5
8
29
32
30
31 35
36
37
2838
39
40
41
51
22
23
24
44
45
47
2
11
U8
HYB25D256800AT-7
11
2
47
45
44
24
23
22
51
41
40
39
38
2837
36
35
31
30
32
29
8
5
21
26
27
49
46
42
65
59
62
56
U7
HYB25D256800AT-7
56
62
59
65
42
46
49
27
26
21
5
8
29
32
30
31 35
36
37
2838
39
40
41
51
22
23
24
44
45
47
2
11
U6
HYB25D256800AT-7
DDR_MEM_WE_N
DDR_MEM_DQS0
DDR_MEM_DM0
DDR_RES_DQ00
DDR_MEM_DQ00
DDR_MEM_CK1
DDR_MEM_CKE
DDR_MEM_WE_N
DDR_MEM_BA1
4321
5678
22R
RP350
DDR_MEM_A11
DDR_MEM_DQ02
DDR_MEM_DQ03
DDR_MEM_DQ01
DDR_MEM_DQ04
DDR_MEM_DQ05
DDR_MEM_DQ06
DDR_RES_DQ16
DDR_RES_DQ31
DDR_RES_DQ30
DDR_RES_DQ29
DDR_RES_DQ28
DDR_RES_DQ27
DDR_RES_DQ26
DDR_RES_DQ25
DDR_RES_DQ24
DDR_MEM_DQ24
DDR_MEM_DQ26
DDR_MEM_DQ25
DDR_MEM_DQ27
DDR_MEM_DQ28
DDR_MEM_DQ29
DDR_MEM_DQ30
DDR_MEM_DQ31
DDR_MEM_A00
DDR_MEM_DM1
DDR_MEM_DQ08
DDR_MEM_CK1_N
DDR_MEM_DQ12
DDR_MEM_DQ13
DDR_MEM_DQ14
DDR_MEM_DQ15
DDR_MEM_A08
DDR_MEM_RAS_N
DDR_MEM_CKE
DDR_MEM_CAS_N
DDR_MEM_CK3
DDR_MEM_BA0
DDR_MEM_BA1
DDR_MEM_WE_N
DDR_MEM_CS_N
DDR_MEM_CK2_N
DDR_MEM_CK2
DDR_MEM_BA1
DDR_MEM_BA0
DDR_MEM_CS_N
DDR_MEM_RAS_N
DDR_MEM_CAS_N
DDR_MEM_BA1
DDR_MEM_BA0
DDR_MEM_CS_N
DDR_MEM_RAS_N
DDR_MEM_CAS_N
DDR_MEM_DQS1
DDR_MEM_DM2
DDR_MEM_WE_N
DDR_MEM_DM3
DDR_MEM_DQS3
DDR_MEM_CK3_N
DDR_MEM_DQS2
DDR_MEM_CKE
DDR_MEM_A09
DDR_MEM_A10
DDR_MEM_A12
DDR_MEM_A11
DDR_MEM_A01
DDR_MEM_A02
DDR_MEM_A03
DDR_MEM_A04
DDR_MEM_A05
DDR_MEM_A06
DDR_MEM_A07
DDR_MEM_A08
DDR_MEM_A09
DDR_MEM_A10
DDR_MEM_A11
DDR_MEM_A12
DDR_MEM_A00
DDR_MEM_A01
DDR_MEM_A02
DDR_MEM_A03
DDR_MEM_A04
DDR_MEM_A05
DDR_MEM_A06
DDR_MEM_A07
DDR_MEM_A08
DDR_MEM_A09
DDR_MEM_A10
DDR_MEM_A11
DDR_MEM_A12
DDR_MEM_A00
DDR_MEM_A01
DDR_MEM_A02
DDR_MEM_A03
DDR_MEM_A04
DDR_MEM_A05
DDR_MEM_A06
DDR_MEM_A07
VREF_DDR
VREF_DDR
VREF_DDR
DDR_MEM_DQ09
DDR_MEM_DQ10
DDR_MEM_DQ11
DDR_RES_DQ15
DDR_RES_DQ14
DDR_RES_DQ12
DDR_RES_DQ09
DDR_RES_DQ10
DDR_RES_DQ11
DDR_RES_DQ13
DDR_RES_DQ21
DDR_RES_DQ19
DDR_RES_DQ18
DDR_RES_DQ17
DDR_RES_DQ20
DDR_RES_DQ22
DDR_RES_DQ23
DDR_MEM_DQ19
DDR_MEM_DQ18
DDR_MEM_DQ17
DDR_MEM_DQ22
DDR_MEM_DQ21
DDR_MEM_DQ20
DDR_MEM_DQ16
DDR_RES_DQ05
DDR_RES_DQ03
DDR_RES_DQ02
DDR_RES_DQ01
DDR_RES_DQ04
DDR_RES_DQ06
DDR_RES_DQ07
VREF_DDR
DDR_MEM_A10
DDR_MEM_A09
DDR_MEM_A08
DDR_MEM_A06
DDR_MEM_A05
DDR_MEM_A04
DDR_MEM_A03
DDR_MEM_A02
DDR_MEM_A01
DDR_MEM_CK0_N
DDR_MEM_CKE
DDR_MEM_BA0
DDR_MEM_CS_N
DDR_MEM_RAS_N
DDR_MEM_CAS_N
DDR_MEM_CK0
DDR_MEM_DQ07
DDR_MEM_A12
DDR_MEM_A00
DDR_MEM_A07
DDR_MEM_DQ23
0402
VTTDDR
CTS742
CTS742
VTTDDR
CTS742
CTS742
CTS742
EXB-E10C
EXB-E10C
EXB-E10C
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
see page 56, Classes 1-8.
NOTES:
BP
DDR SDRAM - Termination (1 of 2)
ML300 CPU
From Registers to Chips
DDR Termination for DDR SDRAM
1. Series termination resistors on this page
2. Parallel termination resistors on this page
should be placed as close as possible tothe DDR registers (U14 and U15)
should be placed after the DDR chipsrelative to the DDR registers.
3. For details of tracelengths control,
31 56
DDR_REG_A00
DDR_MEM_A00
8 9 10
432 57
1 647RRP336
8910
4 3 25 7
16 47RRP338
61
7 52 3 4 10
98
RP33947R
8765
1234
RP31122R
4321
5678
22RRP308
4321
5678
22RRP303
NC
NC
NC
8765
1234
RP30222R
8765
1234
RP30422R
DDR_REG_A08
DDR_REG_A09DDR_REG_A10DDR_REG_A11DDR_REG_A12
DDR_REG_A02DDR_REG_A03DDR_REG_A04
DDR_REG_A05DDR_REG_A06DDR_REG_A07
DDR_MEM_A04DDR_MEM_A03DDR_MEM_A02
DDR_REG_BA1
DDR_REG_RAS_NDDR_REG_CAS_N
DDR_REG_WE_NDDR_REG_CS_NDDR_REG_BA0
DDR_REG_CKE
NC
DDR_MEM_BA1
DDR_MEM_RAS_NDDR_MEM_CAS_N
DDR_MEM_BA0DDR_MEM_CS_N
DDR_MEM_CKE
DDR_MEM_WE_N
DDR_MEM_A05DDR_MEM_A06DDR_MEM_A07DDR_MEM_A08
DDR_MEM_A09DDR_MEM_A10DDR_MEM_A11DDR_MEM_A12
2122.1RR319
DDR_MEM_A01DDR_REG_A01
VTTDDR
0402
0402
0402
VTTDDR
0402
VTTDDR
VTTDDR
VTTDDR
CTS742
CTS742
VTTDDR
VTTDDR
CTS742 CTS742
CTS742
CTS742
CTS742
CTS742
CTS742
CTS742
CTS742
0402
VTTDDR
EXB-E10C
EXB-E10C
EXB-E10C
EXB-E10C
EXB-E10C
EXB-E10C
EXB-E10C
CTS742
0402
0402
0402
CTS742
CTS742
CTS742
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
be after end compThese resistors should
be close to the FPGAThese resistors should
be close to the FPGAThese resistors should
BP
Silkscreen:
DDR_DATA_FPGA Class is onDDR_FPGA_DQ00,04,08,12,16,20,24,28 and DM0
DDR_CLK_MEM Class is on DDR_MEM_CK0, 2, 4, and 6DDR_CNTL_FPGA (DQS0-DQS3) Class is on DDR_FPGA_DQS0
DDR SDRAM - Termination (2 of 2)
"DDR_CLK"
"DDR_CLK_N"
These resistors shouldbe close to the PLL (U16)
be after end compThese resistors should
These resistors shouldbe after end comp
These resistors shouldbe close to the FPGA
VTT Term at Registers
ML300 CPU
DDR Termination
5532
DDR_MEM_DM0DDR_FPGA_DM0
4321
5678
22RRP324
8765
1234
RP32622R
4321
5678
22RRP327
DDR_RES_DQS31 2
R31422.1R
DDR_MEM_DQS12122.1RR312
DDR_RES_DQS1
2149.9R
R316
4321
5678
22RRP322
61
7 52 3 4 10
98
RP34047R
8910
4 3 25 7
16 47RRP341
8 9
10432 57
1 6
47RRP365
8910
4 3 25 7
16 47RRP345
61
7 52 3 4 10
98
RP34447R
6 1
75 23410
9 8
RP34647R
8 9 10
432 57
1 647RRP603
DDR_RES_DQ00DDR_FPGA_DQ00
DDR_MEM_DQS2
DDR_MEM_CK4
DDR_MEM_DQS3
DDR_MEM_DM3
DDR_MEM_DM2DDR_RES_DQS2
DDR_MEM_CK2
DDR_FPGA_DQS0
DDR_MEM_CK0
DDR_FPGA_DQS3DDR_FPGA_DM3DDR_FPGA_DQS2DDR_FPGA_DM2
DDR_PLL_CK2
DDR_FPGA_DQS1DDR_FPGA_DM1 DDR_MEM_DM1
DDR_MEM_CK1_NDDR_MEM_CK1DDR_MEM_CK0_N
DDR_PLL_CK5_NDDR_PLL_CK5DDR_PLL_CK4_NDDR_PLL_CK4
DDR_PLL_CK1_NDDR_PLL_CK1DDR_PLL_CK0_NDDR_PLL_CK0
DDR_RES_DQ28
DDR_RES_DQ24
DDR_RES_DQ20
DDR_RES_DQ16
DDR_RES_DQ12
DDR_RES_DQ08
DDR_RES_DQ04
DDR_FPGA_DQ28
1 2
R31122.1R
DDR_MEM_CK68765
1234
RP32322R
DDR_PLL_CK6
4321
5678
22RRP328
DDR_FPGA_DQ24
DDR_FPGA_DQ20
DDR_FPGA_DQ16
DDR_FPGA_DQ12
DDR_FPGA_DQ08
DDR_FPGA_DQ04
1 TP301
1 TP302
DDR_MEM_CK4_N
4321
5678
22RRP332
8765
1234
RP31622R
4321
5678
22RRP317
4321
5678
22RRP318
8765
1234
RP32022R
8765
1234
RP32522R
8765
1234
RP31922R
4321
5678
22RRP321
8765
1234
RP31522R
DDR_PLL_CK6_NDDR_PLL_CK7DDR_PLL_CK7_N
DDR_RES_DQ25DDR_RES_DQ26DDR_RES_DQ27
DDR_RES_DQ29DDR_RES_DQ30DDR_RES_DQ31
DDR_RES_DQ22
DDR_RES_DQ17DDR_RES_DQ18DDR_RES_DQ19
DDR_RES_DQ21
DDR_RES_DQ23
DDR_RES_DQ07
DDR_RES_DQ05
DDR_RES_DQ03DDR_RES_DQ02DDR_RES_DQ01
DDR_RES_DQ06
DDR_RES_DQ15DDR_RES_DQ14DDR_RES_DQ13
DDR_RES_DQ11DDR_RES_DQ10DDR_RES_DQ09
DDR_MEM_CK3_NDDR_MEM_CK3DDR_MEM_CK2_N
DDR_FPGA_DQ31DDR_FPGA_DQ30DDR_FPGA_DQ29
DDR_FPGA_DQ23DDR_FPGA_DQ22DDR_FPGA_DQ21
DDR_FPGA_DQ17DDR_FPGA_DQ18
DDR_FPGA_DQ25DDR_FPGA_DQ26
DDR_FPGA_DQ19
DDR_FPGA_DQ27
DDR_FPGA_DQ11DDR_FPGA_DQ10DDR_FPGA_DQ09
DDR_FPGA_DQ03DDR_FPGA_DQ02DDR_FPGA_DQ01
DDR_FPGA_DQ06DDR_FPGA_DQ05
DDR_FPGA_DQ07
DDR_FPGA_DQ13DDR_FPGA_DQ14DDR_FPGA_DQ15
DDR_PLL_CK9_NDDR_PLL_CK9DDR_PLL_CK8_NDDR_PLL_CK8
DDR_MEM_CK5_NDDR_MEM_CK5
DDR_MEM_CK9_NDDR_MEM_CK9DDR_MEM_CK8_NDDR_MEM_CK8
DDR_MEM_CK7_NDDR_MEM_CK7DDR_MEM_CK6_N
DDR_PLL_CK3DDR_PLL_CK3_N
DDR_PLL_CK2_N
21
22.1RR313
12
R315
49.9R
2149.9R
R317
12
R318
49.9R
DDR_RES_DQS0 DDR_MEM_DQS0
0402
DD
D
VTTDDR
VDD_1PVDD1VL1PGND1PGND2VL2PVDD2DGND VDD_2
VFBVREFIN
SHDNAGND
VREFOUTVCCQAVCC
REGULATORML6554CU
VCC2V5
DD
VCC3V3
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
Voltage Regulator for DDR SDRAM
DDR VTT & VREF
DDR Regulator
ML300 CPU
Thick Trace
5533
2
1 C1005
04020.1UF
2
1 C1004
04020.1UF
VREF_DDR
1
2
0.1UF0402
C1011
1
TP1003
21
L1001
3.3UH
DO3316
1 21000PF
0402
C1010
1 2
R1005
0402
100K
21100RR1004
21
0402
R1002100K
21
C1006
040230PF
NC
1
TP1001
2
1220UFC1001 1
2
220UFC1002
12345678
161514131211109
U1001
ML6554CU
2
1 C1003220UF
1
2
C1008220UF
1
2
C1009220UF
1 2
R1001
0402
1.00K
1 2
30PF0402
C1007
1 2
R1003100R
VTTDDR
VCC2V5
VCC2V5
VCC2V5
A A A A
A A A A A A
VTTDDR
A A AA
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
SRP
TRP
TRPTRP
TRP
TRP
TRP
TRP
TRP
SRPSRPSRPSRPSRPSRPSRP
DDR HF Bypass Caps (MLC)
DDR Bulk Caps
RPRP
GB
DDR SDRAM - Bypass Caps
ML300 CPU
DDR Bypass Capacitors
DDR Bulk Caps, 2 per IC, at ends
DDR Hi Freq Bypass
VTT Hi Freq Bypass
Vtt Bulk Caps
(X-Ray View to Bottom Side)LAYOUT FOR DDR, CAPS, RPs
TRP
SRP
VTT Bulk Caps
VTT HF Bypass Caps (MLC)
Termination Resistor Pack
Series Resistor Pack
TRP
U7U8U9 U6
5534
2
1 C31710UF 1
2
10UFC324
2
110UFC323
2
1 C31910UF
2
1 04020.1UFC305
2
110UFC3401
2
C33910UF
2
110UFC3381
2
C33710UF
2
110UFC3361
2
C33510UF
2
1 04020.1UFC334
1
2C3330.1UF
0402
2
1 04020.1UFC332
1
2
04020.1UFC331
2
1
C3300.1UF
04021
2
04020.1UFC329
2
1
C3280.1UF
04021
2
04020.1UFC327
2
1
C3260.1UF
04021
2C3250.1UF
0402
1
2
10UFC322
2
1 C32110UF
1
2
10UFC3201
2
10UFC318
1
2
04020.1UFC315
2
1
C3140.1UF
04021
2C3130.1UF
0402
2
1 04020.1UFC312
1
2C3110.1UF
0402
1
2
04020.1UFC308
2
1 04020.1UFC307
1
2C3060.1UF
04021
2C3040.1UF
0402
2
1 04020.1UFC303
1
2C3020.1UF
0402
2
1
C3010.1UF
0402
1
2
04020.1UFC310
2
1
C3090.1UF
0402
GRN
RED
GRN
RED
VCC5VCC5VCC5VCC5
0402
VCC2V5
VCC2V5
VCC5 VCC5 VCC5VCC5VCC5VCC5
0402
0402
0402
GS
D
GS
D
GS
D
0402
0402
0402
0402
0402
0402
0402
0402
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
R
G
R/G
B
R/G BB
BB
B B
B
B
B
B
BP
Illumination LEDs
Illumination LEDs
Illumination LEDs
ML300 CPU
LED placement on Solder side of board (not X-Ray)
FPGAU1
DS406 DS402
DS427DS428
DS429 DS430
B
RGRR/GPLB OPB
DS403
FPGASys ACEBus Err
DS403DS403DS403
DS403DS403
INIT DONESTATERR
DS403
DS405 DS404
DS401 BLUE 0603 LED
RED 0603 LED
GREEN 0603 LED
DUAL COLOR LED
35 55
12
BLUE
DS406
21
DS401
BLUE
12
R469
64.9R
2164.9R
R468
12
R467
64.9R
2164.9R
R466
12
R406
64.9R
2164.9R
R405
12
R404
64.9R
12
R403
64.9R
0402
12
R402
64.9R
2164.9R
R401
CASE_LIGHT_A1
CASE_LIGHT_C
1 2
3Q401BSS138
1 2
3Q405BSS1383
21
Q402BSS138
CASE_LIGHT_C2
2151.1R
R186
12
R184
51.1R
2156.2R
R183
CASE_LIGHT_A3
CASE_LIGHT_B3
CASE_LIGHT_B2
CASE_LIGHT_B1
CASE_LIGHT_A2
CASE_LIGHT_BCASE_LIGHT_A
12
R185
56.2R
CASE_LIGHT
CASE_LIGHT_C1
CASE_LIGHT_C3
CASE_LIGHT_C4
OPB_BUS_ERROR_3V3
34
2 1
LED_DUAL
DS102
PLB_BUS_ERROR_3V3
34
2 1
DS103
LED_DUAL
12
BLUE
DS402
21
DS403
BLUE
12
BLUE
DS404
21
DS405
BLUE
21
DS427
BLUE
12
BLUE
DS428
21
DS429
BLUE
12
BLUE
DS430
DCD
RXD
TXD
GND
DSR
RTS
CTS
RI
DTR
SHLD
DCD
RXD
TXD
GND
DSR
RTS
CTS
RI
DTR
SHLD
VCC2V5
VCC2V5
0402
0402
0402
VCC2V5
VCC2V5
VCC2V5
T1OUT
SHDN_N
VCC
GND
R2IN
T2OUT
T3OUT
R1IN
R2OUT
SWOUT
LOUT
T3IN
C1-
VL
SWIN
LIN
C2+
V+
C1+
C2-
V-
T1IN
T2IN
R1OUT
TSSOP24
MAX3388ETSSOP24
T1OUT
SHDN_N
VCC
GND
R2IN
T2OUT
T3OUT
R1IN
R2OUT
SWOUT
LOUT
T3IN
C1-
VL
SWIN
LIN
C2+
V+
C1+
C2-
V-
T1IN
T2IN
R1OUT
TSSOP24
MAX3388ETSSOP24
0402
VCC2V5
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
RI
CTS
RTS
DSR
SG
DTR
TX
RX
DCD
9
8
6
5
4
3
2
1
7
PIN
Cable Side
ML300
NAME DIR
RI
CTS
RTS
DSR
SG
DTR
TX
RX
DCD
9
8
6
5
4
3
2
1
BP
Silkscreen:
Silkscreen:
"UART 1"
"UART 2"
Serial Ports
Serial Ports
ML300 CPU
V2P7 Bank 4 (16)
7
PIN
RS232 Host (DTE) Pinout
RS232 Host (DTE) Pinout
Cable Side
ML300
NAME DIR
36 55
CTS1_PORT
RXD1_PORT
TXD1_PORT
RTS1_PORT
1
2
0.22UFC278
0603
2
1 C2770.22UF
0603
1
2
0.22UFC276
0603
2
1 C2750.22UF
0603
2
1 C2790.22UF
0603
2
1 C2740.22UF
0603
1
2
0.22UFC273
0603
2
1 C2720.22UF
0603
1
2
0.22UFC271
0603
2
1 C2700.22UF
0603
NC
NC
NC
NC
NC
NC
NC
NC
214.70K
R261
CTS2_PORT
RXD2_PORT
RTS2_PORT
TXD2_PORT
13
8
7
6
5
1
2
4
16
15
14
3
9
10
11
12
18
19
20
17
22
23
24
21
U271MAX3388ECUG
21
24
23
22
17
20
19
18
12
11
10
9
3
14
15
16
4
2
1
5
6
7
8
13
U270MAX3388ECUG
UART1_V+
UART1_C1-
UART1_C1+
UART2_V-
UART2_C2-
UART2_C2+
UART2_C1-
UART2_V+
UART1_C2+
UART1_C2-
UART1_V-
UART2_C1+
12
R262
4.70K
214.70K
R264
12
R263
4.70K
TXD1_FPGA
CTS1_FPGA
RXD1_FPGA
RTS1_FPGA
CTS2_FPGA
RTS2_FPGA
TXD2_FPGA
RXD2_FPGA
UART1_FB 1
2
3
5
6
7
8
9
4
11 10
CONN_DB9_R
P106
UART2_FB 1
2
3
5
6
7
8
9
4
11 10
P107
CONN_DB9_R
YA
VCC5VCC5
VCC5
VCC5
0402
0402
0402
0402
0402
0402
0402
04020402
0402
0402
CTS742
YA
B
E
C
B
E
C
B
E
C
B
E
C
YA
CTS742
YA
YA
VCC5
YA
CONN_MD6_SH
VCC
GND
CLK
NC2
NC6
DATA
SHLDA
SHLDB MNT
CONN_MD6_SH
VCC
GND
CLK
NC2
NC6
DATA
SHLDA
SHLDB MNT
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
PS2 NOTES:
FPGA through a voltage divider for signals from peripheral.
to bring the signal up to 5V levels1. PS2 uses open collector. Use NPN transistor
2. The Signal to the connector is fed back to the
PS/2 Ports
Silkscreen:"PS2 #1"
"Keyboard"Mouse"
ML300 CPU
V2P7 Bank 0 (12)
PS/2 Ports
"PS2 #2"Silkscreen:
Unused gates
37 55
NC
4 3 526 198 7
P104
4 3 526 198 7
P105
PS2_1_DATA
89
U19
DM74AS1034AM
43
U19
DM74AS1034AM
21
U19
DM74AS1034AM
4321
5678
4.7KRP401
PS2_1_CLK
65
U19
DM74AS1034AM
PS2_2_DATA
2
1
6
Q404
MMDT3904 PS2_2_DATA_IN
PS2_1_DATA_IN 2
1
6
MMDT3904
Q403
PS2_2_CLK
5
4
3
Q403
MMDT3904
5
4
3
Q404
MMDT3904
12
R415
10.0K
0402
11
10
U19
DM74AS1034AM
NCNCNC
NC
4321
5678
RP4024.7K
12
R408
10.0K
1 2
R4161.80K
1 21.80KR412
12
R410
4.70K
12
R414
4.70K
12
4.70K
R409
12
4.70K
R411
1 21.80KR413
12
10.0K
R418
12
R407
10.0K
1 2
R4171.80K
12
13
U19
DM74AS1034AM
NC
PS2_1_CLK_OUT
PS2_2_CLK_IN
PS2_1_DATA_OUT
PS2_1_CLK_IN
PS2_2_DATA_OUT
PS2_2_CLK_OUT
NC
NC
VCC3V3
VCC3V3
PARTS=1
1_NC2_A03_A14_A25_A36_A47_A58_A69_A710_GND11_NC12_A813_A914_A1015_A1116_A1217_A1318_A1419_A1520_GND21_NC22_A1623_A1724_A1825_A1926_A2027_A2128_A2229_A2330_GND31_NC32_A2433_A2534_A2635_A2736_A2837_A2938_A3039_A3140_GND B31_41
B30_42B29_43B28_44B27_45B26_46B25_47B24_48OE4_49VCC_50B23_51B22_52B21_53B20_54B19_55B18_56B17_57B16_58OE3_59VCC_60B15_61B14_62B13_63B12_64B11_65B10_66B9_67B8_68OE2_69VCC_70B7_71B6_72B5_73B4_74B3_75B2_76B1_77B0_78OE1_79VCC_80
MILLIPAQ80
LEVEL=STD
MILLIPAQ80QS34XV245
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
Parallel Port Level Shifter
Unused clamp diode pinUnused clamp diode pins.
GB
ML300 CPU
V2P7 Bank 7 (19)
Parallel Port Level Shifter
5538
12345678910111213141516171819202122232425262728293031323334353637383940 41
424344454647484950515253545556575859606162636465666768697071727374757677787980
U20QS34XV245Q3
NC
NC
NC
PP_CLMP_USERDEF3PP_CLMP_USERDEF1PP_CLMP_NWAIT
PP_CLMP_INTRPP_CLMP_DATA7PP_CLMP_DATA6PP_CLMP_DATA5PP_CLMP_DATA4PP_CLMP_DATA3PP_CLMP_DATA2PP_CLMP_DATA1
PP_CLMP_DATA0PP_CLMP_NASTROBEPP_CLMP_NINITPP_CLMP_USERDEF2
PP_CLMP_HD
PP_CLMP_NDSTROBEPP_CLMP_NWRITE
PP_CLMP_DIR
1
2
C1960.1UF
04022
10.1UFC193
0402 2
10.1UFC195
0402
1
2
C1940.1UF
0402
NC
PP_FPGA_DATA1PP_FPGA_DATA2
PP_FPGA_NWAIT
PP_FPGA_USERDEF3PP_FPGA_USERDEF1
PP_FPGA_INTR
PP_FPGA_DATA6PP_FPGA_DATA7
PP_FPGA_DATA5PP_FPGA_DATA4PP_FPGA_DATA3
PP_FPGA_DATA0PP_FPGA_NASTROBEPP_FPGA_NINITPP_FPGA_USERDEF2PP_FPGA_NDSTROBEPP_FPGA_NWRITEPP_FPGA_HDPP_FPGA_DIR
VCC5
VCC3V3
TSSOP48
2B10
2B9
SB8
2B7
2B6
2B5
2B4
GND_32
2B3
2B2
2B1
1B10
1B9
1B8
1B7
1B6
GND41
1B5
1B4
1B3
1B2
1B1
OE2_N
OE1_N
2A10
2A9
2A8
2A7
2A6
2A5
2A4
GND_17
2A3
VCC_15
2A2
2A1
1A10
1A9
1A8
1A7
1A5
1A4
1A3
1A2
1A1
NC
GND_8
1A6
20 bit FET Bus
VCC5
VCC5TSSOP48
HLHIN
C17
C16
C15
C14
PLH
VCB_31
B8
B7
GND_34
B6
B5
B4
B3
GND_39
B2
B1
VCB_42
Y13
Y12
Y11
Y10
Y9
DIR
HLH
A17
A16
A15
A14
PLHIN
VCC_18
A8
A7
GND_15
A6
A5
A4
A3
GND_10
A2
A1
VCC_7
A13
A12
A11
A10
A9
HD
IEEE1284 Transceiver
Parallel Port
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
"Parallel Port LEDs"S:ilkskreen Order as above
BP
Parallel Port Level Shifter
Parallel Port
Parallel Port
Label each withsuffix of netname
ML300 CPU
V2P7 Bank 7 (19)
5539
1
2
3
4
5
7
6
8
9
10
11
12
1325
24
23
22
21
20
19
18
17
16
15
14
P101
21
DS407
YELLOW
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U21
SN74LVC161284DGGR
12
R437
130R
0402
12
R419
130R
0402
21
0402
130R
R420
21
0402
130R
R421
12
R422
130R
0402
21
0402
130R
R423
12
R424
130R
0402
12
R425
130R
0402
21
0402
130R
R426
12
R427
130R
0402
21
0402
130R
R428
21
0402
130R
R429
12
R430
130R
0402
21
0402
130R
R431
12
R432
130R
0402
12
R433
130R
0402
12
R434
130R
0402
21
0402
130R
R435
21
0402
130R
R436
PP_LED_USERDEF2
PP_LED_NASTROBE
PP_LED_NINIT
PP_LED_HD
PP_LED_INTR
PP_LED_NWAIT
21
DS408
YELLOW
21
DS416
YELLOW
21
DS413
YELLOW
21
DS415
YELLOW
21
DS412
GREEN
21
DS418
YELLOW
21
DS419
GREEN
21
DS417
YELLOW
21
DS420
GREEN
21
DS421
GREEN
21
DS422
GREEN
21
DS409
YELLOW
21
DS423
GREEN
21
DS424
GREEN
21
DS410
YELLOW
21
DS425
GREEN
21
DS411
YELLOW
1
TP416
PP_Y11_TP
21
04024.70KR499
PP_PORT_USERDEF2PP_CLMP_USERDEF2
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
12
11
109654321 87
U22
DEVICE=SN74CBTD16210DGGR
1
TP419
1
TP415
PP_PLH_TP
21
DS414
YELLOW
PP_LED_DATA3
PP_LED_NWRITE
PP_LED_NDSTROBE
PP_LED_DATA7
PP_LED_DATA6
PP_LED_DATA5
PP_LED_DATA1
PP_LED_DATA2
PP_CLMP_DATA6
PP_CLMP_DATA7
PP_CLMP_INTR
PP_CLMP_NWAIT
PP_CLMP_USERDEF3
PP_CLMP_USERDEF1
PP_PORT_USERDEF3
PP_PORT_NASTROBE
PP_PORT_DATA2
PP_PORT_NINIT
PP_PORT_DATA0
PP_PORT_NDSTROBE
PP_PORT_DATA1
PP_PORT_DATA3
PP_PORT_DATA6
PP_PORT_DATA7
PP_PORT_INTR
PP_PORT_NWAIT
PP_LED_NASTROBE
PP_LED_DATA0
PP_LED_DATA2
PP_LED_DATA6
PP_LED_DATA7
PP_LED_NWAIT
PP_LED_USERDEF1
PP_LED_USERDEF3
PP_LED_USERDEF2
PP_LED_DATA1
PP_LED_INTR
PP_LED_NDSTROBE
PP_LED_NINIT
PP_LED_NWRITE
PP_LED_DATA5
PP_LED_DATA4
PP_LED_DATA3
PP_LED_HD
PP_LED_DIR
PP_PORT_NWRITE
PP_PORT_DATA4
PP_PORT_DATA5
PP_PORT_USERDEF1
PP_CLMP_DIR
PP_CLMP_HD
PP_CLMP_NWRITE
PP_CLMP_NDSTROBE
PP_CLMP_NINIT
PP_CLMP_NASTROBE
PP_CLMP_DATA0
PP_CLMP_DATA1
PP_CLMP_DATA2
PP_CLMP_DATA3
PP_CLMP_DATA4
PP_CLMP_DATA5
NC
PP_LED_USERDEF1
PP_LED_DATA4
PP_LED_DIR
PP_LED_USERDEF3
PP_LED_DATA0
0402
0402
0402
VCC5
VCC5
VCC5
VCC5
VCC5
VCC12_P
VCC2V5
AUDIO_5V
VCC5VCC1V5
VCC2V5
VCC5
VCC5
0402
NC
SCL2.5V
GND
SDA5V
ADD
VCC
ALRT_N
1.8V
MAX6683AUB
VCC3V3
NC
SCL2.5V
GND
SDA3.3V
ADD
VCC
ALRT_N
12V
MAX6652AUB
VCC5
0402
0402
0402
STBY_NSMBCLK DXP
ADD1
GND1ADD0ALRT_N
GND0
VCC
DXNSMBD
MAX1617
SDA VCCA0
T_CRIT_AGND
SCL
INTA1
LM76CNM_3
A0VCCWP
A2VSS
A1
SDASCL
SOIC8
VCC3V3
SCL
A0
A2
A1
L0
W0
W1
H0
H1
L1
GND
SDA
VCC
WP
TSSOP14
R0
R1
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
ML300_PWR_IO
NOTES:1. The IIC Bus has devices on both the CPU and
PWR_IO boards.
U24ML300_PWR_IOML300_PWR_IO
ML300_PWR_IO
ML300_CPUML300_CPU
Silkscreen:
signals, and isolated from othersignals as much as possible
BP
"ADDR: A0"
IIC Bus
ML300 CPU
Bank 3 (15) - IIC Bus
should be routed as differentialThese signals (FPGA_DXP, FPGA_DXN)
"FPGA Temp Sensor"Silkscreen:
"ADDR: 30"
Ext Volume10K Pot(LINEAR)
Silkscreen:"Audio Trimpot"
Silkscreen:"Sys Monitor 1""ADDR: 28"
"ADDR: 2A""Sys Monitor 2"
"IIC EEPROM"Silkscreen:
Silkscreen:"Ambient Temp Sensor""ADDR: 96"
to U1, FPGA_DXP and FPGA_DXN pins routedas differential pair. C251 close to U251
Decouple Cap
Comp should be placed as close as possible
"ADDR: A6"
MAX6652AUB
MAX6683AUB
BOARD REFIC
MAX6683AUB ML300_CPU
ML300_CPU
ML300_CPUML300_PWR_IO
U502
U251
U252U253
U256U4U2
U24
U255
Audio Trimpot
Ambient Temp32Kbit EEPROM
System Monitor 2System Monitor 4System Monitor 3
Real Time Clock 4Kbit EEPROMReal Time Clock RTC
System Monitor 1
DESCRIPTION ADDR
28/29
A6/A7
30/31
96/97A0/A1
2A/2B2E/2F2C/2D
DE/DFAE/AF
24LC32A/SN
MAX6652AUB
MAX1617 ML300_CPU FPGA Die/Ambient Temp
LM76CNM_3
X1226S8X1226S8
DS1845E-010DS1845E-010 U3 TFT Touchscreen Trimpot AC/AD
5640
IIC_CRIT_A
IIC_SCL
IIC_SCL
IIC_SCL
IIC_SDA
IIC_SDA
IIC_SDA
IIC_IRQ
2
3
5
4
8
9
12
13
11
10
7
1
14
6
U502
DS1845E-010
2
10.1UFC252
0402
187
34
2
56
U25324LC32A/SN
1 87
34
2
56
U252LM76CNM-3
34
6
2
78
15
11
14
10
12
U251MAX1617AMEE
12
R254
10.0K
1
2
0.1UFC253
0402
2
10.1UFC254
0402
12
R255
10.0K
IIC_WP
12
R253
200R
MAX_1_STBY_N
21
0.1UFC281
0402
IIC_SCL
IIC_SDA
NC
4
92
5
83
7
10
6
1
U256
NC
IIC_SDA
IIC_SCL
4
92
5
83
7
10
6
1
U255
211.00KR269
1 2
C2800.1UF
0402
2
1 C2512200PF
0402IIC_IRQ
2
1 C2500.1UF
0402
2
10.1UFC541
0402
1
TP256
1
TP255
1
TP254
12
R252
10.0K
2110.0K
R251
12
R250
10.0K
NC
NC
IIC_SCL
IIC_SDA
NC
IIC_WP
FPGA_DXP
FPGA_DXN
IIC_CRIT_A
AUDIO_VOLUME
GND
IIC_CRIT_A
VCC2V5
CS VCCHOLD
WPVSS
SO
SISCK
SOIC8
0402
0402
0402
0402
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
Decouple Cap
SPI
SPI Bus
SPI ROM 2.5V- 5.5V
ML300 CPU
Bank 4 (16)
5541
1
2
C2550.1UF
0402
21DNP
R267
SPI_DATA_CS_N
SPI_WP_N1
2
R256
DNP
21R257
DNP
21DNP
R258
12
DNP
R259
1 87
34
2
56
U254
DEVICE=25LC160/SN
SPI_DATA_INSPI_CLK
SPI_DATA_OUT
VCCIO_ENET
VCCD_ENET
VCCIO_ENET
VCCA_ENET
VCCIO_ENET
VCCTX_ENET
0402
0402
0402
0402
0402
0402
PKG_TYPE=LQFP64PARTS=1LEVEL=STD
REFCLK/XI_1
XO_2
MDDIS_3
RESET_4
TxSLEW0_5
TxSLEW1_6
GND_7
VCCIO_8
N/C_9
N/C_10
GND_11
ADDR0_12
ADDR1_13
ADDR2_14
ADDR3_15
ADDR4_16
17_RBIAS18_GND19_TPFOP20_TPFON21_VCCA22_VCCA23_TPFIP24_TPFIN25_GND26_SD/TP27_TDI28_TDO29_TMS30_TCK31_TRST32_SLEEP
33_PAUSE
34_TEST0
35_TEST1
36_LED/CFG3
37_LED/CFG2
38_LED/CFG1
39_PWRDWN
40_VCCIO
41_GND
42_MDIO
43_MDC
44_N/C
45_RXD3
46_RXD2
47_RXD1
48_RXD0
RX_DV_49GND_50VCCD_51
RX_CLK_52RX_ER_53TX_ER_54TX_CLK_55TX_EN_56TXD0_57TXD1_58TXD2_59TXD3_60GND_61COL_62CRS_63
MDINT_64
LXT971_LQFP64LQFP64
(DIE DOWN)
TG110-S050N2
0402
0402
0402
0402
VCCD_ENET
0402
0402
0402
MA_506
RJ45
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
Silkscreen:
Silkscreen:"GND"
GRN
"Ethernet Port"Silkscreen:
Connector is bottom view
YLW
Silkscreen:"Link/Act"
Silkscreen:"Full/Coll LED"
Silkscreen: "Ethernet Magnetics"
Ethernet PHY
Ethernet Phy
"PHY 10/100 100=ON"
Place at edge of PCB
Bank 0 (12)
ML300 CPU
Silkscreen: "Ethernet Phy"
42 55
7
5
3
1
6
4
2
8
9
1112
10
P103
CON_AMP_569564
PHY_RESETPHY_SLW0PHY_SLW1
PHY_RXD2
PHY_RX_CLK
PHY_TX_ER
PHY_RXD0
PHY_TX_CLK_TMP
PHY_RX_DV_TMP
1 220.0RR461
0402
PHY_RXD2_TMP
21
0402
R45420.0R
21
0402
R45620.0R
21
0402
R45820.0R
21
0402
R46020.0R
PHY_RXD3
PHY_RXD1
PHY_RX_DV
PHY_RX_ER
PHY_TX_CLK
1 220.0RR459
0402
1 220.0RR457
0402
1 220.0RR455
0402
1 220.0RR453
0402
PHY_CRS1 220.0RR449
0402
PHY_MDIOPHY_MDC
PHY_TX_ENPHY_TXD0PHY_TXD1PHY_TXD2PHY_TXD3
PHY_COL
PHY_MDINT
PHY_TPIP
PHY_CRS_TMP
PHY_COL_TMP 21
0402
R45220.0R
X40125MHZ
12
18PFC8
0402
2 1
C718PF
0402
1 24.70KR465
0402
21
0402
R4644.70K
1 24.70KR463
0402
PHY_ADDR3
PHY_ADDR4
21
0402
R4624.70K
1 24.70KR444
0402
21
R498
4.70K 1
24.70K
R439
1 2
DS426
LED0603
GREEN
21
R496
4.70K
PHY_TPIN
MAG_TAP_16
1
2
270PFC6
0603
1 2
0.01UFC5
0402
21
C4270PF
0603
2
1
C11000PF
1812
2
1
C31000PF
1812
2
1
C21000PF
1812
MAG_TAP_7
12
R445
49.9R
12
R447
49.9R
1 2200RR441
LEDC
1 2
R443200R
PHY_RXD1_TMP
PHY_RX_ER_TMP
1
2
3
6
7
8 9
10
11
14
15
134
5 12
16
T401
1TP425
NC
NC
NC
NC
NC
NC
MAG_TAP_14
12345678910
11
12
13
14
15
16
17181920212223242526272829303132
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49505152535455565758596061626364
U26
DEVICE=DJLXT971ALCA4834105
PHY_PAUSE
GND_ENET
PHY_PWRDN
GND_ENET
TX+
12
49.9R
R448
12
49.9R
R446
1
TP421 1 2
R43825.5R
1TP427
12
22.1K
R450
0402
PHY_RBIAS
12
R451
0R
12
49.9R
R440
12
R442
49.9R
PHY_SD/TP
MAG_TAP_2
RJ45_GND
GND_ENET
GND_ENET
PHY_XI
PHY_XO
PHY_ADDR2
PHY_ADDR1
PHY_ADDR0
PHY_TPONPHY_TPOP
PHY_RXD3_TMP
RJ45_GRND1RJ45_GRND2
RJ45_GRND3RJ45_GRND4
RX-
RX+TX-
PHY_LED1
LEDL
1TP423 1TP424
1TP426
NC
NC
PHY_SLEEP PHY_RX_CLK_TMP
PHY_TX_ER_TMP
PHY_RXD0_TMP
VCC3V3 VCCTX_ENETVCCD_ENET
GND_ENET
VCCA_ENET
VCCIO_ENET
GND_ENET
0402 0402 0402
A
CTCB1210-600-SSM
2961666671FERRITE_BD
2961666671FERRITE_BD
0402 0402 0402
A0402
04022961666671FERRITE_BD A
CTCB1210-600-SSM
0402 0402
04020402
0402
VCC2V5
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
Ethernet Power
Ethernet Power Filter
ML300 CPU
5543
2
10.1UFC20
2
10.1UFC12
2
11000PF
C14
2
1 C230.1UF
2
10.1UFC22
1 2
FB404
PKG_TYPE=L1210
2
1 C2110UF
2
1 C191UF
1 2
FB403L1812
1
2
C170.1UF
2
1 C90.1UF
2
1 C1610UF
2
10.01UF
C26
2
1 C251000PF
2
11000PF
C24
1 2
FB406
L1812
1 2
FB405
L1812
1 2
FB402L12101
2
10UFC18
2
1 C101UF
2
1 C151000PF
2
1 C130.1UF
2
10.1UFC11
PARTS=1LEVEL=STD
TSSOP48
1_1DIR2_1B03_1B14_GND5_1B26_1B37_VCC18_1B49_1B510_GND11_1B612_1B713_2B014_2B115_GND16_2B217_2B318_VCC119_2B420_2B521_GND22_2B623_2B724_2DIR 2OE_25
2A7_26SA6_27GND_282A5_292A4_30
VCC2_312A3_322A2_33GND_342A1_352A0_361A7_371A6_38GND_391A5_401A4_41
VCC2_421A3_431A2_44GND_451A1_461A0_4710E_48
74ALVC164245TSSOP48
VCC3V3
VCC3V3
VCC2V5
VCC2V5
PARTS=1LEVEL=STD
TSSOP48
1_1DIR2_1B03_1B14_GND5_1B26_1B37_VCC18_1B49_1B510_GND11_1B612_1B713_2B014_2B115_GND16_2B217_2B318_VCC119_2B420_2B521_GND22_2B623_2B724_2DIR 2OE_25
2A7_26SA6_27GND_282A5_292A4_30
VCC2_312A3_322A2_33GND_342A1_352A0_361A7_371A6_38GND_391A5_401A4_41
VCC2_421A3_431A2_44GND_451A1_461A0_4710E_48
74ALVC164245TSSOP48
0402
0402
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP
LCD Level Shifters - 2.5V to 3.3V
TFT LCD
TFT LCD - Level Shifter and Conn
ML300 CPU
V2P7 Bank 4 (16)
5544
SYSACE_TSTTMS_3V3
PLB_BUS_ERROR_3V3OPB_BUS_ERROR_3V3
FPGA_INIT_LED
TFT_LCD_DPS
TFT_LCD_DETFT_LCD_B5
TFT_LCD_B3TFT_LCD_B4
TFT_LCD_B2TFT_LCD_B1
TFT_LCD_G4
TFT_LCD_B0TFT_LCD_G5
TFT_LCD_G3
TFT_LCD_G1TFT_LCD_G2
TFT_LCD_R5TFT_LCD_G0
TFT_LCD_R3TFT_LCD_R4
TFT_LCD_VSYNC
TFT_LCD_R2TFT_LCD_R1
TFT_LCD_R0
TFT_LCD_HSYNCTFT_LCD_CLK TFT_FPGA_CLK
TFT_FPGA_HSYNC
TFT_FPGA_R0TFT_FPGA_VSYNC
TFT_FPGA_R1TFT_FPGA_R2
TFT_FPGA_R3TFT_FPGA_R4TFT_FPGA_R5TFT_FPGA_G0
TFT_FPGA_G2TFT_FPGA_G1
TFT_FPGA_G4TFT_FPGA_G3
TFT_FPGA_G5TFT_FPGA_B0
TFT_FPGA_DPS
TFT_FPGA_DETFT_FPGA_B5
TFT_FPGA_B4TFT_FPGA_B3
TFT_FPGA_B2TFT_FPGA_B1
PLB_BUS_ERROROPB_BUS_ERROR
TFT_LCD_HSYNC
SYSACE_TSTTMS_2V5
SYSACE_TSTTCK_2V5SYSACE_TSTTDI_2V5
12
R495
4.70K
12
4.70K
R491
SYSACE_TSTTDI_3V3SYSACE_TSTTCK_3V3
123456789101112131415161718192021222324 25
2627282930313233343536373839404142434445464748
U28
SN74ALVC164245DGGR
NCNCNC
123456789101112131415161718192021222324 25
2627282930313233343536373839404142434445464748
U27
SN74ALVC164245DGGR
VCC3V3
AUDIO_5V
AUDIO_5V
AUDIO_5V
VCC3V3
VCC3V3
VCC3V3
0402
B
B
B
PHONEJACK STEREO
PHONEJACK STEREO
MA_506
PKG_TYPE=LQFP48PARTS=1LEVEL=STD
DVDD1_1
XTL_IN_2
XTL_OUT_3
DVSS1_4
SDATA_OUT_5
BIT_CLK_6
DVSS2_7
SDATA_IN_8
DVDD2_9
SYNC_10
RESET_11
PC_BEEP_12
13_PHONE_IN14_AUX_L15_AUX_R16_VIDEO_L17_VIDEO_R18_CD_L19_CD_GND_REF20_CD_R21_MIC122_MIC223_LINE_IN_L24_LINE_IN_R
25_AVDD1
26_AVSS1
27_VREF
28_VREFOUT
29_AFILT1
30_AFLIT2
31_FILT_R
32_FILT_L
33_RX3D
34_CX3D
35_LINE_OUT_L
36_LINE_OUT_R
MONO_OUT_37AVDD2_38
HP_OUT_L_39AVSS2_40
HP_OUT_R_41NC_42
AVDD3_43AVSS3_44
ID0_45ID1_46JS0_47JS1_48
LQFP48AD1885
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
PLACE NEAR U500
MIC IN
LINE IN
Audio Mixer and Codec
KD
Audio Codec
ML300 CPU
V2P7 Bank 3 (14)
5545
12345678910
11
12
131415161718192021222324
25
26
27
28
29
30
31
32
33
34
35
36
373839404142434445464748
U500
DEVICE=AD1885JST
2
1 C508470PF0402
GND
AUDIO_VREF
NCNCNCNCNC
NC
21
C5110.1UF
0402
2
11UFA
C525
21
0402
R514
47.0K
1247.0K
R516
0402
21
1UFA
C527
1247.0K
R515
0402
21
1UFA
C526
2
10.1UFC524
04022
10.1UFC523
0402
2
10.1UFC521
04022
10.1UFC520
0402
21
C51022PF0402
1 2
22PFC509
0402
12
4.70K
R507
0402
21
0.33UFC503
0805
1 2
C5020.33UF
0805
12
4.70K
R505
0402
21
0.33UFC501
0805
24.576MHZ
X501
2
1 C51847000PF04022
11UFC517
2
11UFC5161
2
270PFC515
06032
1 C514270PF0603
1
2
0.1UFC513
0402
21
C5040.33UF
0805
AUDIO_MIC_1_2_JACK
1
2
470PFC507
0402
AUDIO_AFILT1
NC
AUDIO_MONO_OUT
AUDIO_XTL_IN
AUDIO_XTL_OUT
LINE_OUT_L_COMP
LINE_OUT_R_COMP
AUDIO_CX3D
AUDIO_RX3D
AUDIO_FILT_L
AUDIO_FILT_R
AUDIO_VREFOUT_COMP
PCI_SPKROUT_COMP
AUDIO_BEEPIN_COMPAUDIO_BEEPIN
2
4
5
3
1
P117
2
4
5
3
1
P118
2
1 C5060.33UF
21
0402
R5016.80K
2
1 C52210UF
2
1 C51910UF
2
1 C51210UF
12
R512
1M
21
0402
R5102.00K
210402
R509
4.70K
21
0402
R5064.70K
21
0402
R5044.70K
21
0402
R502DNP
AUDIO_SYNCH
21
0402
R5084.70K
AUDIO_GND
AUDIO_SDATA_IN
AUDIO_GND AUDIO_GND GND
LINE_OUT_L
AUDIO_AMP_SHUTDOWN
LINE_OUT_R
AUDIO_SDATA_OUT
AUDIO_GND
GND
AUDIO_RESET
AUDIO_RIGHT
AUDIO_LEFT
AUDIO_GND
AUDIO_GND
GND
AUDIO_GND
AUDIO_BIT_CLK
AUDIO_GND
AUDIO_GND
AUDIO_GND
AUDIO_GND
PCI_SPKROUT
AUDIO_AFILT2
GND
12
10.0K
R513
0402
21
0402
R503
4.70K
AUDIO_5V
AUDIO_5V
AUDIO_5VVCC5
B
B
PHONEJACK STEREO
VCC5
FERRITE_BD
2961666671FERRITE_BD
TSSOP28
SHUTDOWN
B_IN
B_FB
BYPASS
A_IN
A_FB
BEEP
VOLUME
B_R1
B_R2
OUT_B_MINUS
OUT_B_PLUS
HP_IN
OUT_A_PLUS
OUT_A_MINUS
A_L2
GND2
GND3
GND4
GND5
INTERNAL_GAIN_SELECT
MODE
MUTE
A_L1
GND1
VDD1
VDD2
VDD3
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
RS532RS531
Function
ANALOG GND SHOULD BE SEGREGATED PLANE
HEADPHONE/
LINE OUT
L SPKR
KD
RS531RS532
RS533RS534 Line
Rs InRs Out
RS533RS534
Headphone(Default)
KEEP GND INTO LOTS OF COPPER
Volume of Audio codec is controlled
Place near FB501/502
R SPKR
FAT TRACE
Audio Codec PWR Amps
ML300 CPU
Audio Codec Power Amplifiers
Audio IIC Trimpot Addr is "A6"by an IIC trimpot - see page 40.
46 55
21
C543220UFX
21
0402
R536
1.00K
21
0402
R535
1.00K
1 20R
0805
R534
21
R533
0805
0R
21
0402
R538
100K
2
1
1UFA
C534
2 1
J506DNP
1 2DNP
0805
R532
21
DNP
0805
R531
12
J505DNP
PKG_TYPE=HDR_1X2
21
C53968000PF0402
1220.0K
R523
0402
2
10
9
22
12
13
11
7
24
25
26
28
21
15
17
18
8
14
20
23
3
4
5
19
1
6
16
27
U501
DEVICE=LM4835MTE
21
C54068000PF0402
21
0402
R526
20.0K
21
FB502L1812
1 2
FB501
2961666671
L1812
2
11UFA
C538
GND
2
10.1UFC535
0402
1
2
C5360.1UF0402
2 1
0.33UFA
C533
2 1
0.33UFA
C53221
0402
R51920.0K
2
1 C5310.1UF0402
1
2
0.1UFC530
04022
10.1UFC529
0402
AUDIO_RIGHT
AUDIO_VOLUME
21
0402
R539100K
1 2
20.0KR5250402
LINE_OUT_HP
AUDIO_OUT_B_MINUS
AUDIO_OUT_A_MINUS
AUDIO_OUT_B_PLUS
AUDIO_OUT_A_PLUS
AUDIO_BYPASS
AUDIO_LEFT
2
4
5
3
1
P116
21
0402
R52820.0K
21
0402
R52720.0K
21
0402
R52420.0K
21
0402
R52120.0K
21
0402
R52020.0K
21
0402
R51820.0K
21
C542220UFX
2
1 C53710UF
2
1 C52810UF
GND AUDIO_GND
AUDIO_GND
AUDIO_GND
AUDIO_AMP_SHUTDOWN
LINE_OUT_R
LINE_OUT_L
AUDIO_GND
A0A1
A10A11A12A13A14A15
A2A3A4A5A6A7
A8A9
B0B1
B10B11B12B13B14B15
B2B3B4B5B6B7
B8B9
NC1
VCC1VCC2
OE1
OE2
IDT
GND2 NC2
QVSOP40
GND1
QS32X2245
VCC5
VCC5
VCC5
VCC5
PKG_TYPE=TSSOP56PARTS=1LEVEL=STD
1_NC2_1A13_1A24_1A35_1A46_1A57_1A68_GND9_1A710_1A811_1A912_1A1013_1A1114_1A1215_2A116_2A217_VCC18_2A319_GND20_2A421_2A522_2A623_2A724_2A825_2A926_2A1027_2A1128_2A12 2B12_29
2B11_302B10_312B9_322B8_332B7_342B6_352B5_362B4_37GND_382B3_392B2_402B1_41
1B12_421B11_431B10_441B9_451B8_461B7_471B6_48GND_491B5_501B4_511B3_521B2_531B1_542OE_551OE_56
TSSOP56QS316211
0402
0402
0402
0402
A0A1
A10A11A12A13A14A15
A2A3A4A5A6A7
A8A9
B0B1
B10B11B12B13B14B15
B2B3B4B5B6B7
B8B9
NC1
VCC1VCC2
OE1
OE2
IDT
GND2 NC2
QVSOP40
GND1
QS32X2245
A0A1
A10A11A12A13A14A15
A2A3A4A5A6A7
A8A9
B0B1
B10B11B12B13B14B15
B2B3B4B5B6B7
B8B9
NC1
VCC1VCC2
OE1
OE2
IDT
GND2 NC2
QVSOP40
GND1
QS32X2245
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
Bank 2/3 (14/15)
January 15th, 2002 0.90
A
BOT SIDE
TOP SIDE
BOT SIDE
BP/GB
PCI Clamp Diodes for 5V Compliance
ML300 CPU
PCI Clamps
TOP SIDE
47 55
PCI_PORT_AD31PCI_PORT_AD26PCI_PORT_AD27PCI_PORT_AD28
PCI_PORT_AD25PCI_PORT_AD24
PCI_PORT_AD23PCI_PORT_CBE3
PCI_PORT_AD20PCI_PORT_AD21PCI_PORT_AD22PCI_PORT_AD18PCI_PORT_AD19PCI_PORT_CBE2PCI_PORT_AD16PCI_PORT_AD17
PCI_FPGA_PMC_TDI
PCI_FPGA_AD29PCI_FPGA_AD30
31
3
5
7
9
13
15
17
19
2
4
6
8
12
14
16
1821
40
2223
38
24
37
25
36
26
35
27
34
28
3332
30
1020
29
39
111
U50 QS32X2245Q2
31
3
5
7
9
13
15
17
19
2
4
6
8
12
14
16
1821
40
2223
38
24
37
25
36
26
35
27
34
28
3332
30
1020
29
39
111
U52 QS32X2245Q2
1
TP607
12
1N4148D604
SOD-323
PCI_FPGA_INTA
2 110.0KR622
2 1
1N4148D603
SOD-323
12
R61910.0K
2 1
1N4148D601
SOD-323
2 110.0KR621
12
R62010.0K
123456789
10111213141516171819202122232425262728 29
303132333435363738394041424344454647484950515253545556
U53
QS316211PA
12
D602
1N4148SOD-323
NC
PCI_FPGA_SB0
PCI_FPGA_BUS_RST
PCI_PORT_PMC_TCK
PCI_PORT_PMC_TMS
PCI_PORT_INTDPCI_PORT_PRS2
PCI_PORT_BM4
PCI_PORT_AD30
PCI_PORT_STOP
PCI_PORT_SERR
PCI_PORT_SBO
PCI_PORT_PAR
PCI_PORT_AD10
111
39
29
2010
30
3233
28
34
27
35
26
36
25
37
24
38
2322
40
2118
16
14
12
8
6
4
2
19
17
15
13
9
7
5
3
31
U51 QS32X2245Q2
PCI_PORT_CB_GNT
PCI_PORT_GBL_RSTPCI_PORT_PMC_TRST
PCI_PORT_PMC_TDI
PCI_PORT_PERR
PCI_PORT_AD15
PCI_PORT_FRAME
PCI_PORT_IRDY
PCI_PORT_LOCK
PCI_PORT_SDONEPCI_PORT_CBE1
PCI_PORT_AD13PCI_PORT_AD14
PCI_PORT_TRDY
PCI_PORT_DEVSEL
PCI_PORT_PRS1
PCI_PORT_BM3PCI_PORT_BUS_RST
PCI_PORT_INTBPCI_PORT_INTC
PCI_PORT_PMC_TDO
PCI_PORT_PMC_REQPCI_PORT_AD29
PCI_PORT_PMC_GNT
PCI_PORT_INTA
PCI_PORT_CB_REQ
PCI_FPGA_PMC_TCK
PCI_FPGA_PMC_TMS
PCI_FPGA_INTDPCI_FPGA_PRS2
PCI_FPGA_BM4
PCI_FPGA_CB_GNT
PCI_FPGA_GBL_RSTPCI_FPGA_PMC_TRST
PCI_FPGA_PRS1
PCI_FPGA_BM3
PCI_FPGA_INTBPCI_FPGA_INTC
PCI_FPGA_PMC_TDO
PCI_FPGA_PMC_REQPCI_FPGA_PMC_GNT
PCI_FPGA_CB_REQ
PCI_FPGA_STOP
PCI_FPGA_SERR
PCI_FPGA_PAR
PCI_FPGA_AD10
PCI_FPGA_PERR
PCI_FPGA_AD15
PCI_FPGA_FRAME
PCI_FPGA_IRDY
PCI_FPGA_LOCK
PCI_FPGA_SDONEPCI_FPGA_CBE1
PCI_FPGA_AD13PCI_FPGA_AD14
PCI_FPGA_TRDY
PCI_FPGA_DEVSEL
NC
NC
PCI_FPGA_AD00
PCI_FPGA_AD02
PCI_FPGA_AD03
PCI_FPGA_AD06
PCI_FPGA_ACK64
PCI_FPGA_AD04
PCI_FPGA_REQ64
PCI_FPGA_AD01
PCI_FPGA_CBE0
PCI_FPGA_AD09
PCI_FPGA_AD12
PCI_FPGA_M66EN
PCI_FPGA_AD07
PCI_FPGA_AD11
PCI_FPGA_AD05
PCI_FPGA_AD08
PCI_PORT_AD00
PCI_PORT_AD02
PCI_PORT_AD03
PCI_PORT_AD06
PCI_PORT_CBE0
PCI_PORT_AD09
PCI_PORT_AD12
PCI_PORT_M66EN
PCI_PORT_ACK64
PCI_PORT_AD04
PCI_PORT_AD07
PCI_PORT_AD11
PCI_PORT_REQ64
PCI_PORT_AD01
PCI_PORT_AD05
PCI_PORT_AD08
NC
NCNC
PCI_FPGA_AD31
PCI_FPGA_AD27
PCI_FPGA_AD24PCI_FPGA_AD25
PCI_FPGA_AD21PCI_FPGA_AD22
PCI_FPGA_AD16
PCI_FPGA_AD20
PCI_FPGA_CBE2
PCI_FPGA_AD23
PCI_FPGA_AD26
PCI_FPGA_AD17
PCI_FPGA_AD19PCI_FPGA_AD18
PCI_FPGA_CBE3
PCI_FPGA_AD28
VCC5
VCC5
CTS742
VCC5
VCC5
A0A1
A10A11A12A13A14A15
A2A3A4A5A6A7
A8A9
B0B1
B10B11B12B13B14B15
B2B3B4B5B6B7
B8B9
NC1
VCC1VCC2
OE1
OE2
IDT
GND2NC2
QVSOP40
GND1
QS32X2245
A0A1
A10A11A12A13A14A15
A2A3A4A5A6A7
A8A9
B0B1
B10B11B12B13B14B15
B2B3B4B5B6B7
B8B9
NC1
VCC1VCC2
OE1
OE2
IDT
GND2 NC2
QVSOP40
GND1
QS32X2245
A0A1
A10A11A12A13A14A15
A2A3A4A5A6A7
A8A9
B0B1
B10B11B12B13B14B15
B2B3B4B5B6B7
B8B9
NC1
VCC1VCC2
OE1
OE2
IDT
GND2 NC2
QVSOP40
GND1
QS32X2245
CTS742
A0A1
A10A11A12A13A14A15
A2A3A4A5A6A7
A8A9
B0B1
B10B11B12B13B14B15
B2B3B4B5B6B7
B8B9
NC1
VCC1VCC2
OE1
OE2
IDT
GND2NC2
QVSOP40
GND1
QS32X2245
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
on the Bottom side of the boardThis Clamp Diode will be placed
on the Bottom side of the boardThis Clamp Diode will be placed
This Clamp Diode will be placedon the top side of the board
This Clamp Diode will be placedon the top side of the board
BP
Bank 2/3 (14/15)
PMC Clamps
ML300 CPU
Clamp Diodes for PMC
5548
23
141516171819
456789
1213
3837
262524232221
363534333231
2827
1
3040
39
29
201110
U912
DEVICE=QS32X2245Q2
FPGA_PMC_CONN4_IO30
AUDIO_PMC_SYNCHAUDIO_PMC_CS0
AUDIO_PMC_BIT_CLKPMC_CONN4_IO9
4321
5678
22RRP914
IIC_PMC_SDAIIC_PMC_IRQ
IIC_WP
AUDIO_PMC_SDATA_OUT
FPGA_PMC_CONN4_IO61
31
3
5
7
9
13
15
17
19
2
4
6
8
12
14
16
1821
40
2223
38
24
37
25
36
26
35
27
34
28
3332
30
1020
29
39
111
U802 QS32X2245Q2
23
141516171819
456789
1213
3837
262524232221
363534333231
2827
1
3040
39
29
20 1110
U913DEVICE=QS32X2245Q2
IIC_FPGA_WP
PMC_CONN4_IO11PMC_CONN4_IO13
PMC_CONN4_IO2923
141516171819
456789
1213
3837
262524232221
363534333231
2827
1
3040
39
29
201110
U914
QS32X2245Q2
1 2
1N4148D903
SOD-323
2 1
10.0KR947
0402
PMC_CONN4_IO38PMC_CONN4_IO30
FPGA_PMC_CONN4_IO10
FPGA_PMC_CONN4_IO62
AUDIO_FPGA_SDATA_INAUDIO_FPGA_SDATA_OUT
AUDIO_FPGA_RESET_NIIC_FPGA_SCL
21
D901
1N4148SOD-323
120402
R94510.0K
8765
1234
RP91022R
2 1
D9021N4148
SOD-323
1 20402
R94610.0K
12
1N4148D801
SOD-323
21
10.0KR833
0402
NCNC
NCNC
NCNC
IIC_PMC_SCL
AUDIO_PMC_SDATA_INAUDIO_PMC_RESET_N
AUDIO_SDATA_INAUDIO_SDATA_OUT
IIC_SCLAUDIO_RESET
PMC_CONN4_IO10PMC_CONN4_IO12PMC_CONN4_IO14
PMC_CONN4_IO16PMC_CONN4_IO18PMC_CONN4_IO20PMC_CONN4_IO22PMC_CONN4_IO24PMC_CONN4_IO26PMC_CONN4_IO28
FPGA_PMC_CONN4_IO31
FPGA_PMC_CONN4_IO28FPGA_PMC_CONN4_IO26FPGA_PMC_CONN4_IO24FPGA_PMC_CONN4_IO22FPGA_PMC_CONN4_IO20FPGA_PMC_CONN4_IO18FPGA_PMC_CONN4_IO16
FPGA_PMC_CONN4_IO14FPGA_PMC_CONN4_IO12
FPGA_PMC_CONN4_IO32FPGA_PMC_CONN4_IO34FPGA_PMC_CONN4_IO36FPGA_PMC_CONN4_IO38FPGA_PMC_CONN4_IO40FPGA_PMC_CONN4_IO42FPGA_PMC_CONN4_IO44FPGA_PMC_CONN4_IO46
FPGA_PMC_CONN4_IO48FPGA_PMC_CONN4_IO50FPGA_PMC_CONN4_IO52FPGA_PMC_CONN4_IO54FPGA_PMC_CONN4_IO56FPGA_PMC_CONN4_IO58FPGA_PMC_CONN4_IO60
FPGA_PMC_CONN4_IO59FPGA_PMC_CONN4_IO57FPGA_PMC_CONN4_IO55FPGA_PMC_CONN4_IO53FPGA_PMC_CONN4_IO51FPGA_PMC_CONN4_IO49FPGA_PMC_CONN4_IO47
FPGA_PMC_CONN4_IO45FPGA_PMC_CONN4_IO43FPGA_PMC_CONN4_IO41FPGA_PMC_CONN4_IO39FPGA_PMC_CONN4_IO37FPGA_PMC_CONN4_IO35FPGA_PMC_CONN4_IO33
PMC_CONN4_IO61
PMC_CONN4_IO31PMC_CONN4_IO33PMC_CONN4_IO35PMC_CONN4_IO37PMC_CONN4_IO39PMC_CONN4_IO41PMC_CONN4_IO43PMC_CONN4_IO45
PMC_CONN4_IO47PMC_CONN4_IO49PMC_CONN4_IO51PMC_CONN4_IO53PMC_CONN4_IO55PMC_CONN4_IO57PMC_CONN4_IO59
PMC_CONN4_IO32PMC_CONN4_IO34PMC_CONN4_IO36
PMC_CONN4_IO40PMC_CONN4_IO42PMC_CONN4_IO44PMC_CONN4_IO46
PMC_CONN4_IO48PMC_CONN4_IO50PMC_CONN4_IO52PMC_CONN4_IO54PMC_CONN4_IO56PMC_CONN4_IO58PMC_CONN4_IO60PMC_CONN4_IO62
NCNC
PMC_CONN4_IO15PMC_CONN4_IO17PMC_CONN4_IO19PMC_CONN4_IO21PMC_CONN4_IO23PMC_CONN4_IO25PMC_CONN4_IO27
AUDIO_BIT_CLKAUDIO_SYNCH
IIC_IRQIIC_SDA
FPGA_PMC_CONN4_IO11FPGA_PMC_CONN4_IO13
FPGA_PMC_CONN4_IO15FPGA_PMC_CONN4_IO17FPGA_PMC_CONN4_IO19FPGA_PMC_CONN4_IO21FPGA_PMC_CONN4_IO23FPGA_PMC_CONN4_IO25
IIC_FPGA_IRQIIC_FPGA_SDAAUDIO_FPGA_CS0AUDIO_FPGA_SYNCH
AUDIO_BIT_FPGA_CLKFPGA_PMC_CONN4_IO9
FPGA_PMC_CONN4_IO27FPGA_PMC_CONN4_IO29
VCC3V3
0402
IO11IO13IO15IO17IO19
IO1
IO21IO23IO25IO27IO29IO31IO33IO35IO37IO39
IO3
IO41IO43IO45IO47IO49IO51IO53IO55IO57IO59
IO5
IO61IO63
IO7IO9
IO60IO58
IO54
IO48IO46
IO32
IO28
IO22IO20
IO52
IO26
IO16IO14
IO24
IO34
IO44
IO56
IO4IO6
IO36
IO40
IO10IO12
IO64
IO42
IO2
IO18
IO30
IO38
IO50
IO62
IO8
MOLEX
PMC_CONN4
IO11IO13IO15IO17IO19
IO1
IO21IO23IO25IO27IO29IO31IO33IO35IO37IO39
IO3
IO41IO43IO45IO47IO49IO51IO53IO55IO57IO59
IO5
IO61IO63
IO7IO9
IO60IO58
IO54
IO48IO46
IO32
IO28
IO22IO20
IO52
IO26
IO16IO14
IO24
IO34
IO44
IO56
IO4IO6
IO36
IO40
IO10IO12
IO64
IO42
IO2
IO18
IO30
IO38
IO50
IO62
IO8
MOLEX
PMC_CONN4
VCC12_N
VCC5 VCC3V3
VCC12_P
IO11IO13IO15IO17IO19
IO1
IO21IO23IO25IO27IO29IO31IO33IO35IO37IO39
IO3
IO41IO43IO45IO47IO49IO51IO53IO55IO57IO59
IO5
IO61IO63
IO7IO9
IO60IO58
IO54
IO48IO46
IO32
IO28
IO22IO20
IO52
IO26
IO16IO14
IO24
IO34
IO44
IO56
IO4IO6
IO36
IO40
IO10IO12
IO64
IO42
IO2
IO18
IO30
IO38
IO50
IO62
IO8
MOLEX
PMC_CONN4
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
BP/GB
21
63 64
6463
1 2
2
Conn1
1
63 64
PMC Connectors
Conn2
Conn4
TOP XRAY VIEW
PMC Connectors
PMC Mounting Holes
PMC_CONN4_IO61 should beused as a clock if clockingis needed for PMC_CONN4
Bank 1/2 (13/14)
ML300 CPU
49 55
MH6MH4MH3MH2
8
62
50
38
30
18
2
42
64
1210
40
36
64
56
44
34
24
1416
26
52
2022
28
32
4648
54
5860
97
6361
5
59575553514947454341
3
39373533312927252321
1
1917151311
PMC_CONN
PMC64
J105
PMC_TP3PCI_PORT_PRS2PCI_PORT_BUS_RST
1113151719
1
21232527293133353739
3
41434547495153555759
5
6163
79
6058
54
4846
32
28
2220
52
26
1614
24
34
44
56
46
36
40
1012
64
42
2
18
30
38
50
62
8
J106
PMC64
PMC_CONN
PMC_CONN4_IO61
PMC_CONN4_IO10
PMC_CONN4_IO62
MH1
8
62
50
38
30
18
2
42
64
1210
40
36
64
56
44
34
24
1416
26
52
2022
28
32
4648
54
5860
97
6361
5
59575553514947454341
3
39373533312927252321
1
1917151311
PMC_CONN
PMC64
J104
PMC_CONN4_IO9AUDIO_PMC_BIT_CLK
12
R6230R
AUDIO_PMC_SDATA_OUTAUDIO_PMC_SDATA_INAUDIO_PMC_RESET_N
AUDIO_PMC_SYNCHAUDIO_PMC_CS0
IIC_PMC_SCLIIC_PMC_SDA
PLB_BUS_ERROROPB_BUS_ERROR
PMC_TP9
PMC_TP5
PMC_TP4
PCI_PORT_ACK64
PCI_PORT_AD14
PMC_IDSEL
PCI_PORT_CBE2
PCI_PORT_BM3
PCI_PORT_PMC_TRST
PCI_PORT_CBE1
PCI_PORT_TRDY
PCI_PORT_PMC_TDIPCI_PORT_PMC_TMS PCI_PORT_PMC_TDO
PCI_PORT_BM4
PCI_PORT_AD29PCI_PORT_AD26
PCI_PORT_AD23PCI_PORT_AD20
PCI_PORT_STOP
PCI_PORT_SERR
PCI_PORT_AD13PCI_PORT_AD10
PCI_PORT_AD07PCI_PORT_AD08
PCI_PORT_PERR
PCI_PORT_AD16PCI_PORT_AD18
PCI_PORT_AD24
PCI_PORT_AD30
PCI_PORT_M66EN
PMC_TP6
PMC_TP7PMC_TP8
PMC_TP10PMC_TP11
PMC_TP12PMC_TP13
PMC_TP14
PMC_IDSEL PCI_PORT_AD17
MH5
PCI_PORT_INTAPCI_PORT_INTC
PMC_TP1PMC_TP2
PCI_PORT_PMC_GNT
PCI_PORT_AD31PCI_PORT_AD27
PCI_PORT_CBE3PCI_PORT_AD21
PCI_PORT_AD17
PCI_PORT_IRDY
PCI_PORT_LOCKPCI_PORT_SBO
PCI_PORT_AD15PCI_PORT_AD11
PCI_PORT_CBE0PCI_PORT_AD05
PCI_PORT_AD03PCI_PORT_AD01
PCI_PORT_REQ64PCI_PORT_AD00PCI_PORT_AD02
PCI_VIO
PCI_PORT_AD04PCI_PORT_AD06
PCI_PORT_AD09PCI_PORT_AD12
PCI_PORT_PARPCI_PORT_SDONE
PCI_PORT_DEVSEL
PCI_PORT_FRAME
PCI_PORT_AD19PCI_PORT_AD22
PCI_PORT_AD25PCI_PORT_AD28
PCI_PORT_PMC_REQ
PCI_PORT_CLK_PMC
PCI_PORT_INTDPCI_PORT_PRS1PCI_PORT_INTB
PCI_PORT_PMC_TCK
PMC_CONN4_IO58
PMC_CONN4_IO54PMC_CONN4_IO56
PMC_CONN4_IO60
PMC_CONN4_IO36
PMC_CONN4_IO18PMC_CONN4_IO16PMC_CONN4_IO14PMC_CONN4_IO12
PMC_CONN4_IO20PMC_CONN4_IO22PMC_CONN4_IO24PMC_CONN4_IO26PMC_CONN4_IO28PMC_CONN4_IO30PMC_CONN4_IO32PMC_CONN4_IO34
PMC_CONN4_IO38PMC_CONN4_IO40PMC_CONN4_IO42PMC_CONN4_IO44PMC_CONN4_IO46PMC_CONN4_IO48PMC_CONN4_IO50PMC_CONN4_IO52
PMC_CONN4_IO57PMC_CONN4_IO55PMC_CONN4_IO53PMC_CONN4_IO51PMC_CONN4_IO49PMC_CONN4_IO47PMC_CONN4_IO45PMC_CONN4_IO43PMC_CONN4_IO41PMC_CONN4_IO39
PMC_CONN4_IO59
PMC_CONN4_IO35PMC_CONN4_IO33PMC_CONN4_IO31PMC_CONN4_IO29PMC_CONN4_IO27PMC_CONN4_IO25PMC_CONN4_IO23PMC_CONN4_IO21
PMC_CONN4_IO11PMC_CONN4_IO13PMC_CONN4_IO15PMC_CONN4_IO17PMC_CONN4_IO19
PMC_CONN4_IO37
VCC5
VCC5
VCC5
VCC3V3
VCC3V3
04020402
0402
0402
VCC3V3
VCC3V3
VCC3V3
0402
S-PBGA-N256PCI4451GFNVCC12
RI_OUT/PME
SUSPEND
SPKROUT
CARDBUSA_CTRDY
CARDBUSA_CBLOCK
CARDBUSA_CAUDIO
CARDBUSA_PAR
PCI_AD31
PCI_RESET
PCI_GBL_RESET
PCI_CLK_RUN
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_CBE3
PCI_CBE2
PCI_CBE1
PCI_CBE0
PCI_PAR
PCI_DEVSEL
PCI_FRAME
PCI_IRDY
PCI_PERR
PCI_REQ
PCI_SERR
PCI_STOP
PCI_TRDY
PCI_INTA
PCI_INTB
PCI_INTC
CARDBUSA_CAD29
CARDBUSA_CAD28
CARDBUSA_CAD27
CARDBUSA_CAD26
CARDBUSA_CAD25
CARDBUSA_CAD24
CARDBUSA_CAD23
CARDBUSA_CAD22
CARDBUSA_CAD21
CARDBUSA_CAD20
CARDBUSA_CAD19
CARDBUSA_CAD18
CARDBUSA_CAD17
CARDBUSA_CAD16
CARDBUSA_CAD15
CARDBUSA_CAD14
CARDBUSA_CAD13
CARDBUSA_CAD12
CARDBUSA_CAD11
CARDBUSA_CAD10
CARDBUSA_CAD09
CARDBUSA_CAD08
CARDBUSA_CAD07
CARDBUSA_CAD06
CARDBUSA_CAD05
CARDBUSA_CAD04
CARDBUSA_CAD03
CARDBUSA_CAD02
CARDBUSA_CAD01
CARDBUSA_CAD00
CARDBUSA_BE2
CARDBUSA_BE1
CARDBUSA_BE0
CARDBUSA_CCD1
CARDBUSA_CCD2
CARDBUSA_CDEVSEL
CARDBUSA_CFRAME
CARDBUSA_CGNT
CARDBUSA_CINT
CARDBUSA_CPERR
CARDBUSA_CREQ
CARDBUSA_CSERR
CARDBUSA_CSTOP
CARDBUSA_CVS1
CARDBUSA_CVS2
CARDBUSA_BE3
CARDBUSA_CRST
CARDBUSA_CCLKRUN
CARDBUSB_CRST
CARDBUSB_CCLKRUN
CARDBUSB_CAD30
CARDBUSB_CAD29
CARDBUSB_CAD28
CARDBUSB_CAD27
CARDBUSB_CAD26
CARDBUSB_CAD25
CARDBUSB_CAD24
CARDBUSB_CAD23
CARDBUSB_CAD22
CARDBUSB_CAD21
CARDBUSB_CAD20
CARDBUSB_CAD18
CARDBUSB_CAD17
CARDBUSB_CAD16
CARDBUSB_CAD15
CARDBUSB_CAD14
CARDBUSB_CAD13
CARDBUSB_CAD11
CARDBUSB_CAD09
CARDBUSB_CAD08
CARDBUSB_CAD07
CARDBUSB_CAD06
CARDBUSB_CAD05
CARDBUSB_CAD04
CARDBUSB_CAD03
CARDBUSB_CAD02
CARDBUSB_CAD01
CARDBUSB_CAD00
CARDBUSB_BE3
CARDBUSB_BE2
CARDBUSB_BE1
CARDBUSB_BE0
CARDBUSB_PAR
CARDBUSB_CAUDIO
CARDBUSB_CBLOCK
CARDBUSB_CCD1
CARDBUSB_CCD2
CARDBUSB_CDEVSEL
CARDBUSB_CFRAME
CARDBUSB_CGNT
CARDBUSB_CINT
CARDBUSB_CIRDY
CARDBUSB_CPERR
CARDBUSB_CREQ
CARDBUSB_CSERR
CARDBUSB_CSTOP
CARDBUSB_CSTSCHG
CARDBUSB_CTRDY
CARDBUSB_CVS1
CARDBUSB_CVS2
PHY1394_DATA7PHY1394_DATA6PHY1394_DATA5PHY1394_DATA4PHY1394_DATA3PHY1394_DATA2PHY1394_DATA1PHY1394_DATA0
PHY1394_CLKPHY1394_LREQ
PHY1394_LINKONPHY1394_LPS
PHY1394_CTL0
CARD_PWRSW_CLOCK
CARD_PWRSW_DATA
CARD_PWRSW_LATCH
IIC_SDA
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IIC_SCL
IRQSER
ZV_Y7
ZV_Y6
ZV_Y5
ZV_Y4
ZV_Y3
ZV_Y2
ZV_Y1
ZV_Y0
ZV_UV7
ZV_UV6
ZV_UV5
ZV_UV4
ZV_UV3
ZV_UV2
ZV_UV1
ZV_UV0
ZV_HREF
ZV_VSYNC
ZV_PCLK
ZV_SCLK
ZV_MCLK
ZV_LRCLK
ZV_SDATA
CLAMP_PCI_VCCP1CLAMP_PCI_VCCP2
CLAMP_CARDBUSA_VCCA1CLAMP_CARDBUSA_VCCA2CLAMP_CARDBUSA_VCCA3
CLAMP_CARDBUSB_VCCB1CLAMP_CARDBUSB_VCCB2
VCC2VCC3VCC4VCC5VCC6VCC7VCC8VCC9VCC10
VCC1
GND1GND2GND3GND4GND5GND6GND7GND8GND9GND10GND11GND12GND13
CARDBUSA_CSTSCHG
CARDBUSA_CCLK
CARDBUSA_RSVD_DATA2
CARDBUSA_RSVD_ADDR18
CARDBUSB_CCLK
CARDBUSB_RSVD_DATA2
CARDBUSB_RSVD_ADDR18
VCC11
PCI_CLK
PCI_GNT
PCI_LOCK
PHY1394_CTL1
CARDBUSA_CAD31
CARDBUSA_CAD30
CARDBUSA_CIRDY
CARDBUSB_CAD19
CARDBUSB_CAD12
CARDBUSB_CAD31
CARDBUSB_RSVD_DATA14
CARDBUSA_RSVD_DATA14
CARDBUSB_CAD10
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
PCI 3VPCI 5V
PCI 3VPCI 5V
Default
Default
UPPER
LOWER
CLOSEDOPEN
OPENCLOSED
CLOSEDOPENCLOSED
OPEN
CLOSEDOPEN
E601
5V Exxx
CardBus
Pg 8/9
Bnk 1/2
GB
CardBus to PCI Bridge
E601 OPENCLOSED
3V Exxx
E603E603
E605E605
E602E602
E604E604
E606E606
What
FPGAFPGA
LOWER
UPPER
DefaultPCI 3VPCI 5V
DO NOT STUFF
PCI 2
50 55
U15
Y13
U11
V11
E2
D2
M1
C2
L18
K19
Y12
K18
L19
M20
M19
M18
M17
N20
N19
P18
R20
R19
P17
R18
T20
T19
T18
Y19
W18
V17
U16
Y18
W17
V16
Y17
V15
U14
Y16
W15
Y15
W14
Y14
V13
N18
U20
V18
W16
W19
U19
V20
T17
W20
L20
Y20
V19
U18
W11
Y11
Y10
N3
N2
N1
K1
K3
K2
J2
J4
H1
H3
G2
G3
F1
A2
B3
B2
D5
C4
A3
B4
C5
C6
D7
C7
B6
B7
A6
C8
A7
B8
F2
C3
A4
A8
M4
D1
G4
C1
L2
D3
J3
L3
E4
L1
G1
J1
H2
M3
B15
A10
B9A9D10
C10
C12
D12
A13
A14
C14
A15
D14
B16
C16
E17
D19
C20
D20
F18
E20
G18
F20
H18
G20
H20
H19
J18
J17
J19
C13
A17
D18
F19
B20
C11
C18
J20
B10
B18
A18
A19
A12
D16
B19
B14
B11
A20
A11
C17
B12
C15
V9U9Y8W8V8Y7W7V7V6Y5Y6W5
U7
U12
V12
W12
Y9
V10
W9V5Y4
W10
W13
V1U2T3U1T2R3P4T1Y2W2Y1W1V3U3V2T4P3R2Y3
W3W4V4U5
P19V14
B5F3L4
B13E19
D11D15F4F17K4L17R4R17U6
D6
A1D4D8D13D17H4H17N4N17U4U8U13U17
M2
E3
P2
B1
B17
C9
C19
U10
K17
K20
P20
W6
R1
P1
E1
A16
E18
G17
D9
G19
A5
U601
1 2
R6270R
NC
NCNC
CARDBUSB_CAD30
2151.1RR625
1 2
R62651.1R
1 2
R6244.70K 21
R6284.70K
PCI_FPGA_CB_IRQSER
PCI_PORT_AD07
PCI_PORT_AD09
PCI_PORT_CLK_CB
PHY1394_CTL0
PHY1394_DATA0
PHY1394_DATA1
PHY1394_DATA4
PHY1394_DATA5
PHY1394_DATA6
CARDBUSB_CCD2
CARDBUSA_CCD1
CARDBUSA_CCD2
PCI_PORT_CB_GNT
PCI_PORT_CB_REQ
CB_IDSEL_LOCK
PCI_PORT_AD18
PHY1394_LPS
CB_IDSEL_LOCK
PCI_FPGA_CB_SUSPEND
CARDBUSB_CVS1
CARDBUSA_CVS1
CARDBUSA_CSERR
CARDBUSA_CINT
CARDBUSA_CAD5
CARDBUSA_CAD6
CARDBUSA_CAD8
CARDBUSA_CAD16
CARDBUSA_CAD17
CARDBUSA_CAD18
CARDBUSA_CAD20
CARDBUSA_CAD21
CARDBUSA_CAD27
CARDBUSA_CAD31
PCI_IIC_SCL
PCI_IIC_SDA
IIC_SCL CARD_PWRSW_LATCH
CARD_PWRSW_OC
PCI_IIC_SDA
CARDBUSB_RSV_A18
PCI_PORT_GBL_RST
PCI_PORT_BUS_RST
PCI_PORT_CLKRUN
PCI_PORT_AD31
PCI_PORT_AD30
PCI_PORT_AD29
PCI_PORT_AD28
PCI_PORT_AD27
PCI_PORT_AD26
PCI_PORT_AD25
PCI_PORT_AD24
PCI_PORT_AD23
PCI_PORT_AD22
PCI_PORT_AD21
PCI_PORT_AD20
PCI_PORT_AD19
PCI_PORT_AD18
PCI_PORT_AD17
PCI_PORT_AD16
PCI_PORT_AD15
PCI_PORT_AD14
PCI_PORT_AD13
PCI_PORT_AD12
PCI_PORT_AD11
PCI_PORT_AD10
PCI_PORT_AD08
PCI_PORT_AD06
PCI_PORT_AD05
PCI_PORT_AD04
PCI_PORT_AD03
PCI_PORT_AD02
PCI_PORT_AD01
PCI_PORT_AD00
PCI_PORT_INTA
PCI_PORT_INTB
PCI_PORT_INTC
CARDBUSA_RSV_A18
CARDB_VIO
CARDA_VIO
1
2
BOWTIE_CLOSED
E602
2
1
BOWTIE_OPENE601
PCI_VIO
PHY1394_CTL1
CARDBUSB_RSV_D14
CARDBUSB_RSV_D2
CARDBUSB_CCLK
CARDBUSB_CRST
CARDBUSB_CCLKRUN
CARDBUSB_CAD31
CARDBUSB_CAD29
CARDBUSB_CAD28
CARDBUSB_CAD27
CARDBUSB_CAD26
CARDBUSB_CAD25
CARDBUSB_CAD24
CARDBUSB_CAD23
CARDBUSB_CAD22
CARDBUSB_CAD21
CARDBUSB_CAD20
CARDBUSB_CAD19
CARDBUSB_CAD18
CARDBUSB_CAD17
CARDBUSB_CAD11
CARDBUSB_CAD12
CARDBUSB_CAD13
CARDBUSB_CAD14
CARDBUSB_CAD15
CARDBUSB_CAD16
CARDBUSB_CAD10
CARDBUSB_CAD9
CARDBUSB_CAD8
CARDBUSB_CAD7
CARDBUSB_CAD6
CARDBUSB_CAD5
CARDBUSB_CAD4
CARDBUSB_CAD3
CARDBUSB_CAD2
CARDBUSB_CAD1
CARDBUSB_CAD0
CARDBUSB_CCBE3
CARDBUSB_CCBE2
CARDBUSB_CCBE1
CARDBUSB_CAUDIO
CARDBUSB_CCD1
CARDBUSB_CVS2
CARDBUSA_RSV_D14
CARDBUSA_RSV_D2
CARDBUSB_CTRDY
CARDBUSB_CSTSCHG
CARDBUSB_CSTOP
CARDBUSB_CSERR
CARDBUSB_CREQ
CARDBUSB_CPERR
CARDBUSB_CBLOCK
CARDBUSB_CDEVSEL
CARDBUSB_CGNT
CARDBUSB_CINT
CARDBUSB_CIRDY
CARDBUSB_CCBE0
CARDBUSB_CPAR
PHY1394_DATA7
PHY1394_DATA3
PHY1394_DATA2
PHY1394_CLK
PHY1394_LREQ
PHY1394_LINKON
CARDB_VIO
1
2
E603
BOWTIE_OPEN
2
1
E604
BOWTIE_CLOSED
CARDA_VIO
1
2
E606
BOWTIE_CLOSED
2
1
E605
BOWTIE_OPEN
PCI_VIO
PCI_PORT_TRDY
PCI_PORT_STOP
PCI_PORT_SERR
PCI_PORT_PERR
PCI_PORT_IRDY
PCI_PORT_FRAME
PCI_PORT_DEVSEL
PCI_PORT_PAR
PCI_PORT_CBE0
PCI_PORT_CBE1
PCI_PORT_CBE2
PCI_PORT_CBE3
CARD_PWRSW_STBY
PCI_IIC_SCL
PCI_SPKROUT
CARD_PWRSW_CLOCK
CARD_PWRSW_DATA
IIC_SDA
CARDBUSA_CAUDIO
CARDBUSA_CFRAME
CARDBUSA_CVS2
CARDBUSA_CTRDY
CARDBUSA_CSTSCHG
CARDBUSA_CSTOP
CARDBUSA_CREQ
CARDBUSA_CPERR
CARDBUSA_CBLOCK
CARDBUSA_CDEVSEL
CARDBUSA_CGNT
CARDBUSA_CIRDY
CARDBUSA_CCLK
CARDBUSA_CRST
CARDBUSA_CCLKRUN
CARDBUSA_CAD30
CARDBUSA_CAD29
CARDBUSA_CAD28
CARDBUSA_CAD26
CARDBUSA_CAD25
CARDBUSA_CAD24
CARDBUSA_CAD23
CARDBUSA_CAD22
CARDBUSA_CAD19
CARDBUSA_CAD11
CARDBUSA_CAD12
CARDBUSA_CAD13
CARDBUSA_CAD14
CARDBUSA_CAD15
CARDBUSA_CAD10
CARDBUSA_CAD9
CARDBUSA_CAD7
CARDBUSA_CAD4
CARDBUSA_CAD3
CARDBUSA_CAD2
CARDBUSA_CAD1
CARDBUSA_CAD0
CARDBUSA_CCBE3
CARDBUSA_CCBE2
CARDBUSA_CCBE1
CARDBUSA_CCBE0
CARDBUSA_CPAR
PCI_PORT_LOCK
CARDBUSB_CFRAME
NCNC
NCNCNCNC
NCNCNCNC
NCNCNC
NC
NCNCNC
NCNCNC
NCNC
NC
AD0_CA02
AD11_CA09
AD12_CA10
AD14_CA11
AD18_CA22
AD1_CA03
AD20_CA23
AD21_CA24
AD22_CA25
AD23_CA26
AD24_CA27
AD25_CA28
AD26_CA29
AD27_CA30
AD3_CA04
AD5_CA05
AD7_CA06
AD9_CA08
CA35_GND
CA36_CD1#
CA37_AD2
CA38_AD4
CA39_AD6
CA40_RSRVD_D14
CA41_AD8
CA42_AD10
CA43_VS1
CA44_AD13
CA45_AD15
CA46_AD16
CA47_RSRVD_A18
CA48_BLOCK#
CA49_STOP#
CA50_DEVSEL#
CA51_VCC
CA52_VPP2
CA53_TRDY#
CA54_FRAME#
CA55_AD17
CA56_AD19
CA57_VS2
CA58_RST#
CA59_SERR#
CA60_REQ#
CA61_CAE3#
CA62_AUDIO
CA63_STSCHG
CA64_AD28
CA65_AD30
CA66_AD31
CA67_CD2#
CA68_GND
CAE0#_CA07
CAE1#_CA12
CAE2#_CA21
CLKRUN#_CA33
CLK_CA19
GND_CA01
GND_CA34
GNT#_CA15
INT#_CA16
IRDY#_CA20
PAR_CA13
PERR#_CA14
PAGND1
PAGND10
PAGND11
PAGND12
PAGND13
PAGND14
PAGND15
PAGND16
PAGND17
PAGND18
PAGND19
PAGND2
PAGND20
PAGND21
PAGND22
PAGND23
PAGND24
PAGND25
PAGND26
PAGND27
PAGND28
PAGND29
PAGND3
PAGND30
PAGND31
PAGND32
PAGND4
PAGND5
PAGND6
PAGND7
PAGND8
PAGND9
VCC_CA17
VPP1_CA18
D2_RSRVD_CA32
AD29_CA31
CARDBUS_CONN
Upper Slot
SHIELD207
SHIELD205
AD0_CB02
AD11_CB09
AD12_CB10
AD14_CB11
AD18_CB22
AD1_CB03
AD20_CB23
AD21_CB24
AD22_CB25
AD23_CB26
AD24_CB27
AD25_CB28
AD26_CB29
AD27_CB30
AD3_CB04
AD5_CB05
AD7_CB06
AD9_CB08
CB35_GND
CB36_CD1#
CB37_AD2
CB38_AD4
CB39_AD6
CB40_RSRVD_D14
CB41_AD8
CB42_AD10
CB43_VS1
CB44_AD13
CB45_AD15
CB46_AD16
CB47_RSRVD_A18
CB48_BLOCK#
CB49_STOP#
CB50_DEVSEL#
CB51_VCC
CB52_VPP2
CB53_TRDY#
CB54_FRAME#
CB55_AD17
CB56_AD19
CB57_VS2
CB58_RST#
CB59_SERR#
CB60_REQ#
CB61_CBE3#
CB62_AUDIO
CB63_STSCHG
CB64_AD28
CB65_AD30
CB66_AD31
CB67_CD2#
CBE0#_CB07
CBE1#_CB12
CBE2#_CB21
CLKRUN#_CB33
CLK_CB19
GND_CB01
GND_CB34
GNT#_CB15
INT#_CB16
IRDY#_CB20
PAR_CB13
PERR#_CB14
PBGND1
PBGND10
PBGND11
PBGND12
PBGND13
PBGND14
PBGND15
PBGND16
PBGND17
PBGND18
PBGND19
PBGND2
PBGND20
PBGND21
PBGND22
PBGND23
PBGND24
PBGND25
PBGND26
PBGND27
PBGND28
PBGND29
PBGND3
PBGND30
PBGND31
PBGND32
PBGND4
PBGND5
PBGND6
PBGND7
PBGND8
PBGND9
VCC_CB17
VPP1_CB18
D2_RSRVD_CB32
AD29_CB31
CB68_GND
SHIELD208
SHIELD206
CARDBUS_CONN
Lower SLOT
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
ML300 CPU
BP/GB
Notes:
A34
A68
B68
FRONT VIEW
LOWER CARD SLOT
EJ
EJ
B34B1
A1
B35
A35
PCB
UPPER CARD SLOT
Cardbus Conn
CardBus Connectors
PCI Bridge
1. Power Supply for CardBus found on page 53.
51 55
102
112
114
115
133
103
134
136
137
139
140
142
143
145
105
106
108
111
151
152
153
155
156
158
159
161
162
164
165
167
168
170
171
173
174
177
178
180
181
183
184
186
187
189
190
192
193
195
196
198
199
200
109
117
131
149
128
101
150
121
123
130
118
120
104
129
132
135
138
141
144
147
154
157
160
107
163
166
169
172
175
176
179
182
185
188
110
191
194
197
113
116
119
122
125
126
124
127
148
146
206208
207205
P110
PKG_TYPE=FCI71240-340CA
CARDBUS_SHIELD 21
1000_OHMFB601
IND_BLM21A
2 12
14
15
33
3 34
36
37
39
40
42
43
45
5 6 8 11
51
52
53
55
56
58
59
61
62
64
65
67
68
70
71
73
74
77
78
80
81
83
84
86
87
89
90
92
93
95
96
98
99
100
9 17
31
49
28
1 50
21
23
30
18
20
4 29
32
35
38
41
44
47
54
57
60
7
63
66
69
72
75
76
79
82
85
88
10
91
94
97
13
16
19
22
25
26
24
27
48
46
P110
PKG_TYPE=FCI71240-340CA
CARDBUSB_CCLK
CARDBUSB_CPAR
CARDBUSB_CREQ
CARDBUSB_CFRAME
CARDBUSB_CBLOCK
CARDBUSB_CCBE0
CARDBUSB_CAD28
CARDBUSB_CAD24
CARDBUSB_CAD20
CARDBUSB_CAD16
CARDBUSB_CAD12
CARDBUSB_CAD8
CARDBUSB_CAD4
CARDBUSB_RSV_D14
CARDBUSB_CAD3
CARDBUSB_CAD0
CARDBUSB_CCD1
CARDBUSB_CAD29
CARDBUSB_RSV_D2
CARDBUSB_CVPP
CARDBUSB_CVCC
CARDBUSB_CPERR
CARDBUSB_CIRDY
CARDBUSB_CINT
CARDBUSB_CGNT
CARDBUSB_CCLKRUN
CARDBUSB_CCBE2
CARDBUSB_CCBE1
CARDBUSB_CCD2
CARDBUSB_CAD31
CARDBUSB_CAD30
CARDBUSB_CSTSCHG
CARDBUSB_CAUDIO
CARDBUSB_CCBE3
CARDBUSB_CSERR
CARDBUSB_CRST
CARDBUSB_CVS2
CARDBUSB_CAD19
CARDBUSB_CAD17
CARDBUSB_CTRDY
CARDBUSB_CVPP
CARDBUSB_CVCC
CARDBUSB_CDEVSEL
CARDBUSB_CSTOP
CARDBUSB_RSV_A18
CARDBUSB_CAD15
CARDBUSB_CAD13
CARDBUSB_CVS1
CARDBUSB_CAD10
CARDBUSB_CAD6
CARDBUSB_CAD2
CARDBUSB_CAD9
CARDBUSB_CAD7
CARDBUSB_CAD5
CARDBUSB_CAD27
CARDBUSB_CAD26
CARDBUSB_CAD25
CARDBUSB_CAD23
CARDBUSB_CAD22
CARDBUSB_CAD21
CARDBUSB_CAD1
CARDBUSB_CAD18
CARDBUSB_CAD14
CARDBUSB_CAD11
CARDBUS_SHIELD
CARDBUSA_RSV_A18
CARDBUSA_CREQ
CARDBUSA_CFRAME
CARDBUSA_CBLOCK
CARDBUSA_CAD28
CARDBUSA_CAD16
CARDBUSA_CAD8
CARDBUSA_CAD4
CARDBUSA_RSV_D14
CARDBUSA_CCD1
CARDBUSA_CCD2
CARDBUSA_CAD31
CARDBUSA_CAD30
CARDBUSA_CSTSCHG
CARDBUSA_CAUDIO
CARDBUSA_CCBE3
CARDBUSA_CSERR
CARDBUSA_CRST
CARDBUSA_CVS2
CARDBUSA_CAD19
CARDBUSA_CAD17
CARDBUSA_CTRDY
CARDBUSA_CVPP
CARDBUSA_CVCC
CARDBUSA_CDEVSEL
CARDBUSA_CSTOP
CARDBUSA_CAD15
CARDBUSA_CAD13
CARDBUSA_CVS1
CARDBUSA_CAD10
CARDBUSA_CAD6
CARDBUSA_CAD2
CARDBUSA_CCLK
CARDBUSA_CPAR
CARDBUSA_CCBE0
CARDBUSA_CAD24
CARDBUSA_CAD20
CARDBUSA_CAD12
CARDBUSA_CAD3
CARDBUSA_CAD0
CARDBUSA_CAD29
CARDBUSA_RSV_D2
CARDBUSA_CVPP
CARDBUSA_CVCC
CARDBUSA_CPERR
CARDBUSA_CIRDY
CARDBUSA_CINT
CARDBUSA_CGNT
CARDBUSA_CCLKRUN
CARDBUSA_CCBE2
CARDBUSA_CCBE1
CARDBUSA_CAD9
CARDBUSA_CAD7
CARDBUSA_CAD5
CARDBUSA_CAD27
CARDBUSA_CAD26
CARDBUSA_CAD25
CARDBUSA_CAD23
CARDBUSA_CAD22
CARDBUSA_CAD21
CARDBUSA_CAD1
CARDBUSA_CAD18
CARDBUSA_CAD14
CARDBUSA_CAD11
EXB-E10C
VCC3V3
EXB-E10C
EXB-E10C EXB-E10C EXB-E10C
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
PCI Termination
BP
PCI Termination
ML300 CPU
52 56
12
4.70K
R659
0402
12
4.70K
R647
0402
21
4.70K
R675
0402
12
R649 DNP
0402
61
7 52 3 4 10
98
RP6064.7K
8 9 10
432 57
1 6
4.7KRP605
NC
PCI_PORT_CLKRUN
PCI_PORT_PMC_TMS
PCI_PORT_PMC_TDI
PCI_PORT_PMC_TRST
CARDBUSA_CCD1
CARDBUSA_CCD2
CARDBUSB_CCD1
CARDBUSB_CCD2
PCI_PORT_GBL_RST
PCI_PORT_BUS_RST
PCI_PORT_BM4
PCI_PORT_BM3
PCI_PORT_PRS2
PCI_PORT_PRS1
PCI_PORT_SBO
61
7 52 3 4 10
98
RP6044.7K
PCI_PORT_PAR
PCI_PORT_CB_GNT
PCI_PORT_CB_REQ
PCI_PORT_PMC_GNT
PCI_PORT_PMC_REQ
PCI_PORT_INTA
PCI_PORT_INTB
PCI_PORT_ACK64
PCI_PORT_REQ64
PCI_PORT_INTD
8 9 10
432 57
1 6
4.7KRP602
PCI_PORT_M66EN
PCI_PORT_PMC_TCK
PCI_PORT_CBE2
PCI_PORT_IRDY
PCI_PORT_CBE0
PCI_PORT_CBE1
8 9 10
432 57
1 6
RP6014.7K
PCI_PORT_FRAME
PCI_PORT_TRDY
PCI_PORT_STOP
PCI_PORT_DEVSEL
PCI_PORT_LOCK
PCI_PORT_PERR
PCI_PORT_SERR
PCI_PORT_CBE3
PCI_PORT_INTC
PCI_PORT_SDONE
NC
0402
VCC5VCC12_P
VCC12_P VCC5
C
VCC3V3
VCC3V3
VCC3V3
0402
A
VCC3V3
BB
SM
2961666671FERRITE_BD
2961666671FERRITE_BD
SM
5VB
5VC
5VA
MODEDATACLOCKLATCHRESETRESET_NSTBY_NOC_N
NC1
BVCC3BVCC2BVCC1BVPP
12VB
12VA
AVCC3AVCC2AVCC1AVPP
GND
3.3VC
3.3VB
3.3VA
NC2NC3NC4NC5NC6NC7
TPS2216A
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
ML300 CPU
Power Supply
BP
CardBus Power Supply
Place Near VCCIO PCI pins on U601
Place Near VCC Pins of U601
Place Near 12VX of U58 Place Near 3.3VX of U58Place Near 5VX of U58
53 55
1 232
304567141920
3
21222324
25
8
1211109
13
16
17
18
152627282931
U58DAP32
1 2
2961666671FB602
L1210
21
FB603
L1812
1 2
L1812
FB605
1 2
2961666671FB604
L1210
1
2
0.1UFC1013
0402
1
2
0.1UFC1015
0402 2
1 C10210.1UF
0402
1
2
0.1UFC1025
0402
CARDB_VIO
2
1 C10260.1UF
0402
1
2
0.1UFC679
0402
2
10.1UFC676
04022
1 C67333UF
2
1 C6810.1UF
04022
1 C67533UF
2
1 C6770.1UF
0402
1
2
0.1UFC680
0402 2
1 C10270.1UF
0402
1
2
0.1UFC1022
0402
1
2
0.1UFC1023
04022
1 C10240.1UF
04022
1 C10190.1UF
0402
1
2
0.1UFC1018
0402
1
2
0.1UFC1020
04022
1 C10170.1UF
0402
1
2
0.1UFC1016
04022
1 C10140.1UF
0402
1
2
0.22UFC682
2
1 C6780.22UF
2
1 C102810UF
21R629
1.00K
CARD_PWRSW_MODE
NC
CARD_PWRSW_RESET_TP
CARD_PWRSW_DATA
CARDBUSA_CVCC
CARDBUSA_CVPP
CARDBUSB_CVPP
CARDBUSB_CVCC
1
TP650
1
2
C67410UF
PCI_PORT_BUS_RST
CARDA_CVCC
CARDB_CVPP
CARDB_CVCC
CARDA_CVPP
CARD_PWRSW_LATCH
CARD_PWRSW_STBYCARD_PWRSW_OC
NC
NCNC
NCNC
NC
CARD_PWRSW_CLOCK1
243.0K
R676
PCI_VIO
CARDA_VIO
VCC12_PVCC3V3
MA_506
CTCB1210-600-SSM
CTCB1210-600-SSM
0402
0402
0402
0402
0402
0402
VCC3V3
VCC3V3
0402
0402
TPA1+
TPA1-
TPB1+
TPB1-
TPBIAS
R0
R1
CPS
PC0
PC1
PC2
RESET
PD
PHY_LREQ
PHY_CLK
PHY_CTL0
PHY_CTL1
PHY_D0
PHY_D1
PHY_D2
PHY_D3
PHY_D4
PHY_D5
PHY_D6
PHY_D7
PHY_LPS
PHY_LINKON
ISO
TESTM
SE
SM
FILTER0
FILTER1
XO
XI
DVDD1
DVDD2
AGND1
AGND2
AGND3
DGND1
DGND2
DGND3
AVDD1
AVDD2DVDD3
PLLGND
PLLVDD
TSB41AB1PHP
0402
TPA+
TPA-
TPB+ VG
VP
TPB-
SHIELD
A B
SMT
SELF HEALING
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
ML300 CPU
GB
IEEE1394 (FireWire) PHY
IEEE1394 PHY
Cardbus Bridge
54 55
1
2
D605
1N5819
MELF
1 2
F601
2920
6
5
4 2
1
3
7 1098
P108
CONN1394A
125%10.0K
R642
0402
12
R640
0R
1 2
C6980.1UF
0402
2 11%6.34K
R637
0402
1 2
12PFC684
0402
21
12PFC683
0402
2
1220PFC685
0402
21
C6900.1UF
0402
1
2
C6970.1UF
0402 2
1 C6960.01UF
0402
1
2
1000PFC695
04022
1 C6941000PF
0402
1
2
C6930.1UF
0402
2
10.01UFC691
0402
1
2
C6921000PF
0402
1
2
C6860.01UF
0402 2
11000PFC687
0402
2
1 C6880.01UF
0402
1
2
C6890.01UF
0402
2 1
R64110.0K 5%
0402
12
R6381.00K 5%
0402
12
R6451.00K 5%
0402
2 1
R6441.00K 5%
040212
5%1.00KR643
0402
30
29
28
27
31
33
34
20
16
17
18
37
12
48
1
2
3
4
5
6
7
8
9
10
11
13
15
19
22
23
24
38
39
43
42
21
45
26
32
36
14
47
46
25
3544
41
40
U59
12
R632
5.10K
PHY1394_CPS
PHY1394_XO
PHY1394_XI
FW_PLL_AVDD
PHY1394_SM
PHY1394_SE
PHY1394_TESTM
PHY1394_ISO_N
PHY1394_RESET_N
PHY1394_PC2
PHY1394_PC1
PHY1394_PC0
21R639
1.00K
211M
R633
12
56.2R
R630
2156.2R
R631
12
56.2R
R636
21R635
56.2R
1 2
R634402K
1 2
FB607L1210
1 2
FB606L1210
X601
24.576MHZ
PHY1394_LREQ
PHY1394_TPBIAS
IEEE1394_AVDD
PHY1394_CLK
PHY1394_CTL0
PHY1394_CTL1
PHY1394_DATA0
PHY1394_DATA1
PHY1394_DATA2
PHY1394_DATA3
PHY1394_DATA4
PHY1394_DATA5
PHY1394_DATA6
PHY1394_DATA7
PHY1394_LPS
PHY1394_LINKON
PHY1394_POWER
PHY1394_TPB1_M
PHY1394_TPB1_P
PHY1394_TPA1_M
PHY1394_TPA1_P
VCC3V3
VCC5VCC5
VCC12_N
VCC12_P
VCC2V5VCC1V5VTTDDR
B B B
VCC3V3 VCC5
B
HDR2x32
HDR_2x25
VCC12_P
VCC3V3 VCC3V3
VCC12_NVCC12_P
HDR2x32
B
VCC2V5
B
C
C
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
Silkscreen:
ML300 CPU
Mezz Connector
BP
Mezzanine Power and I/O Connectors
Silkscreen:
Place Caps adjacent to J702
Powerboard Mounting Holes
Fabrication Fiducials
Three per Side
"Digital Conn 2"Silkscreen:"Digital Conn 1"
"Power Conn"
55 55
MH10JACK_116_280
MH9JACK_116_280
MH8JACK_116_280
MH7JACK_116_280
1GND-TURRET
GND2
1
GND1
GND-TURRET
FPGA_GPIO_24
FPGA_GPIO_[00:31]
FPGA_GPIO_31
FPGA_GPIO_20
FPGA_GPIO_25
FPGA_GPIO_23FPGA_GPIO_22FPGA_GPIO_21
FPGA_GPIO_19FPGA_GPIO_18FPGA_GPIO_17FPGA_GPIO_16FPGA_GPIO_15
FPGA_GPIO_02
FPGA_GPIO_00FPGA_GPIO_01
FPGA_GPIO_03FPGA_GPIO_04FPGA_GPIO_05FPGA_GPIO_06FPGA_GPIO_07FPGA_GPIO_08FPGA_GPIO_09FPGA_GPIO_10FPGA_GPIO_11FPGA_GPIO_12FPGA_GPIO_13FPGA_GPIO_14
FPGA_GPIO_30FPGA_GPIO_29FPGA_GPIO_28FPGA_GPIO_27FPGA_GPIO_26
FID4FID1
IIC_CRIT_A
2
110UFC796
1
2
C79710UF
2
1 C79533UF
TOUCH_CS_N
124
.70K
R702
0402
2
1 04020.1UFC809
2
1 04020.1UFC8071
2
47UFC793
1
2C8080.1UF
04021
2C8060.1UF
04021
2C8040.1UF
0402
FPGA_PWR_SIG_N
6163
987
646260
6
59585756555453525150
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J102
SYSACE_RESET_N
NC
NC
NC
FPGA_CPU_RESET
VCC2V5
9876
50
5
49484746454443424140
4
39383736353433323130
3
29282726252423222120
2
19181716151413121110
1
J103
1
1011 1213 1415 1617 1819
2
2021 2223 2425 2627 2829
3
3031 3233 3435 3637 3839
4
4041 4243 4445 4647 4849
5
5051 5253 5455 5657 5859
6
606264
7 89
6361
J101
2
1 C79447UF
2
1 C79247UF
1
2
47UFC791
2
1 C79047UF
TFT_LCD_DE
TFT_LCD_HSYNCTFT_LCD_CLK
TFT_LCD_B5
TFT_LCD_VSYNC
TFT_LCD_B0TFT_LCD_G5
TFT_LCD_R4TFT_LCD_R3
TFT_LCD_R0
TFT_LCD_B3
TFT_LCD_R1TFT_LCD_R2
TFT_LCD_B1
TFT_LCD_B4
TFT_LCD_B2
TFT_LCD_G3
TFT_LCD_G1TFT_LCD_G0
TFT_LCD_G4
TFT_LCD_G2
TFT_LCD_R5
TFT_LCD_DPS
SYSACE_CFGADDR2SYSACE_CFGADDR1SYSACE_CFGADDR0
VCC1V5
VCC2V5
VCC1V5
PLB_BUS_ERROROPB_BUS_ERRORFPGA_CPU_RESET
FPGA_PROG_B
DONE_LEDSYSACE_ERRLEDSYSACE_STATLED
NC
NC
NC
NC
PMC_CONN4_IO62
PMC_CONN4_IO36
PMC_CONN4_IO58
PMC_CONN4_IO18PMC_CONN4_IO16PMC_CONN4_IO14PMC_CONN4_IO12PMC_CONN4_IO10
PMC_CONN4_IO20PMC_CONN4_IO22PMC_CONN4_IO24PMC_CONN4_IO26PMC_CONN4_IO28PMC_CONN4_IO30PMC_CONN4_IO32PMC_CONN4_IO34
PMC_CONN4_IO38PMC_CONN4_IO40PMC_CONN4_IO42PMC_CONN4_IO44PMC_CONN4_IO46PMC_CONN4_IO48PMC_CONN4_IO50
PMC_CONN4_IO54PMC_CONN4_IO56
PMC_CONN4_IO60
PMC_CONN4_IO52
IIC_PMC_SCLPMC_CONN4_IO61
PMC_CONN4_IO57PMC_CONN4_IO55PMC_CONN4_IO53PMC_CONN4_IO51PMC_CONN4_IO49PMC_CONN4_IO47PMC_CONN4_IO45PMC_CONN4_IO43PMC_CONN4_IO41PMC_CONN4_IO39
PMC_CONN4_IO35PMC_CONN4_IO33PMC_CONN4_IO31PMC_CONN4_IO29PMC_CONN4_IO27PMC_CONN4_IO25PMC_CONN4_IO23PMC_CONN4_IO21
PMC_CONN4_IO9PMC_CONN4_IO11PMC_CONN4_IO13PMC_CONN4_IO15PMC_CONN4_IO17PMC_CONN4_IO19
PMC_CONN4_IO59
PMC_CONN4_IO37
IIC_PMC_SDA
2
1 04020.1UFC805
TOUCH_IRQ_NTOUCH_DOUTTOUCH_BUSYTOUCH_DINTOUCH_DCLK
FID2 FID3 FID6FID5
1
GND3
GND-TURRET
ofSheet
Date:
Title:
Ver:A
B
C
D
1234
D
C
B
A
4 3 2 1
Sheet Size: B Rev:
Drawn By
1.00October 17th, 2002
ML300_CPU
SCH: 0381135ASM: 0431182PCB: 1280285
A
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BP
| Net Class Routing Rules |
| 1 | NET_CLASS | DDR_CNTL_FPGA + DDR_CNTL_RES | < 6000 mils | thru resistors | + ignore tracelength to termination resistor |
| 14 | NET_CLASS | CPU_TRACE | Matched Length +/- 50 mil | Tight |
| 16 | NET_CLASS | SYSACE_MPU | Tight | | Tight || 17A | NET_CLASS | SYSACE_JTAG_2V5 | Tight | | Tight || 17B | NET_CLASS | SYSACE_JTAG_3V3 | Tight | | Tight || 18 | Deleted to remove redundancy | | | || 19 | NET_CLASS | TFT_CNTL_FPGA | Tight | | These go from the FPGA to a level shifter || 20 | NET_CLASS | TFT_CNTL_LCD | Tight | | These go from level shifter to TFT conn to PWRIO |
| 21 | NET_CLASS | TFT_CLR_FPGA | Tight | | These go from the FPGA to a level shifter || 22 | NET_CLASS | TFT_CLR_LCD | Tight | | These go from level shifter to TFT conn to PWRIO || 23 | NET_CLASS | PCI_FPGA_CONN | Tight | | These go from the FPGA to clamp diodes || 24 | NET_CLASS | PCI_PORT_CONN | Tight | | These go from clamp diodes to the PMC and PCI4451 || | Route Order U50,U51,U52,U53 - J104,J105, U601. Term Res (RP601, RP602, RP604, RP605, RP606 R649, R675, R647, R659) not part of length. |
ML300 CPU
| 2 | NET_CLASS | DDR_CNTL_REG + DDR_CNTL_MEM | < 4500 mils | thru resistors | + ignore tracelength to termination resistor || | Route Order U15 - U9,U8,U7,U6 through (RP308,RP311). Termination Resistor(RP336) not part of overall length. |
| 3 | NET_CLASS | DDR_ADDR_FPGA + DDR_ADDR_RES | < 6000 mils | thru resistors | + ignore tracelength to termination resistor || | Route Order U1 - U14 through (RP359,RP360,RP361,RP362). Termination Resistor(RP330,RP331) not part of overall length. |
| 4 | NET_CLASS | DDR_ADDR_REG + DDR_ADDR_MEM | < 4500 mils | thru resistors | + ignore tracelength to termination resistor || | Route Order U14 - U6,U7,U8,U9 through (RP302,RP303,RP304,RP311). Termination Resistor(RP338,RP339) not part of overall length. |
| 5 | NET_CLASS | DDR_DQS_FPGA + DDR_DQS_RES + DDR_DQS_MEM | < 3300 mils | thru resistors | + ignore tracelength to termination resistor || | Route Order U1 - U6,U7,U8,U9 through (RP326,RP324,R311-R314). Termination resistor (RP340,RP341,R315-R318) not part of overall length. |
| 6 | NET_CLASS | DDR_DATA_FPGA + DDR_DATA_RES + DDR_DATA_MEM | < 3750 mils | thru resistors | + ignore tracelength to termination resistor || | Route Order U1 - U6,U7,U8,U9 through (RP315-RP322 and RP347,RP348,RP350,RP351,RP353,RP354,RP356,RP357). || | Termination resistor (RP349,RP352,RP355,RP358,RP603,RP346,RP344,RP345) not part of overall length. |
| 7 | NET_CLASS | DDR_CLK_FPGA + DDR_CLK_RES | Matched lengths +/- 6 mil | + ignore tracelength to termination resistor || | Route Order U1 - U16 through (R307, R308). Termination resistor (R302,R303,R309) not part of overall length. || | DDR_CLK_*** PT 1: Route Order U1.U21 through resistor R308 to U16.13 (ignore tracelength to term R302) || | DDR_CLK_*** PT 2: Toute Order U1.U21 through resistor R308 back to U1.AC14 (ignore tracelength to R309). || | DDR_CLK_***_N PT 1: Route Order U1.U22 through resistor R307 to U16.14 (ignore tracelength to term R303). || | DDR_CLK_***_N PT 2: Route Order U1.U22 through resistor R307 to C366 (ignore tracelength to R310). |
| 8 | NET_CLASS | DDR_CLK_PLL + DDR_CLK_MEM | Matched lengths +/- 60 mils | thru resistors + ignore tracelength to term res || | Route Order U16 - U6,U7,U8,U9 through (RP328,RP327,RP325). Term resistor (RP340,RP341,RP330,RP331,RP329) not part of overall length |
| 9 | NET_CLASS | CLK_27MHZ_FPGA + CLK_27MHZ_COMP | Matched length +/- 60 mil | thru resistors || | Route Order U1 - U601,J104 through (R1007,R108). | | | || | U1 to U601 through R1007 | | | || | U1 to J104 through R108 | | | |
| 10A | NET_CLASS | ENET_PHY | Matched Length +/- 1000 mil | |
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| | Route Order U1 - U15 through (RP362,RP363). Termination Resistor(RP329,RP331) not part of overall length. ||----------------------------------------------------------------------------------------------------------------------------------------------------|
| 29 | NET_CLASS | AUDIO_DIG_COMP | Tight | | These go from the resistor pack to the AD1885 comp |
| 10B | NET_CLASS | ENET_PHY_COMP | Tight | | Tight |
| 11 | NET_CLASS | PS2_1 | No Issues | | || 12 | NET_CLASS | PS2_2 | No Issues | | || 13 | NET_CLASS | CPU_DEBUG | Matched Length +/- 1250 mil | Tight |
| 15 | NET_CLASS | SYSACE_FLASH | Tight | | Tight |
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| 26 | NET_CLASS | CARDBUSB | Tight | | these go from the PCI4451 to the Cardbus connectors || 27 | NET_CLASS | AUDIO_DIG_FPGA | Tight | | these go from the FPGA to the clamp Diodes || 28 | NET_CLASS | AUDIO_DIG_PMC | Tight | | These go from the clamp diodes to conn and res pack |
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| 30 | NET_CLASS | PMC_FPGA_CONN4 | Tight | | These go from the FPGA to clamp diodes |
| 31 | NET_CLASS | PMC_PMC_CONN4 | Tight | | These go from clamp diodes to PMC4 and PWRIO conn || | Route Order U802,U912,U913,U914 - J106, J102 | | | || 32 | NET_CLASS | IIC_FPGA | no Issues | | These go from the FPGA to clamp diodes || 33 | NET_CLASS | IIC_PMC | no Issues | | These go from clamp diodes to the IIC and conn || 34 | NET_CLASS | DDR_DM_FPGA + DDR_DM_MEM | < 4500 mils | thru resistors | + ignore tracelength to termination resistor || | Route Order U1 - U6,U7,U8,U9 through (RP326,RP324). Termination resistor (RP340,RP341) not part of overall length. |
| 25 | NET_CLASS | CARDBUSA | Tight | | these go from the PCI4451 to the Cardbus connectors ||----------------------------------------------------------------------------------------------------------------------------------------------------|
| | Route Order U1 - P14, P109. | | | |
Net Classes
Net Classes
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5656