custom 14-bit, 125mhz adc/data processing module for the kl experiment at j-parc
DESCRIPTION
Custom 14-Bit, 125MHz ADC/Data Processing Module for the KL Experiment at J-Parc. M. Bogdan, J. Ma, H. Sanders, Y. Wah The University of Chicago. Custom 14-Bit, 125MHz ADC DAQ - Block Diagram. - PowerPoint PPT PresentationTRANSCRIPT
Mircea Bogdan, NSS2007Oct. 27-Nov.3, 2007 – Honolulu, Hawaii 1
Custom 14-Bit, 125MHz ADC/Data Processing Module
for the KL Experiment at J-Parc
M. Bogdan, J. Ma, H. Sanders, Y. Wah
The University of Chicago
Mircea Bogdan, NSS2007Oct. 27-Nov.3, 2007 – Honolulu, Hawaii 2
Custom 14-Bit, 125MHz ADC DAQ - Block Diagram
Custom Boards: - 14-Bit ADC-125MHz, - 12-Bit FADC-500MHz, - Crate Traffic Control Module,- System Trigger Module.
• CsI DAQ up to 2,816 Ch 14Bit/125 MHz;• Veto DAQ up to 512 Ch 14Bit/125 MHz;• BHPV DAQ up to 100 Ch 12Bit/500 MHz.
DAQ designed for an International High Energy Physics Experiment (to study CP Violation) at the new Japanese Accelerator Complex.
Mircea Bogdan, NSS2007Oct. 27-Nov.3, 2007 – Honolulu, Hawaii 3
Custom 14-Bit, 125MHz ADC CsI Crate - Block Diagram
6U VME Crates; 16 ADC Boards/Crate; Local Processing; Continuous Readout; Simultaneous Sampling.
Mircea Bogdan, NSS2007Oct. 27-Nov.3, 2007 – Honolulu, Hawaii 4
Custom 14-Bit, 125MHz ADC Module Block Diagram
•Each ADC channel - one AD9254 chip: 14 bits/125MHz;•10-Pole Filter/Shaper Included on Board;•One STRATIX II FPGA EP2S60F1020 for 16 ADC channels:
•Trigger rate: 10kHz, 32 samples/trigger (256ns);•Input Pipeline: ~25us depth (3,200 samples);•Two VME readout buffers - max 128 triggers, (10 ms).
Mircea Bogdan, NSS2007Oct. 27-Nov.3, 2007 – Honolulu, Hawaii 5
Actual Module Schematic – DA/Mentor Graphics
LVDS Inputs:- 8-Bit Parallel;
LVDS Outputs:- 16-Bit Parallel;- 12-Bit Serialized;
Readout: VME32/64 with CBLT; GLINK/SLINK if needed.
Custom 14-Bit, 125MHz ADC Module Schematic – Top Level
Mircea Bogdan, NSS2007Oct. 27-Nov.3, 2007 – Honolulu, Hawaii 6
Custom 14-Bit, 125MHz ADC Analog Channel
Analog Channel Schematic
Filter/Shaper Simulation
Mircea Bogdan, NSS2007Oct. 27-Nov.3, 2007 – Honolulu, Hawaii 7
16 Channel, 14 bits, 125 MSPS ADC; 10 pole input filter – configurable; Powerful local processing with FPGA; Low cost, 6U VME64 with CBLT.
Built and tested 2 prototypes: Full-Scale Input ~ 250mV/50Ohm; Input noise ~ 35 uV RMS;
Custom 14-Bit, 125MHz ADC Hardware