スケーラブル12bitsar adcの開発...isscc 2008-2013 vlsi symp. 2008-2012 sar adc w/ ovs...

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of Technology



Development of a scalable 12-bit SAR ADC

スケーラブル12bitSAR ADCの開発

H. Kawaraguchi*, S. Lee*, T. Hirato*,

M. Sugawara, M. Miyahara*, and A. Matsuzawa*

*Tokyo Institute of Technology

JST CREST

1





Contents

• Development goal• Frequency, performance, and power

scalable ADC

• SAR ADC design• Circuit design

• Capacitor design

• Measurement results

• Conclusion

2013/11/19

2





Goal: One ADC for versatile use

1. Enough high SNR for wide signal bandwidth

2. Lowest power for wide conversion rate

3. Smallest occupied area

50

60

70

80

90

0.1 1 10 100

135dB

143dB

150dB

BW (MHz)

SN

R (

dB

)

Scalable ADC

BWSNRSNR log100

)log(10140)( BWdBSNR

sd fP

1

10

100

0.1 1 10 100

BW [MHz]

SDCT SDSC VCO

ISSCC 2008-2013

VLSI Symp. 2008 -2012

Po

wer

dis

sip

ati

on

(m

W)

BWKPd 1 K1: 0.2 -- 3 (mW/MHz)

Matsuzawa, A. “Digitally-Assisted Analog and RF CMOS Circuit

Design for Software-Defined Radio,” Chapter 7,Springer 2011. 2013/11/19

SDCT SDSC VCO

3





Contents


scalable ADC




• Conclusion

2013/11/19

4





Block diagram of SAR ADC

Vin

Bootstrap SW

VRNVRP

Floating Cap.

CsCa

128CuCu CH

Dynamic Comp.

Out

Sample

Self-clock Logic

w/ Calibration

Cu 8Cu

Sprit Cap.

Sprit capacitor to reduce the total capacitance

Capacitance is determined by thermal noise

Calibration for mismatch Cap. and parasitic Cap.

Dynamic comparator to reduce power

Self clocking to avoid PLL and DLL

2013/11/19

5





Output

VDDCLK

Vin+

For CAL

Vin-

M1 M2

CL CL

ID ID

Dynamic amplifier Latch

Dynamic comparator

N1a N1b

N2a N2b

N3a

N3b

Fi le : C:\Us e rs \m a ts u \Do c u m e n ts \Top Sp ic e \Ci rc u i ts \DYNAM IC_ COM P_ 12 0 90 1 .OUT Rev : 16 5

Top Sp ic e 8 .10

0 1 -SEP-20 1 2

1 5 :0 1 :5 0 V(151)

Plo t 1 :

V(1 5 1 )

V(153)

V(1 5 3 )

V(152)

V(1 5 2 )

V(150)

V(1 5 0 )

V(155)

V(1 5 5 )

V(154)

V(1 5 4 )

-0.5

0

0.5

1.0

1.5

2.0

V

(V)

ID(M165)

Plo t 2 :

ID(M 1 6 5 )

ID(M127)

ID(M 1 2 7 )

ID(M130)

ID(M 1 3 0 )

ID(M164)

ID(M 1 6 4 )

ID(M129)

ID(M 1 2 9 )ID(M163)

ID(M 1 6 3 )

-750u

-500u

-250u

0

250u

500u

750u

I (

A)

0 200p 400p 600p 800p

TIME (s )

N2

N1

N3a

N3b

VDD

GND

Low noise dynamic comparator to reduce power

No static current flows because of dynamic action

Load capacitance of the 1st stage determines the noise

M. Miyahara, Y. Asada, D. Paik, and A.

Matsuzawa, "A Low-Noise Self-

Calibrating Dynamic Comparator for

High-Speed ADCs," A-SSCC, Nov. 2008.

Yusuke Asada, Kei Yoshihara, Tatsuya Urano,

Masaya Miyahara, and Akira Matsuzawa, "A 6bit,

7mW, 250fJ, 700MS/s Subranging ADC," A-SSCC,

5-3, pp. 141-144, Taiwan, Taipei, Nov. 2009.

2013/11/19

6





Required capacitance and consumed Energy

6 7 8 9 10 11 12 13 140.1

1

10

100

1 103

1 104

1 105

f x( )

g x( )

x

CL(f

F),

Ec(f

J)

Resolution (bit)

CL

Ec

VDD=1V, Veff=0.2V

Proposed dynamic comparator can reduce the noise

due to CMOS input of flip flop circuit, originally.

Node capacitance CL should be increased for higher ADC resolution.

DDL

eff

inVC

TVV

k22_

CL=0.5pF is used

A. Matsuzawa, ASICON 2009, pp. 218-221, Oct. 2009.2013/11/19

1000

10000

100000

7





Self clocking circuit

CAP

DAC

Sampling

CLK

Async.

SAR

Control

Logic

Controllable Dl

Neg. Edge

Pulse

B9

B0

Comparator output

Fi le : C:\Us e rs \m a ts u \Do c u m e n ts \Top Sp ic e \Ci rc u i ts \DYNAM IC_ COM P_ 12 0 90 1 .OUT Rev : 16 5

Top Sp ic e 8 .10

0 1 -SEP-20 12

1 5 :0 1 :5 0 V(151)

Plo t 1 :

V(15 1 )

V(153)

V(15 3 )

V(152)

V(15 2 )

V(150)

V(15 0 )

V(155)

V(15 5 )

V(154)

V(15 4 )

-0.5

0

0.5

1.0

1.5

2.0

V

(V)

ID(M165)

Plo t 2 :

ID(M 1 65 )

ID(M127)

ID(M 1 27 )

ID(M130)

ID(M 1 30 )

ID(M164)

ID(M 1 64 )

ID(M129)

ID(M 1 29 )ID(M163)

ID(M 1 63 )

-750u

-500u

-250u

0

250u

500u

750u

I (

A)

0 200p 400p 600p 800p

TIME (s )

Voa

Vob

Voa

VobComparingEnd of Comp.

Self clocking circuit

Nature of dynamic comparator

can detect the end of comparison.

The self clocking can avoid PLL and DLL.

Comparing period: Same Low states

End of comparison: Different logic states

2013/11/19

8





Timing

Sampling

Power off

Conversion period

Conversion

End flag

Power on

2ns

12ns: 1.2V18ns: 1.0V

Only sampling pulse is required.

Conversion is finished within 12 ~ 18ns

Rest period can be used for power Shut off.

2013/11/19

9





0.5

0.6

0.7

0.8

0.9

1

2

3

50 60 70 80 90 100 200

MOM cap.

MIM cap.

Design rule (nm)

De

ns

ity (

fF/u

m2)

MOM capacitance

MOM

capacitor

MOM capacitance is used to increase capacitor density

and to reduce capacitor area.

2013/11/19

10





Issue of MOM capacitor

177

177.5

178

178.5

179

179.5

180

0 200 400 600 800 1000

Distance (mm

Cap

acitan

ce (fF

)

MOM_A32

2fF (1.1%)

2.75%/mm

MOM capacitance has a large position dependence.

Calibration circuit is needed.

2013/11/19

11





Linearity calibration

2C1C8C4C2C1C

Vref

26C4C2C1C1

2

1

4CC

1

8C 4C2C1C

1

2

1

4CC

-4

-2

0

2

4

0 1024 2048 3072 4096

INL

[L

SB

]

OUTPUT CODE

-4

-2

0

2

4

INL

[L

SB

]

修正後

修正前

Capacitance mismatch CAL

Before

After

Floating capacitor CAL

-5-4-3-2-1012345

2048 2176 2304 2432 2560

INL

[LS

B]

OUTPUT CODE

補正後

補正前After

Before

Split capacitor

Main CDAC

Comp.

Floating capacitance CALCapacitance mismatch CAL

12bit SAR

12bit

Simulation

Capacitance mismatch and parasitic capacitance calibrations

2013/11/19

12





Layout

Logic Comp CDAC

65nm CMOS 0.03mm2

Short cell for future interleaving architecture

Small occupied area

2013/11/19

13





Contents


scalable ADC




• Conclusion

2013/11/19

14





Measured results: SNDR

50

55

60

65

70

0 5 10 15 20 25 30 35 40

SN

DR

[d

B]

Input frequency [MHz]

1.2V

1.0V

0.8V

55

60

65

70

0 10 20 30 40 50 60 70 80 90

SN

DR

[d

B]

Sampling frequency [MHz]

1.2V 1.0V 0.8V

SNDR of 64dB is obtained for Vdd of 1.0V and 1.2V.

SNDR is degraded at Vdd of 0.8V.

2013/11/19

15





Linearity improvement by Calibration

2

3

4

5

6

7

8

2048 2080 2112 2144 2176

INL

[LSB

]

CODE [LSB]

3LSB

Parasitic capacitance of sprit capacitance causes the linearity error

of 3 LSB without calibration, and it can be reduced to 1.2LSB

with calibration.

-2

-1.5

-1

-0.5

0

2048 2080 2112 2144 2176

INL

[LSB

]

CODE [LSB]

1.2LSB

Without CAL. With CAL.

2013/11/19

16





Power dissipation

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 10 20 30 40 50 60 70 80

Po

we

r d

iss

ipa

tio

n [

mW

]

Sampling frequency [MHz]

1.2V

1.0V

0.8V

Power dissipation is very proportional to sampling frequency.

Low voltage operation is effective to reduce power dissipation.

High conversion frequency of 70MHz is achieved.

Power scalable ADC can be realized.

2013/11/19

17





Performance comparison

[3] W. Liu, P. Huang, Y. Chiu, ISSCC, pp. 380-381, Feb. 2010.

[4] T. Morie, et al., ISSCC, pp.272-273, Feb. 2013.

・ Maximum conversion speed of 70MSps・ Lowest operating voltage of 0.8V・ Lowest power dissipation of 2.2mW at 50MSps・ Lowest FoM (DC) of 28fJ・ Smallest area of 0.03mm2

12bit SAR ADCs

[3] [4]

Resolution　(bit) 12 12

VDD (V) 0.8 1 1.2 1.2 1.2

fsample (MHz) 30 50 70 45 50

Pd (mW) 0.8 2.2 4.6 3 4.2

SNDR (dB) 62 64 65 67 71

FoM (fJ) Nyq/DC 81/28 62/33 100/45 36/31 36/29

Technology (nm) 130 90

Occupied area(mm2) 0.06 0.1

This work

12

65

0.03

2013/11/19

18





SNR and Pd vs. signal bandwidth

50

60

70

80

90

0.1 1 10 100

SN

R [

dB

]

BW [MHz]

SDCT SDSC VCO

135dB

143dB

150dB

ISSCC 2008-2013VLSI Symp. 2008-2012

SAR ADC w/ OVS

Interleaving

Over sampling

1V, 50MSps Operation

SNR of 70dB at 10MHz input and 78dB at 1.5MHz

is attained by digital filter (Over sampling).

Frequency and performance scalable ADC is realized.

Power dissipation is the lowest and conversion rate scalable..

Interleaving will expand the BW in future.

1

10

100

0.1 1 10 100BW [MHz]

SDCT SDSC VCO

ISSCC 2008-2013

VLSI Symp. 2008 -2012

This ADC

Over samplingOptimized

Po

wer

dis

sip

ati

on

(m

W)

2013/11/19

19





Conclusion

• 12bit SAR ADC is designed

– Low noise dynamic comparator

– MOM capacitor

– Mismatch Cap. and parasitic Cap. Calibration

– Self clocking circuit

• The SAR ADC achieves

– Maximum conversion speed of 70MSps

– Lowest Vdd of 0.8V and Pd of 2.2mW at 50MSps

– Smallest area of 0.03mm2

• Frequency, performance and power scalable ADC

– 70dB for BW of 10MHz in, 78dB for BW of 1.5MHz

– Power dissipation is perfectly proportional to sampling frequency

– Expected expand of BW by interleaving

2013/11/19

スケーラブル12bitsar adcの開発...isscc 2008-2013 vlsi symp. 2008-2012 sar adc w/ ovs...

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