Upload File

fall 2006ee 5301 - vlsi design automation i i-1 ee 5301 – vlsi design automation i kia bazargan...

  • Home
  • Documents
  • Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction
36
Fall 2006 EE 5301 - VLSI Design Automat ion I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Post on 20-Dec-2015

226 views

Category:

Documents


0 download

Report

TRANSCRIPT

Page 1: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-1

EE 5301 – VLSI Design Automation IEE 5301 – VLSI Design Automation I

Kia Bazargan

University of Minnesota

Part I: IntroductionPart I: Introduction

Page 2: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-2

Administrative Issues• Class

Time and venue: _MW 4:40pm - 5:55pm, ME212 _ Web page:

o http://www.ece.umn.edu/users/kia/Courses/EE5301o http://webct.umn.edu/ (requires x.500 ID & pwd)o !!!! Check the class web page & discussion group

regularly !!!! Textbook:

Sadiq M. Sait, Habib Youssef, "VLSI Physical Design Automation: Theory and Practice", World Scientific Publishing Company; 1st edition (November 15, 1999)

• Grades 30% homework 10% presentations / papers 10% quizzes 40% two open book midterms: Mon Oct 16, Wed Nov 29 10% Final project. Due Wed Dec 6

Page 3: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-3

Administrative Issues (cont.)

• Personnel Instructor: Kia Bazargan

o Email: [email protected] Phone: (612) 625-4588o Office: EE/CSci 4-159o Office hours: __MW 3:30-4:30pm __

TA: ___________________

o Email: ___________________________

o Phone: _____________________________

o Office: ______________________________

o Office hours: __________________________

Page 4: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-4

Administrative Issues (cont.)

• Policies Homework must be received before class starts (hardcopy) or

before 4:30pm (electronic) on the due date

o Three days of grace period for the whole semester

o After the grace period is used, > 10 minutes late 0% of the grade

Zero tolerance for cheating

Collaboration OK, copying NOT OK

Include ID on all homework, exams, etc.

No extra work for extra credit

Check class web pages regularly, students are responsible for checking discussion threads and announcements regularly

Subscribe to the class mailing list (instructions on the web page)

Page 5: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-5

Online Slides

• Slides are posted on the web Handouts posted as .pdf files Powerpoint slides provided too

o NOTE: some slides are animated (like this one)o Click on the slide to see the animationo Click once more.

o Note: some slides have notes! (like this one)

o Some slides contain text that is not printed in the handouts, but animated. These are left for you to fill out in the handouts. An example is shown below (animated: click to see)

This is a sample text, not printed, but animated

Page 6: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-6

References and Copyright

• Textbooks referred (none required) [Mic94] G. De Micheli

“Synthesis and Optimization of Digital Circuits”McGraw-Hill, 1994.

[CLR90] T. H. Cormen, C. E. Leiserson, R. L. Rivest“Introduction to Algorithms”MIT Press, 1990.

[Sar96] M. Sarrafzadeh, C. K. Wong“An Introduction to VLSI Physical Design”McGraw-Hill, 1996.

[She99] N. Sherwani“Algorithms For VLSI Physical Design Automation”Kluwer Academic Publishers, 3rd edition, 1999.

Page 7: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-7

References and Copyright (cont.)

• Slides used: (Modified by Kia when necessary) [©Sarrafzadeh] © Majid Sarrafzadeh, 2001;

Department of Computer Science, UCLA

[©Sherwani] © Naveed A. Sherwani, 1992 (companion slides to [She99])

[©Keutzer] © Kurt Keutzer, Dept. of EECS, UC-Berekeleyhttp://www-cad.eecs.berkeley.edu/~niraj/ee244/index.htm

[©Gupta] © Rajesh Gupta UC-Irvinehttp://www.ics.uci.edu/~rgupta/ics280.html

Page 8: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-8

What is This Course All About?

• Prerequisite C / C++ programming experience Kia will try to provide tutorials

• What is covered? Basic algorithms, complexity theory Integrated circuit (IC) Design flow Computer Aided Design (CAD) tool development

for Very Large Scale Integration (VLSI) Lots of programming!

• Next slides: Overview of IC design steps Related courses at U of M Outline of this course

Page 9: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-9

IC Products• Processors

CPU, DSP, Controllers

• Memory chips RAM, ROM, EEPROM

• Analog Mobile communication,

audio/video processing

• Programmable PLA, FPGA

• Embedded systems Used in cars, factories Network cards

• System-on-chip (SoC)Images: amazon.com

Skipecon

Page 10: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-10

IC Product Market Shares

Source: Electronic Business

Page 11: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-11

The Inverted Pyramid

[©Keutzer]

Electronic Systems > $1 Trillion

Semiconductor > $220 B

CAD $3 B

Page 12: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-12

Semiconductor Industry Growth Rates

Source: http://www.icinsight.com/ (McClean Report)

Page 13: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-13

More Demand for EDA

Source: http://www.edat.com/edac

CA

E =

Com

pute

r Aid

ed E

ngin

eerin

g

Page 14: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-14

Growth in System Size

Source: http://www.edat.com/edac

CA

GR

= C

om

pou

nd A

nnu

al G

row

th R

ate

Page 15: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-15

Example: Intel Processor Sizes

Source: http://www.intel.com/

Intel386TM DXProcessor

Intel486TM DXProcessor

Pentium® Processor

Pentium® Pro &Pentium® II Processors

1.5 1.0 0.8 0.6 0.35 0.25Silicon ProcessTechnology

Page 16: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-16

Moore’s Law

1

10

100

1K

10K

100K

1M

10M

1975 1980 1985 1990 1995

Transistors

10x/6 years10x/6 years

8086

6800068020

80386

80486

68040

80804004

Pentium ProPentium

PPC601

PPC603

MIPS R4000

Microprocessors

[©Keutzer]

Page 17: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-17

NRTS: Chip Frequencies

[©Keutzer]

Clock speed GHz

0

1

3

5

7

9

11

1997 1999 2001 2003 2006 2009 2012

On-chip, local clock, high performance

On-chip, global clock, high performance

Page 18: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-18

Increasing Device and Context Complexity

• Exponential increase in device complexity Increasing with Moore's law (or faster)!

• More complex system contexts System contexts in which devices are

deployed (e.g. cellular radio) are increasing in complexity

• Require exponential increases in design productivity

[©Keutzer]

We have exponentially more transistors!We have exponentially more transistors!

Com

ple

xity

Page 19: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-19

Deep Submicron Effects

• Smaller geometries are causing a wide variety of effects that we have largely ignored in the past: Cross coupled capacitances Signal integrity Resistance Inductance

[©Keutzer]

Design of each transistor is getting more difficult!

Design of each transistor is getting more difficult!

DS

M E

ffects

Page 20: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-20

Heterogeneity on Chip

• Greater diversity of on chip elements Processors Software Memory Analog

[©Keutzer]

More transistors doing different things!More transistors doing different things!

Heterogeneity

Page 21: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-21

Stronger Market Pressures

• Decreasing design window

• Less tolerance for design revisions

[©Keutzer]

Time-to-market

Exponentially more complex, greater design risk, greater variety, and a smaller design

window!

Exponentially more complex, greater design risk, greater variety, and a smaller design

window!

Page 22: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-22

A Quadruple Whammy

[©Keutzer]

Time-to-market

Com

ple

xity

DS

M E

ffects

Heterogeneity

Page 23: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-23

Productivitygap

Role of EDA: close the productivity gap

How Are We Doing?

[©Keutzer]

Source:SEMATECH

Pro

du

ctiv

ity

Tra

ns.

/ S

taff

. M

on

th

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Tr./S.M

Log

ic t

ran

sist

ors

per

chip

(K

)

10

100

1,000

10,000

100,000

1,000,000

10,000,000

Logic

Tr./Chip

198

1

198

5

198

9

199

3

199

7

200

1

200

5

200

9

58% / Yr. compoundcomplexity growth rate

21% / Yr. compoundproductivity growth rate

Page 24: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-24

Evolution of the EDA Industry

[©Keutzer]

Results(design productivity)

Effort(EDA tool effort)McKinsey S-Curve

Transistor entry – Calma, Computervision, Magic

Schematic entry – Daisy, Mentor, Valid

Synthesis – Cadence, Synopsys

What’s next?

Page 25: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-25

IC Design Steps (cont.)

SpecificationsSpecifications High-levelDescriptionHigh-level

DescriptionFunctionalDescriptionFunctionalDescription

BehavioralVHDL, C

StructuralVHDL

Figs. [©Sherwani]

Page 26: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-26

Packaging Fabri-cation

PhysicalDesign

TechnologyMapping

Synthesis

IC Design Steps (cont.)

SpecificationsSpecifications High-levelDescriptionHigh-level

DescriptionFunctionalDescriptionFunctionalDescription

Placed& RoutedDesign

Placed& RoutedDesign

X=(AB*CD)+ (A+D)+(A(B+C))Y = (A(B+C)+AC+ D+A(BC+D))

Figs. [©Sherwani]

Gate-levelDesign

Gate-levelDesign

LogicDescription

LogicDescription

Page 27: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-27

The Big Picture: IC Design Methods

Full Custom

ASIC – StandardCell Design

Standard CellLibrary Design

RTL-Level Design

DesignMethods

Cost /Development

Time

Quality # Companiesinvolved

Page 28: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-28

Optimization: Levels of Abstraction

• Algorithmic Encoding data, computation

scheduling, balancing delays of components, etc.

• Gate-level Reduce fan-out, capacitance Gate duplication, buffer

insertion

• Layout / Physical-Design Move cells/gates around to

shorten wires on critical paths

Abut rows to share power / ground lines

Eff

ecti

ven

ess

Level of

deta

il

Page 29: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-29

Full Custom Design

Structural/RTL Description

Mem

Ctrl

Comp.Unit

RegFile

...

Layouts [© Prentice Hall]

Component Design

Floorplan [©Sherwani]

Place & Route

A/D

PLA

I/Ocomp

RAM

Page 30: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-30

Full Custom Design Example

A/D

PLA I/O

comp

RAM

Metal1

Via

Metal2

I/O Pad

Glue logic(standard

cell design)

Macrocell

design

[©Sherwani]

Page 31: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-31

ASIC DesignStructural/

RTL Description

Mem

Ctrl

Comp.Unit

RegFile

HDL Programming

P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0';

P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0';

add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o);Mult_i1 <= sum_o(7 downto 0);

add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o);Mult_i1 <= sum_o(7 downto 0);

Floorplan [©Sherwani]C D

A B

Cell library

D C C B

A C C

D C D B

BCCC

Page 32: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-32

ASIC (Standard Cell) Design Example

D C C B

A C C

D C D B

BCCC

CellMetal1Metal2

GNDVDD

C D

A BCell library

Placement [©Sherwani]

Page 33: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-33

Where Is This Course in the Big Picture?

• VLSI related courses:VLSI CAD VLSI Design Others

EE 4301Digital Design

With Programmable Logic

EE 5329VLSI Digital

Signal Processing Systems

EE 5333Analog

Integrated CircuitDesign

EE 5549Digital

Signal ProcessingStructures for VLSI

EE 5323VLSI Design I

EE 5324VLSI Design II

EE 5301VLSI DesignAutomation I

EE 5302VLSI Design

Automation II

Page 34: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-34

Course Outline

• Basic algorithms and complexity theory Circuit representations Classes of problems (P, NP) Classes of algorithms (dynamic programming,

network flow, greedy, linear programming, etc.) Graph algorithms

• High-level synthesis Converting high-level languages to RTL Scheduling operations Allocating functional resources (adders,

multipliers, registers, etc.) Register minimization

Page 35: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-35

Course Outline (cont.)

• Partitioning FM, KL, hMetis algorithms

• Floorplanning Slicing, non-slicing floorplans Simulated annealing floorplanning algorithms

• Placement / Packing Force-directed Simulated annealing Quadratic placement

• Global / detailed routing Maze routing, line-search, Steiner trees, channel

routing,

Page 36: Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

Fall 2006 EE 5301 - VLSI Design Automation I I-36

To Probe Further...

• International Technology Roadmap for Semiconductors (ITRS) http://public.itrs.net/

• SEMATECH http://www.sematech.org/

• Textbook Chapters 1, 2


2004/9/16EE 5301 - VLSI Design Automation I 85 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part III: Partitioning

M.tech VLSI SEM II MID I ImportantQuestions

Fall 2006EE 5301 - VLSI Design Automation I VII-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part VII: High Level Synthesis

EE 5301 – VLSI Design Automation I Part I: IntroductionPart I: …aboutme.samexent.com/classes/fall08/ee5301/Slides/EE5301... · 2009. 4. 7. · Overview of IC design steps Related

Viper 5301 Installation Guide

Part No. 5301-1 Part No. 5301-2 - PBEPRO.com Connector... · Part No. 5301-5 BOTTOM ID 1" ... Included with Part No. 780 Part No. 5301-2 BOTTOM ... 3951, 3960, 3961, 3632, 3953, 3962,

Lei nº 5301

Fall 2006EE 5301 - VLSI Design Automation I VI-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part VI: Routing

Fall 2003EE 5301 - VLSI Design Automation I 37 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part II: Algorithms

ECAD & VLSI LAB (90) IV -I

VLSI-I - Incheonesc.incheon.ac.kr/~chung/VLSI/Lecture_05.pdf · 2018-03-20 · Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University VLSI-I Lecture 5

CPE/EE 427, CPE 527 VLSI Design I Introduction, Design ...•VLSI Design I; A. Milenkovic •1 Aleksandar Milenković CPE/EE 427, CPE 527 VLSI Design I Introduction, Design Metrics

5301 Bad Breath

Es Vlsi Vlsi Es Es Vlsi Vlsi Es Vlsi Esd

ACCT 5301 Summer 2013

5301 13th Ave Buyer Booklet

VLSI - 25.01 · UNIT I VLSI DESIGN METHODOLOGIES 9 Introduction to VLSI Design methodologies - Review of Data structures and algorithms - Review of VLSI Design automation tools -

AE 5301 HW 1 Solution

Fall 2006EE 5301 - VLSI Design Automation I V-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part V: Placement

Fall 2003EE 5301 - VLSI Design Automation I 118 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part IV: Floorplanning

SCYA 5301 ORGANIC REACTION MECHANISM

ECE4740: Digital VLSI Design · Digital VLSI Design Lecture 1: Introduction 1 What is digital VLSI •VLSI = very large scale integration •Idea: Implement thousands (…I mean billions)

VLSI, VLSI System & VLSI system design

5301 Instructions 3-22-11 - skytechpg.comskytechpg.com/skytech/assets/File/5301 Instructions 3-22-11(1).pdf · Skytech 5301 1REV 3/22/11 Page of 8 Model: 5301 INSTALLATION AND OPERATING

JIS D 5301:2006

5301 Base Relnotes

Oral Biology 5301

Fall 2006EE 5301 - VLSI Design Automation I 1 Depth-First Search Algorithm acdeb b · c · d · e · a · b·d·c·a·d·a·e·b·b·a·d· dfs(“a”).... dfs(“a”).... a

VLSI I summary lukasc.pdf

•VLSI Design I; A. Milenkovic •1milenka/cpe527-05F/lectures/l02_dmicf.pdf · 2005-08-29 · •VLSI Design I; A. Milenkovic •3 8/29/2005 VLSI Design I; A. Milenkovic 13 Reliability

5301 Northshore Drive - adeq.state.ar.us

5301 G - premierdevelop.com

01 Lei 5301 Estatuto

Lei 5301 Estatuto Dos Militares

5301 5305.output