fall 2006 1 ee 333 lillevik 333f06-l23 university of portland school of engineering computer...
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Fall 2006
Lillevik 333f06-l23 1University of Portland School of Engineering
EE 333
Computer OrganizationLecture 23
RAIDInput/output design
RS232 serial port exampleDirect memory access
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RAID
• RAID: redundant arrays of inexpensive disks
• History: Patterson, Gibson, Katz (1987); UC Berkeley
• Goal: high speed, high reliability, low cost
• Technique: place data across multiple drives and include redundancy (striping)
• RAID levels: 0 – 6, define the striping
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Data striping
• Bit level: each bit of a byte written on a different disk, along with parity
• Block level: each byte of a file written to a different disk, along with ECC
• LUN: collection of drives appear as one logical storage unit
• Multiple, parallel drives: number often a factor of 8, increase bandwidth
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RAID example: 4 data disks
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Commercial productFeatures: 7TB, hot swappable (17 drives), 400 MB/s, 7200 rpm drives, $2/GB, RAID 0, 1, 3, 5, 0+1
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System view of a computer
One Agent at-a-time owns the bus
···
Signal 0
Signal n
Agent 0 Agent n···
BusSignal 1
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Bus timing
Clk
Breq
Bgnt
Ack
Data Bus Driven
ARB ADR DATA RESP
Address Bus Driven
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I/O design
• Memory-mapped– Shared memory and I/O addresses– Some addresses I/O devices, some memory– All memory instructions may operate on an I/O
device
• Separate I/O address space: called ports– Two address spaces: memory and I/O– Unique I/O instructions: in, out
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General memory design
A
DQ
E
R/W
A
DQ
E
R/W
In 0
E
1
n
AddressData
R/W
Qout(low bits)
(upper bits)
decoder
memory
memory
From Lecture 14
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Memory design guide
• Bus lower addresses to all devices• Use upper addresses and decoder for device
enables• Data bus and other control signals sent to
all devices• No read-write signal for ROM• Bus outputs together because they are tri-
stated
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General I/O design
DQ
E
DQ
E
In0
E
1
n
AddressData
Qout
decoder
I/O: D flip flops
Ctl
Ctl
Ctl (Read, Write)
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I/O design guide
• Use address, control, and decoder for device reads and writes
• Data bus sent to all devices
• Bus outputs together because they are tri-stated
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Example I/O design
• Bus (simplified)– Address: 8-bit – Data: 8-bit, tri-state (uni-directional)– Control: read, write
• I/O addresses (Port addresses)– Device 0 = 0xf8– Device 1 = 0xf9
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Schematic
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Trace
Bus floats to 0xff
Write to Ports
Bus floats to 0xff
Read from Ports
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Find decode logic for 4 ports?
Port addresses = 0xf8, 0xf9, 0xfa, 0xfb
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Trace
Bus floats to 0xff
Write to Ports
Bus floats to 0xff
Read from Ports
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RS-232 serial port
• I/O device: USART (universal synchronous asynchronous receiver transmitter)
• Functionality (similar to shift register)
– Transmitter: parallel in, serial out– Receiver: serial in, parallel out– Status
• Output buffer empty
• Input buffer full
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C8251 block diagram
parallel in
parallel outserial in
serial out
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USART addressing
• Memory-mapped I/O (MIPS approach)
• Receiver– Control register: 0xffff 0000– Data register: 0xffff 0004
• Transmitter– Control register: 0xffff 0008– Data register: 0xffff 000c
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USART assembly code
Definitions for memory-mapped devices
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Receive, transmit subroutines
Subroutines to read and write a byte
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Find flowchart for rcvbyte?
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Wait (busy) loop
• Programming technique– CPU continuously reads control register until
non-zero (ready bit set): wait loop
– CPU reads/writes data to port
• Results in poor system utilization: both memory-mapped or separate I/O addresses
• Known as programmed I/O
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Disadvantages of programmed I/O?
1.
2.
3.
4.
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Direct memory access
• Objective: avoid the disadvantages of programmed I/O (eliminate busy loop)
• Technique– CPU writes to special controller (word count
and memory address)– CPU tells controller to start data transfers– CPU continues with other computing– CPU responds to interrupt from controller: ISR
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Role of DMA controller
• Accept initialization data from CPU
• Access I/O device and drive bus (master)– Input: read I/O device and write data to
memory– Output: read memory data and write to I/O
device
• Interrupt CPU when transfer complete
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Programmed I/O
Programmed I/O ties up CPU
Read I/O
Write memory
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DMA I/O
DMA requires little CPU overhead
Initialize
Multiple
transfers
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DMA time line
ISR ISR
Interrupt Interrupt
CPU and I/O concurrent in time
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Find decode logic for 4 ports?
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Find flowchart for rcvbyte?Push $ra
Get rcv status
Char ready?
Read and echo char
Pop $ra
yes
no
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Disadvantages of programmed I/O?
1. CPU cycles result in little computing
2. Memory continuously accessed, possible contention with another CPU
3. One I/O access at a time
4. Bus heavily requested