Exploring EPC Gen-2 clock generation withself-calibrating oscillator

Lucas Teixeira∗†, Gustavo Fernando Dessbesell∗

mails: teixeira@ieee.org, gdessbesell@smdh.org†Federal University of Santa Maria, Informatics Postgraduate Program, GMicro ∗Santa Maria Design House

Santa Maria, Brazil

Abstract—This works presents a study that aims the devel-opment of a power efficient clock generator to fulfill EPCglobalclass 1 generation 2 RFID standard specification. Firstly, clockfrequency requirements were investigated. Then, the standardcharacteristics were explored in order to define a self-calibrationmethodology. The circuit designed was simulated at electricdevice level in a 0.18 micrometer CMOS technology. Powerconsumption results presented (117 nW/MHz in oscillator) provedthe feasibility of this strategy. The tolerance to process variationand temperature fluctuation were verified by simulation.

KeywordsRFID; clock; oscillator; self-calibrated; lowpower; EPC class 1 generation 2.

I. INTRODUCTION

Passive UHF Radio Frequency Identification (RFID) tagsare adopted in logistics and supply chain management [1] asa way to speed up items identification and inventory tasks.The EPCglobal Class-1 Generation-2(EPC Gen-2) is one ofthe existing standards that defines a set of features allowingfast inventory of items using a wireless RF link with a carrierwave in the 860 MHz 960 MHz range [2] . This wireless linkis used to transmit power to the passive circuits and exchangedata between reader and the tag. Using the inventory methodsdefined, one is able to, even in dense populated environments(i.e. a truck full of small identified items), read separately eachof the tags in a defined volume inside the reader RF field.

All power necessary to the tag operation is extracted fromthe RF carrier, so the maximum distance that a tag can beread is limited by its own power consumption and its energyharvesting capability. Then, in order to increase tag readingdistance, the designer shall work to reduce power consumption.

In order to fulfill all requirements of the EPC Gen-2standard a digital control unit (Digital Base Band, DBB) isembedded in the tag circuit. It is responsible to handle datareceived in the modulated carrier and, when requested to do so,to answer (backscatter the requested data). DBB has complexcircuits to decode data from and code data to the reader, checkoperation state, store flags, manage anti-collision algorithm,read and write data from and to memory (when included inthe device). The majority of implementations of such DBBuses synchronous circuits, in which the synchronization signal(clock) allows precise decoding and coding of data in thecommunication with the reader. To deal with the codificationtolerances defined in EPC Gen-2 standard, the clock signal hasa minimum frequency that was already explored in the liter-ature [3], [4], [5], [6]. This frequency, however, is minimized

by the designer in order to reduce the digital circuit powerconsumption and even the clock generator power consumption.

The main purpose of this work is to present the conceptionof a clock generator to be used in an EPCglobal Gen-2 tagdevice. The study of the standard allowed the development ofan oscillator with reduced power consumption and immuneto process variations (without the need of post-manufacturingtrimming) and (in-field) temperature fluctuations. First theclocking requirements are presented in chapter II. Then, theserequirements that define the minimum clock frequency aimedand guided the oscillators review presented in chapter III.Next, the proposed oscillator self calibration process and thedigital implementation are presented in chapter IV. Finally,the implemented oscillator, simulated results and performanceanalysis are presented in chapter V, while the conclusions fromthis design process are discussed in chapter VI.

II. CLOCK REQUIREMENTS

A. Decode requirements

The DBB shall be able to receive and decode Pulse-intervalEncoding (PIE) symbols to fulfill EPC Gen-2 standard. Thesymbols that represent logical data-0 and data-1 are shown inFig. 1. The symbols length is given as a function of ”Tari”value, which is a fixed time length defined by the reader. Itcan range from 6.25 µs to 25 µs. To define the logical valueof each symbol, its length is compared with a pivot value,defined as half of a RTcal symbol, which is sent by the reader(in the transmission preamble, shown in Fig. 1) previously tothe transmission of the data [2]. The number of clock samplestaken during RTcal symbol and data decoding defines the limitbetween a well detected logic symbol and an error due toimprecision. Several studies about this issue allege minimumfrequencies to be used. [6] chooses among 3 frequency values:1.28 MHz, 1.92 MHz and 2.56 MHz, and proved that the first

Fig. 1. PIE data symbols codification and preamble

one is not suitable for decoding, while others claim that thisvalue (1.28 MHz) is suitable [7]. According to [3], for clockfrequencies greater than 1 MHz the distinction between data-0and data-1 can be secured.

B. Encoding requirements

EPC Gen-2 standard defines four possible codificationsthat can be used (selected by the reader) in the tag responseprocess (backscattering). These codifications use a basic wave(Backscatter Link Frequency, BLF) that has its phase changedto represent o high or low logic levels. The frequency of theBLF is in the range from 40kHz to 640kHz, while the expectedvalue for BLFs period is defined by the length of the TRcalsymbol (see Fig. 1 ), and a Divide Ratio(DR) parameter (withvalue 8 or 64/3). Different tolerances are allowed by standarddepending on the frequency range. They are between 4% and22% of BLF.

To comply with EPC Gen-2 standard, while generating theBLF wave, a minimum system frequency is required. For [6]the frequency shall be at least 1.92 MHz, while others (like[7], [3] and [4] claim that it shall be at least 1.28 MHz.

[5], however, affirms that from the final product pointof view a frequency higher than 1.28 MHz should be used.Although a tag can be certified using such clock frequency, theuse of such lower value would lead to a very noise sensitivecircuit. [5] explains that in real application the environmentalnoise would cause the worst-case performance of the tag.

In order to define the minimum frequency that can beused to satisfy TRcal symbol sampling and generate the outputbasic wave to BLF (same frequency is to be used), numericsimulations were made. By calculating the number of samplestaken during TRcal symbol and using both possible DR values,the resulting BLF was calculated considering the frequencydivisions that are possible to be implemented in digital circuits.This process was repeated for frequencies from 1.28 MHz to2.56 MHz and the minimum frequency error was observed.

In this sense, the following restrictions were imposed tothe generated clock and considered in the simulation: theclock shall have a maximum frequency variation of 2% duringbackscatter due to jitter. Also, the division by an odd numberis possible to be implemented since a 50% duty cycle clock isto be used.

From the estimated error results in the generated BLF itwas possible to observe that with the frequencies higher than1.67 MHz the generated BLF does not violate tolerances ofthe standard. These results are consistent with the ones shownby [5], since a frequency jitter was added in simulation, thatincreased the minimum operation frequency to avoid violationsin the standard.

C. Robustness against external factors

The main problem on integrating any circuit is that eachprimitive device will suffer from mismatch with others aroundit and global process variation will influence thresholds,transconductances and other device parameters. As these de-vices cannot be tested before integration, since they are builtdirectly on the wafer, circuit designers aim to reduce thesensitivity of the global circuit to any device parameter in

order to keep expected circuit behavior regardless of theunpredictable device parameters variation. Besides the changeson the behavior of the devices used to build the clock generatorcircuit, voltage or current references used also changes due toprocess variation and device mismatch.

Clock generator usually employs voltage and current refer-ences to define threshold for level change or biasing currents.These references are supposed to have constant and wellknown values during operation, regardless of temperature orpower supply voltage. However, small variations on thesevalues will always occur due to process variation. In orderto overcome any change in references (from expected behav-ior) a trimming procedure can be used after production, butthis increases circuit cost and is not desired. Some authorsalready proposed several self-calibration methodologies thatare suitable to be applied to RFID tags as is presented in [8],[9] e [10],[11]. Most of these calibration results are obtainedusing clock generated by a current controlled oscillator (CCO)circuit. In order to implement a self-calibration strategy severaloscillator implementations reported were studied. The resultsof this research are discussed in next section.

III. OSCILLATORS FOR RFID TAG APPLICATION REVIEW

Several different circuits can be used to obtain a clocksignal to be used in an RFID tag. They can be separated inclock dividers and clock generators. The former type extractsthe clock signal from any available source, while the latterfrom a local oscillator.

Some authors like [12], [13], [1], report the use of injectionlocking clock dividers in order to extract the signal from theRF signal with 860 MHz to 960 MHz. This strategy does notdepend on implementing an oscillator, but it is very powercostly, since several circuits operating in high frequency shallbe used to divide clock from 960 MHz to around 2 MHz.

From the ones that report the use of local oscillators,prevails the implementations that use ring oscillators, as in[3], [4], [9] , [8], [14], [15], [11], [16],[17], [18], [19],[10], [1], [20], [21]. The ring oscillator is a structure thatuses an odd number of NOT logical gates in a loop, so thelogical value in the loop output is never stable. The oscillationperiod is given by the sum of delays of all logic gates inthe loop. These delays can be controlled during operationby changing power supply voltage, capacitances connectedto the gates outputs or by limiting the maximum currentallowed to be drained from power supply. The first strategyis frequently used in order to reduce power consumption andthe oscillator implemented with it is frequently called currentstarve oscillator (one implementation can be seen in Figure 2). It can be built by inserting current sources in series withthe logic gates connections to power rails. Other oscillatorarchitecture referenced by [22], [7], [17], [23], [13], [24] is therelaxation oscillator. The operating principle of this oscillatoris the charge and discharge of a capacitor using two currentsources with known current values or a resistor and a digitalcontrol circuit (commonly a SR-latch).

LC classical oscillator was not used in any of the worksfound. This is probably explained by the prohibitive size of theinductor and capacitor that should be integrated to generate the

Fig. 2. Current starved oscillator circuit

TABLE I. REPORTED RING OSCILLATORS POWER CONSUMPTION

Work Power consumption Work Power consumption[20] 6,250 nW/MHz [11] 625 nW/MHz[19] 5,500 nW/MHz [18] 11 nW/MHz[3] 149 nW/MHz [8] 1,125 nW/MHz[4] 182 nW/MHz [1] 691 nW/MHz[14] 125 nW/MHz [21] 173 nW/MHz[17] 205 nW/MHz

resonance frequency near 2 MHz, suitable to the tag operationin EPC Gen-2 standard.

The choice for a ring oscillator implementation was due totwo main characteristics. Firstly, the power budget reported inmany works was lower when using this oscillator topology thanwhen using others, see Table I. Secondly, as already shown by[3], [4] and [17], a ring oscillator can be designed to have anoscillation frequency very linear to the biasing current (Ib). Thecalibration methodology to be followed was proposed takingadvantage of this linearity and is described in section IV.

IV. PROPOSED OSCILLATOR SELF-CALIBRATION PROCESS

The proposed clock calibration methodology uses the de-limiter symbol shown in Fig. 1) to calibrate the clock frequencyat each incoming transmission from the reader. The oscillatorbias current is controlled using a Digital to Analog Converter(DAC) circuit configured with a default trimming word. Afterreceiving the delimiter symbol the clock is calibrated. Thenthe calibration circuit has its clock signal turned off in orderto reduce its power consumption. Using the oscillator initialfrequency (f(TW0)), which is result from the default knowntrimming word (TW0), the calibration circuit measures howlong is the delimiter symbol in number of clock ticks (ND0),as shown in Equation 1. The relation between clock frequencyand trimming word (TW ) is approximated as linear accordingto Equation 2.

ND0(f0) = 12.5µs.f(TW0) (1)

F (TW ) = c.TW (2)

in which c is a constant given by devices parameters, biascurrent, power supply and device parasitic capacitances. Thevalue of c is expected to be approximately constant during thetime interval between the reception of a given command andthe backscattering of its respective response (if any).

The relation between initial frequency and the expected(f(TWf )) is the c constant, from Equation 2:

c =f(TW0)

TW0=f(TWf )

TWf(3)

TABLE II. DESIGNED CIRCUIT POWER CONSUMPTION

Component During calibration After CalibrationRing oscillator 240 nW 200 nW

Calibration circuit 501 nW 1.9 nW

Isolating f(TW0) from Equation 1 and using it on Equation3 it is possible to determine the final calibration word (TWf ):

TWf = TW0.NDf

ND0(4)

in which NDf is the number of samples that would be takenduring delimiter symbol with expected frequency (constant).Equation 4 is solved using a lookup-table.

This calibration methodology was numerically simulated,using the oscillator linear approximation, considering nominaldelimiter length and extremes of tolerance limits (+/- 5%).The target frequency was set to 1.92 MHz, starting fromfrequencies of 1 MHz to 4 MHz uniformly distributed. Aftercalibrated the oscillator final frequency would range between1.83 MHz (-4.76%) and 2.18 MHz (+13.64%).

The described oscillator and digital calibration controlcircuit were implemented in CMOS technology and simulatedusing real devices models, at SPICE level. The results fromthis implementation are presented in the next section.

V. OSCILLATOR AND CALIBRATION RESULTS

The ring oscillator and the digital calibration circuit wereimplemented using devices from a commercial 0.18 µmCMOS process and 1 V power supply. Monte Carlo analysiswas performed with 50 transient runs, repeated in three tem-peratures: -40◦, +27◦ and +120◦ Celsius. Initial frequency andresulting frequency after calibration were analyzed. The distri-bution of the generated frequencies before and after calibrationprocess is shown in Figure 4. The minimum frequency aftercalibration is 1.81 MHz (higher that the 1.67 MHz necessary tofulfill standard), while the maximum is 2.2 MHz, with standarddeviation of 3.65% of average value.

Total power consumption results are presented in II . Incomparison with the results reported in Table I, the powerperformance measured is 0,117 µW/MHz(after calibration),although a total of 0,741 µW is consumed during calibrationprocess. Further results (such as current-frequency linearity)can still be obtained from this implementation.

VI. CONCLUSION

Comparing the final frequency values (simulated) and thepower consumption (measured) obtained by [4](2.6% over 300

Fig. 3. Layout designed, its dimensions are 55.5 µm X 98µm, leftmostblock is the digital control, top-right block is the DAC and bottom-right blockis the ring oscillator core

0

20

40

60

80

100 O

ccu

ren

ces

Oscillator frequency (MHz)

Before calibration After calibration

Fig. 4. Clock calibration process deviation result

runs and 4.4% over 300 runs), which used a 0.14 µm CMOSprocess, this implementation shows a relative advantage inpower consumption, as ensures generated frequency with lessthan 4% of error over process variation and temperaturefluctuation.

The comparison with other implementations would beunfair, as some adopt power supply rejection techniques (in-creasing unavoidably the power consumption) or aim so highfrequency, as [18] did, that the power saved in the oscillatorwould probably be spent in the DBB.

The use of small components in the ring oscillator, thatcaused more deviation from expected frequency over processvariation, allowed the reduction of bias current. By adjustingthis current according to the obtained frequency during op-eration, the frequency deviation due to process variation andtemperature fluctuation was successful overcomed and the lowpower consumption was kept.

Despite the calibration circuit power consumption, theDBB power consumption will be less when a calibratedclock is used in spite of a fixed higher frequency clock (toavoid violations in the standard). Also, the calibration processensures the minimum clock frequency to be more than 1.67MHz in this implementation.

ACKNOWLEDGMENT

The development of this work would not be possiblewithout the support from the people of Santa Maria DesignHouse, that provided technical support, a creative environmentand active discussions. The knowledge obtained in GMicro, aswell as CAD support, was also very valuable. We would liketo thank the people from these both groups.

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