explore efficient test approaches for pcie at 16gt/s · de-embedding is required to see what the...

Copyright © 2015, PCI-SIG, All Rights Reserved 1

Explore Efficient Test Approaches for PCIe at 16GT/s

Kalev Sepp

Principal Engineer

Tektronix, Inc

PCI-SIG Developers Conference

Disclaimer

Presentation Disclaimer: All opinions, judgments, recommendations, etc. that are presented herein are the opinions of the presenter of the material and do not necessarily reflect the opinions of the PCI-SIG®.


PCI-SIG Developers Conference Copyright © 2015, PCI-SIG, All Rights Reserved 3

Agenda

PCIe® Base vs CEM Tx testing

Testing Challenges in Tx and Rx

Automation to Simplify Tx Testing

Automatic Calibration Essential for Rx Testing

Effective Instruments for PLL Testing

Getting Ready for PCIe 4.0

Conclusions


PCIe Base vs CEM Tx Testing


What test point each type of testing addresses?

How do we get to see the signal at the point of interest?

CaptureMeasure for Base Measure for CEM


Base Spec Testing


Base Specification measurements are defined at the pins of the transmitter

Signal access at the pins is often not possible

De-embedding is required to see what the signal looks like at the pins of the TX, without the added effects of the channel

S-Parameters are acquired for the replica channel

Signal at TX Pins Measured Signal

at TP1

De-embed using

S-Parameters

Signal with Channel

Effects Removed


CEM Testing


CEM Specification measurements are defined at the slicer of a receiver

Signal access at this test point not possible

Embedding of the compliance channel and package, as well as application of the behavioral equalizer is required

SigTest or custom software like SDLA and DPOJET will perform the embedding and calculate measurements

Signal Acquired

from Compliance

Board

Closed Eye due to

the Channel

Apply CTLE + DFE Open Eye for

Measurements

Embed Compliance

Channel and Package


Agenda

PCIe® Base vs CEM testing


Automation to simplify Tx testing


Effective instruments for PLL testing

Getting ready for PCIe 4.0

Conclusions


Testing Challenges in Tx

Meet requirements for effective testing

Compliance mode support, proper patterns

Toggling support (100MHz clock on Rx Ln0)

Correct Tx equalization settings

Preset and Lane ID encoding in Tx pattern

How to handle all lanes, speeds and presets

The answer is test automation, RF switch

Measurement algorithms require channel embed and behavioral equalizer with optimization

Implemented in SigTest, or scope specific software



Automation of Tests


Automation steps

Acquisition of waveforms

Processing of waveforms

Reporting

Toggling of Presets (Tx equalization)

Use AFG or another signal source to generate toggle

4.0 will introduce addition ones

Connecting to all lanes

Use RF Switch

PCI Express testing lends to efficient automation thanks to the methodology based on individual files (test items)


Automated Capture


Use applications built into the scope

Optimize signal capture quality and speed

Organize test data by using naming convention

Supports various test modes


Automated Processing


Typically the processing is built into the standard based application

Processing occurs in series with capture

Processing is serial due to test software limitation (SigTest)

Scope compute platform does not necessarily have the latest processor and is otherwise occupied with scope control, acquisition and visualization

Parallel processing provides improvement

Well designed system provides scalability

Sigtest engines that can be added any time


Practical Comments on Sigtest


Make sure you are using the latest approved version for given technology

Version 3.2.0 requires template patch for Gen2

New installer is being tested

Command line interface is available

Flexible for scripting, for exampleSigtest.exe /e /d folder /s *.wfm /t "PCIE_3_0_CARD\PCIE_3_8GB_CEM.dat"

Binary location different on 32 vs 64 bit system

Two copies can be run but they are not guaranteed to peacefully coexist

Scripting using batch file, powershell or python is available


Agenda

PCIe Base vs CEM Testing






Conclusions


Essentials of Rx Testing

PCIe 3.0 introduced formal Rx testing

Based on stress testing of the DUT in loopback

Looped back signal must contain the same data as the stressed signal

DUT must support loopback initialization and training

Impairments in stress must be controlled and repeatable

DUT must receive stressed signals without errors for certain time or confidence level (below specified BER10-12)



Stress Composition


Tx Eq

8G PRBSGen

RJSource

SJSource

Combiner

DiffInterference

Cal.Channel

ReplicaChannel

Test Equipment

CMInterference

Post-processing

Eye HeightAdjust

PCI Express 3.0 uses a long circuit board channel that closes the eye, and two forms of vertical eye closure (‘Interference’).


Automatic Calibration

Due to complex test setup and variations in DUTs and test equipment just dialing up the settings on the signal source is not sufficient

Stress must be measured and adjusted

Automatic calibration is used to achieve the right amount of stress

Margin testing complements the compliance testing

Help understand your device’s margins

How much additional stress does it tolerate?



Stressed Eye Calibration Setup



Navigate Presets in Rx Testing



Rx Testing Challenges for 16G

Rev 4.0 Spec attempts to streamline testing by reducing differences between Base and CEM

Significant differences at 8GT/s recognized

BERT with required stress generation

RJ, SJ are likely the most challenging specs

De-emphasis

Accurate coverage of the coefficient space

Variable ISI channels

Use ISI emulators or ISI boards planned in PCI-SIG

Custom loopback initialization for test silicon



Rx Testing Summary

High complexity of equipment and procedures

Repeat of extensive correlation studies at 16GT/s in PCI-SIG that helped streamline solutions from multiple vendors

Similar stress signals

Guided calibration and test execution (MOIs)

Good correlation on latest workshops



Agenda







Conclusions


Effective Instrument for PLL Testing

For PLL testing use a setup that requires single instrument

The method is based on modulating the 100MHz reference clock and measuring the bandwidth with clock recovery unit

The limits for bandwidth are 2-4MHz with 2dB peaking

If BW 4-5MHz, peaking must remain under 1dB



PLL Testing with CRU



PLL Testing Setup



Agenda







Conclusions


Review of PCIe 4.0 Characteristics

Some important characteristics Use of the same form-factor, backward compatibility

Due to long channels wider use of extension devices (repeaters)

More states, more complexity in speed and equalization training

New ‘SRIS’ independent Ref Clk modes

– SRNS – Separate RefClk Independent with No SSC Architecture

– SRIS – Separate RefClk Independent with SSC Architecture

Increased number of presets in Tx, 11 presets at 16GT/s, total of 25 presets as of 0.5 spec revision

More complex behavioral receiver (CTLE, DFE with higher number of taps), more time needed for optimization in measurement algorithms




Utilize the investment in PCIe 3.0 as much as possible

Tx signal quality tests

At least 25GHz Oscilloscope, 100GSa/s sampling

16GT/s capable RF switch for automation

Signal source for automation (toggle)

Rx Testing

BERT and related equipment capable of 16GT/s testing

New test boards from PCI-SIG



Conclusions

PCIe 3.0 was a significant step forward in technology and testing methodology

Dealing effectively with closed-eye standard and signals

Virtual test points, multiple presets and lanes

Introducing new types of measurements (uncorrelated jitter)

Formalizing Rx stress test process

PCIe 4.0 is an evolution in test methodology

Methods used in PCIe 3.0 will be extended to higher signaling rate assuming similar losses in the channel

Extension devices (redrivers/retimers) will have impact

Deal with higher number of test items (e.g. waveforms in Tx)

Use efficient tools and you will be ready for PCIe 4.0 testing



Thank you for attending the PCI-SIG Developers Conference

Israel 2015

For more information please go to www.pcisig.com

explore efficient test approaches for pcie at 16gt/s · de-embedding is required to see what the...

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