ex3 de sistemes electrònics digitals - upcdigsys.upc.es/ed/sed/grups_classe/08-09_q1/2at4/... ·...

EX3: Application project 1: Asynchronous serial transmitter in CPLD or FPGA using VHDL

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EX3 de Sistemes Electrònics Digitals

GRUP: DATA: Descripció de les aportacions realitzades i de les conclusions d’aquest exercici TEMPS D’ESTUDI I DE PREPARACIÓ DE L’EXERCICI:

Sessions TGA a l’aula: Sessions TGB al laboratori Sessions TGC fora de l’horari Treball individual Estudiant 1: Estudiant 2: Estudiant 3:

Mitjana de temps total (per estudiant) ÍNDEX DE CONTINGUT

Application project 1: Asynchronous serial transmitter in CPLD or FPGA using VHDL ................. 3

1.1 Description ................................................................................................................................... 3

1.2 Objectives ..................................................................................................................................... 3

1.3 Study time: ................................................................................................................................... 4

1.4 Designing the vending machine.................................................................................................... 4

1.4.1 Electrical schematic or hardware......................................................................................... 4

1.4.2 Coin selector and input synchronisation using a FSM ......................................................... 4

1.4.3 Vending FSM ........................................................................................................................ 5

1.5 On the design of the asynchronous transmitter ............................................................................. 5

1.5.1 Hardware consisting in an OU and a CU ............................................................................ 5

1.5.2 Designing the control unit (CU) ........................................................................................... 7

State diagram for the FSM ................................................................................................................... 7

Synthesis and simulation ...................................................................................................................... 8

1.6 Improvements and new features ................................................................................................... 8

1.7 Desenvolupament de la pràctica/problema. Treball del grup (títol 2) ........................................ 10

1.7.1 El vostre primer subtítol (títol 3) ........................................................................................ 10

Aquest apartat és obligatori. Si no és present, no es corregeix l’exercici i s’ha de tornar a lliurar

Heu d’apuntar tot el temps d’estudi que heu dedicat a l’exercici

EPSC – SED: Sistemes Electrònics Digitals

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1.8 Bibliografia i referències consultades ......................................................................................... 10

1.9 Pla de treball que heu preparat per resoldre el disseny ............................................................... 11

1.10 “Fulls de dubtes” de l’EX2 ......................................................................................................... 12

1.10.1 Sobre els apartats Error! Reference source not found., Error! Reference source not found.

i C) de disseny del codificador del teclat hexadecimal ...................................................................... 12

1.10.2 Sobre l’apartat D) de disseny del multiplexor de displays ................................................. 12

1.10.3 Full de dubtes sobre els apartats F) i H) de la unitat de control........................................ 13

MOLT IMPORTANT: Aquest curs s’espera de vosaltres que ja prepareu i editeu textos de certa qualitat, per tant: preneu aquest document de plantilla d’estils i formats. Amplieu-lo i modifiqueu-lo per plantejar, desenvolupar, solucionar i verificar el funcionament del vostre disseny. NO ES POT LLIURAR CAP TREBALL QUE NO SEGUEIX EXACTAMENT AQUESTA PLANTILLA:

- Fixeu-vos que l’índex de contingut de l’exercici es genera automàticament si respecteu els estils: Normal, Títol 1, Títol 2 i Títol 3.

- Respecteu i useu l’estil del peu de figura (Llegenda) i les referències creuades a les figures que s’actualitzen automàticament quan n’inseriu de noves.

- Respecteu i useu les referències creuades a la bibliografia numerada

- Passeu el corrector ortogràfic i repasseu la gramàtica tant si escriviu en anglès, castellà o català.

- Per eliminar errors, feu una segona lectura a través dels companys de grup abans de lliurar l’exercici

Consulteu-nos també qualsevol dubte que tingueu sobre l’edició de documents i aquesta plantilla en particular. Tingueu en compte les anotacions i indicacions que us han fet els professors en els vostres treballs previs, per tal de no cometre les mateixes errades en aquest treball

ACTIVITATS Qui Què Com Quan Grup de treball cooperatiu Edició impresa (primera

versió) de l’informe de l’exercici. Imprimiu la pàgina 1 i 2 amb l’índex actualitzat 1 i a partir de la pàgina 10

Amb la plantilla i seguint el documents de criteris de qualitat

Abans de la data límit que trobareu al pla de treball o bé al tauló d’anuncis de la web de SED

Els professors o els companys a través d’una correcció creuada

Correcció de la primera versió

Amb la plantilla d’avaluació

Com a màxim una setmana desprès del lliurament de la primera versió impresa

(amb caràcter voluntari)2 Grup de treball cooperatiu Edició electrònica (segona

versió) del document complet amb la incorporació de les millores assenyalades pels correctors

Amb un generador de fitxers PDF

Com a màxim una setmana desprès del lliurament de la correcció. S’enviarà per correu electrònic als professors.

Professors Penjar a la web de SED el document per evidenciar el treball desenvolupat

A través d’un enllaç al document a l’apartat de Grups de Classe

Durant el quadrimestre, si s’escau

NOTA: També es valora la iniciativa. Si el grup cooperatiu vol realitzar una aplicació similar a la presentada en aquest exercici que incorpori els conceptes introduïts, bàsicament el disseny d’un altre sistema digital combinacional amb VHDL, que ho comuniqui als professors i es considerarà.

1 Recordeu que l’índex de continguts el genera automàticament el processador de textos 2 És clar que la realització d’aquesta feina addicional millora la qualificació de l’exercici


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Application project 1: Asynchronous serial transmitter in CPLD or

FPGA using VHDL

1.1 Description

This third exercise, which can be considered a complete project, will integrate the work developed in previous exercises: shift and data registers, multiplexers, counters and frequency dividers, parity generators, etc., with the design of a FSM that will act as the transmitter controller. Thus, the operational unit (OU) or datapath will be combined with the control unit (CU) in order to generate a complete and autonomous subsystem: a computer peripheral for serial communication. ED3. Firstly, an introductory exercise, with the objective to familiarise students with the design of FSM, will be proposed. For example a very simple vending machine will be implemented, synthesised and verified using simulation and the UP2 board. Secondly, A FSM will be added to the existing EX1-EX2 project which, as you remember, consisted in all the operational unit blocks. In this manner, the complete peripheral communication system will work autonomously to transmit data following the standard serial protocol: 1 start bit, 8 data bits, 1 even parity bit, and 1 stop bit. All the VHDL-only projects must be developed and synthesised into FPGA or CPLD chip using the Altera Quartus-II integrated development environment. Again, as in EX2, the proposed design has to be carefully planned (structured) due the large number of blocks involved. Essentially, the project will consist in many VHDL source files to define components to be afterwards instantiated following a hierarchical top-down design approach. The project will be verified using the UP2 Altera board.

1.2 Objectives

After completing the task and studying practically all the Chapter 1 units, students will be able to:

- Explain the basics of the RS232 communication between a computer and a peripheral - Explain the main blocks in which are based the design of an asynchronous serial transmitter - Remember how to design synchronous sequential systems revisiting ED materials - Explain how a FSM can be described as digital system consisting in a (1) state register, (2) the

next state logic, and (3) the outputs’ logic - Search books and the Internet to find information about how a FSM can be coded in VHDL - Describe and conceptualize a digital system as an operational unit (OU) or datapath and a

control unit (CU) - Reinforce the concept of a hierarchical designs using components and their instantiation as the

basis for a good IP (intellectual property) design and documentation - Make projects using Quartus-II software following the design flow which basically consists in:

(1) VHDL source files; (2) functional simulation; (3) pin assignment and synthesis; (4) gate-level simulation; (5) device programming; and (6) prototype verification

- Verify the design (or design components) using the integrated Quartus-II simulator which runs both, functional and gate-level simulation.

- Use RTL, state machine, and technology views as a help to interpret the synthesis process - Use the design summary to get information about the design process and resource usage

(basically registers) - Document the work using a predefined word processor template and utilities: spelling and

grammar, chapter enumeration, page headers and footers, hyperlinks, cross-references, figure captions, text styles, etc.

- Organize the study time and plan the cooperative group work time 3 http://epsc.upc.edu/projectes/ed/grups_classe/07-08-q1/1BT4/07-08-Q1-1BT4.htm


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1.3 Study time:

The estimated student study time for this exercise is 3 weeks4: that means about 20 hours of cooperative work in laboratory sessions (TGA, TGB) or anywhere (TGC).

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1.4 Designing the vending machine

1.4.1 Electrical schematic or hardware

The coffee vending machine (Fig. 1) must accept 0.5 €, 1 € and 2 € coins. The coffee costs 1.5 €, so you can inert coins in any order and the machine will respond by delivering the product and/or the change coins. The change consists in coins of 0.5 € only, thus, if 3 € are introduced as 1 € + 2 € coins, the machine has to generate up to 3 output pulses to give back the 1.5 € of change in 0.5 € coins. 1.4.2 Coin selector and input synchronisation using a FSM

Clicking keys is an asynchronous activity produced at human speed, milliseconds or even seconds or whatever period of time by which you have the key pressed by the physical action of your hand. However, computers work at higher speeds, normally in nanoseconds. So, the problem is how to interface a human action like this one of pressing keys to a computer controlled by a synchronous CLK signal. Furthermore, mechanical keys, pushbuttons or switches can produce contact bounces which are unstable and random for some time and must be removed in order the digital system operate correctly. Let us to design a synchronous 4-key keyboard encoder using the concepts of finite state machines (FSM) to produce clean digital outputs when any key is hit.

A) Find information in books or through the Internet related to the problem of mechanical contact bouncing in pushbuttons, and explain the phenomena.

B) Design the internal circuitry of the coin encoder and synchronizer as a FSM prepared to produce

the following function table: coin type (CT)

coin present (CP)

00 0 none 01 1 0,5 € 10 1 1 € 11 1 2 €

Fig. 1 Vending machine schematic structured into two blocks: a coin encoder and

synchroniser, and the FSM to produce the desired outputs: coffee and coin change

4 Students will work in cooperative groups for the whole semester. They must work an average time of 6.5 hours per week in order to produce significative results and learn enough matter to pass the course.

SS1

COIN_SELECTOR

Coin2

CT0

CT1Coin0_5

Coin1

CP

1

10

CLKCD_L

CLK

100Hz

1 €

0,5 €

2 €

R1100k

VCC

reset

SS2

VENDING FSM

CM

CFCT1

CLKCD_L

CT0

CP

0 Coffee

0Change


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1. Plan and develop a state diagram 2. Write the VHDL code for the FSM the components and the high level

entity (remember to draw an ASM charts for every process before writing any line of code)

3. Functional or behavioural simulation 4. Device selection, pin assignment (constraints) and project synthesis 5. RTL and technology views, state machine view 6. Gate-level (timed) simulation 7. Device programming 8. Verification using a prototype board

1.4.3 Vending FSM

C) Repeat B for the vending FSM component and implement all the application into a single CPLD device

------------------------------------------------------------------------

1.5 On the design of the asynchronous transmitter

1.5.1 Hardware consisting in an OU and a CU

D) Explain why the circuit in Fig. 2 can be used for the transmitter. Explain the basics of the RS232 communication protocol


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Fig. 2 General structure for the asynchronous transmitter


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E) Take all the blocs and components developed in EX2 and place them all into an operational unit entity clearly specifying data inputs and outputs and control lines

1.5.2 Designing the control unit (CU)

State diagram for the FSM

F) Firstly, check the state diagram in Fig. 3 for the Moore FSM and confirm that it can work in order to run the state machine.

1) You may consider naming states with meaningful names, for instance:

a. Idle when nothing happens and the transmitter is waiting for an order and TxD is

marking (high)

b. Enable_Reg to activate LDD signal before the rising edge of the clock

c. Load_Reg to save the byte to be transmitted in the 8-bit parallel register and enabling

the shift register for a parallel load

d. Load_Shift_Reg for loading data to the shift register after a clock edge

e. Start_bit to transmit the first synchronizing bit

f. D0 to transmit the Least Significative Bit of the data byte D[7..0]

g. If you consider having a hardware modulus-8 binary counter, Right_shift can be the

state in which the FSM remains while transmitting the remaining 7 bits of the data

byte till terminal count TC8 is activated. Or alternatively, you can simply expand the

state diagram in Fig. 3 for 7 additional states for transmitting the whole data byte

h. EPB to send the even parity bit

i. Stop_bit for transmitting the last synchronization bit and the End of transmission

pulse

j. End may be an extra state to check if the start transmission pulse is still on

2) Look at Fig. 3 to understand state transitions and consider the important output control signals

at each state for commanding the operational unit.

3) Write down an algorithmic state machine chart (ASM) for state diagram of Fig. 3 and review the

theory of building FSM’s in VHDL (Unit 1.6) to determine your strategy to organize the VHDL

code

4) Code your ASM in VHDL and verify it in Quartus-II environment after the proposal of a stimulus

waveform file for the FSM


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Fig. 3 Example of state diagram showing state transitions and some significative control lines

Synthesis and simulation

G) Connect the FSM to the blocks of the operational unit and verify the transmitter operation

H) Assign pins for the UP2 board and implement the whole transmitter the FSM downloading the configuration file into the FLEX device EPF10K70RC240-4

1.6 Improvements and new features

I) To the basic transmitter, you could add new features to obtain a professional subsystem with intellectual property (IP)5:

1. A configuration bit to program whether parity bit is added or not to the serialised bit stream

2. A configuration bit to select between odd or even parity 3. A programmable clock generator to choose between multiple transmission frequencies

5 Check the IP library from Altera to see if there is available an USART block


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4. A RAM buffer to transmit more than a single byte of data

5. The receiver, if a complete UART peripheral must be implemented

J) Instead of the UP2 (or DE2) training board from Altera, you can migrate to Lattice FPGA boards like “MachXO USB Starter Kit”, or to Xilinx boards like “Spartan-3AN Starter kit, non-volatile FPGA”.

K) Instead of training boards you can design your own prototype PCB using software like EAGLE6

to solder the real-time clock electronic components. Basically, adding characteristics like the ones described above, you can build a system which will have the complexity associated to a final career project.

6 http://epsc.upc.edu/projectes/ed/programari/Programari.html


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1.7 Desenvolupament de la pràctica/problema. Treball del grup (títol 2)

1.7.1 El vostre primer subtítol (títol 3)

La instal·lació del Quartus-II (títol 4)

Afegiu aquí el vostre text (estil normal) encapçalat amb títols (Títol 2 i 3 i 4), amb figures (estil llegenda o “epígrafe”) i referències creuades en el text com aquesta Fig. 4 (és una referència creuada a la llegenda) a les figures que inseriu. Feu referència també en el text a les fonts bibliogràfiques o de web que consulteu d’aquesta manera [1] (és una referència creuada a l’element numerat [1]). Expliqueu perquè les heu consultat i quina informació útil heu trobat.

Fig. 4 Exemple de peu de figura que segueix la numeració de l’enunciat (llegenda)

1.8 Bibliografia i referències consultades

Amplieu i modifiqueu aquesta secció de referències.

[1] http://epsc.upc.edu/projectes/sed/. Pàgina web de SED on trobareu materials i treballs de cursos anteriors. Vegeu la secció unitats didàctiques i grups de classe

[2] Brown,S., Vranesic, Z., “Fundamentals of digital logic with VHDL design”, Mc Graw-Hill, 2005

[3] http://epsc.upc.edu/projectes/ed/problemes/problemes_PA/Problemes_PA.htm. Pàgina web d’ED on hi ha el problema que descriu el funcionament i el disseny del descodificador HEX-7SEG.

[4] http://epsc.upc.edu/projectes/sed/projectes_aplicacio/Projectes_Aplic.htm. Lloc on hi trobareu el full

de plantilla per a distribuir tasques entre els membres del grup cooperatiu


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1.9 Pla de treball que heu preparat per resoldre el disseny

Consulteu els documents de la web [4] per veure com us podeu preparar el pla de treball i el repartiment de tasques per realitzar una bona feina en equip. Useu diagrames de flux, mapes conceptuals, esquemes, taules, etc.



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1.10 “Fulls de dubtes” de l’EX27

1.10.1 Sobre els apartats Error! Reference source not found., Error! Reference source not found. i C)

de disseny del codificador del teclat hexadecimal

Grup de treball: Data: Pla de treball: Dubtes: 1.10.2 Sobre l’apartat D) de disseny del multiplexor de displays

Grup de treball: Data: Pla de treball: Dubtes:

7 Afegiu, si és necessari, altres mitjos fulls com aquests per documentar el vostre progrés a través del projecte i poder realitzar consultes i discussions



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1.10.3 Full de dubtes sobre els apartats F) i H) de la unitat de control

Grup de treball: Data: Pla de treball: Dubtes:

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