ews design guidelines for pcb manufacture may 2012

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Electronics Workshop (EWS) Science 2 Building N34_-1.17 Nathan Campus X57289 Design guidelines for PCB manufacture This Workshop manufactures single-sided and double-sided boards by either chemical etching or mechanical milling. We can accept all Protel and some Altium version files. Ignoring the restrictions below may result in broken or shorted tracks. Ask workshop staff if special requirements exist. Note: Ask about our in house plated-through-hole connections and overlays. We can also arrange PCBs to be produced by external providers. Grid Size – the suggested grid size is 25 mil (1 mil = 0.001”) Minimum clearances 13 mil (0.33 mm) between tracks and pads. Use larger clearances wherever possible to minimise the possibility of short circuits. Mains potentials to any other copper areas must have 6mm (240mil) minimum clearance (AS3100:2002). Consider removing intervening pins from connectors to increase separation. All mains voltage design and manufacture must be compliant with the Queensland Electrical Safety Act 2002, and the Griffith University Electrical Safety Policy 2008. Do not perform this work if you do not hold a current licence for electrical work. Consult E.W.S. staff for information on compliance. Track width – 12 mil (0.3mm) minimum. Use 20 mil (0.5mm) or wider wherever possible, reducing down to 12 mil (0.3mm) minimum, only where necessary (i.e. going between I.C. pins). See Table 3 for information on current carrying capacity verses copper track width. document.doc

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Page 1: EWS Design Guidelines for PCB Manufacture May 2012

Electronics Workshop(EWS)

Science 2 BuildingN34_-1.17Nathan CampusX57289

Design guidelines for PCB manufacture

This Workshop manufactures single-sided and double-sided boards by either chemical etching or mechanical milling. We can accept all Protel and some Altium version files. Ignoring the restrictions below may result in broken or shorted tracks. Ask workshop staff if special requirements exist.

Note: Ask about our in house plated-through-hole connections and overlays. We can also arrange PCBs to be produced by external providers.

Grid Size – the suggested grid size is 25 mil (1 mil = 0.001”)

Minimum clearances –

13 mil (0.33 mm) between tracks and pads.Use larger clearances wherever possible to minimise the possibility of short circuits.

Mains potentials to any other copper areas must have 6mm (240mil) minimum clearance (AS3100:2002). Consider removing intervening pins from connectors to increase separation. All mains voltage design and manufacture must be compliant with the Queensland Electrical Safety Act 2002, and the Griffith University Electrical Safety Policy 2008. Do not perform this work if you do not hold a current licence for electrical work. Consult E.W.S. staff for information on compliance.

Track width – 12 mil (0.3mm) minimum.

Use 20 mil (0.5mm) or wider wherever possible, reducing down to 12 mil (0.3mm) minimum, only where necessary (i.e. going between I.C. pins). See Table 3 for information on current carrying capacity verses copper track width.

Pad size - 62 mil (1.55mm) minimum.

Use 78 mil (2.0 mm) or larger wherever possible.When using connector pins, “D” connectors etc., use 70 mil (1.78 mm) and for voltage regulators, 1-amp diodes etc, use 78 mil (2.0 mm)

Pads should be at least 20 mil (0.5 mm) larger than the required hole size. After the board is routed, check for and modify small pads that can be enlarged without causing clearance errors.

Because the holes are not plated-through, beware of connections on the top layer that are under components and hence can’t be soldered to, e.g. multi-pin transition connectors, IC sockets, trim pots

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Page 2: EWS Design Guidelines for PCB Manufacture May 2012

etc. Use vias, or another components’ pins, to connect top layer tracks to the bottom layer component pads.

Pad Hole Sizes – Edit pads and vias to accommodate stock drill sizes from Table 1. Avoid using hole sizes below 0.7mm as the drills break more easily, and are expensive. Check that the stock library pad hole sizes are what you want drilled. Consider creating a duplicate library with edited components for use while prototyping PCBs.

Power Plane Connect Style Use 20 mil (0.5mm) wherever possible, reducing down to 12 mil (0.3mm) minimum, only if necessary.

Via size - Use 62 mil (1.55mm) where possible, 55 mil (1.4 mm) only if necessary. These have to be connected top layer-to-bottom layer by inserting a piece of wire and soldering both sides, so minimise their use. Where possible, use an existing component lead that can be soldered on both layers to make the connection.

Via Hole Sizes - Make via holes 28 mil (0.7 mm)

Cut lines or a border must be included on Keep Out Layer in your artwork to indicate final board size. Make cut lines 10 mil wide.

Text - To aid in the handling of the artwork in the darkroom when photographically processed, there must be some Correct-reading text on each layer when viewed from that side of the board. This means that any bottom layer text needs to be reversed when viewed from the top. Possible text suggestions are a unique board name, your initials or name, the date, version number etc.

Maximum PC board size is 12” x 18” (300 x 455 mm).

Maximum artwork print sizes are:A4 -> 7.8” x 11.3” (198 x 287mm) A3 -> 11.1” x 16” (282 x 406mm). Larger sizes will involve joining sheets and should be avoided where possible.

Arrays of boards - If multiple copies of the same board are required, they should be arrayed with overlapping 10 mill cut lines. Ensure that the cuts can be made in a logical sequence on our guillotine, and that the dimensions above for maximum pcb size aren’t exceeded.

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Page 3: EWS Design Guidelines for PCB Manufacture May 2012

Table 1: STOCK DRILL EQUIVALENTS

HOLE SIZE (MILS)

DRILL SIZE (mm)

24 0.628 0.731 0.835 0.939 1.043 1.147 1.251 1.355 1.459 1.563 1.671 1.879 2.098 2.5

118 3.0

Table 2: USE THE FOLLOWING LAYERS FOR THE REQUIRED PROCESS

PROCESS CHEMICALLY ETCHED MILLING MACHINETop Text Top Layer Mechanical Layer 1Bottom Text Bottom Layer Mechanical Layer 2Inside Cutting Mechanical 1, 2 or 3 Middle Layer 1Outside Cutting Mechanical 1, 2 or 3 Keepout Layer

Note 1: When boards are to be machine milled, prepare inside and outside cut lines using layers from the above

table. Make cut lines 10 mils wide and lay them continuous and unbroken at corners. Use Imperial grid with “snap-to-grid” resolution not less than 5 mils.

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Page 4: EWS Design Guidelines for PCB Manufacture May 2012

Table 3

Stock copper thicknesses are 35um (1oz) for single-sided and 18um (1/2 oz) for double-sided boards.

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Page 5: EWS Design Guidelines for PCB Manufacture May 2012

FR-4 FIBREGLASS EPOXY-RESIN BONDED LAMINATE

GENERAL SPECIFICATIONGENERAL:

Density, gm. / c.c.-------------------------------------------------------------------------- 1.95Specific Volume, in3/lb---------------------------------------------------- 14.3

Weight per sq.ft. (125” thick),lbs. ------------------------------------------------------- 1.26

MECHANICAL:

Tensile Strength, p.s.i., lengthwise--------------------------------------- 48,000Tensile Strength, p.s.i., crosswise---------------------------------------- 44,000Compressive Strength, p.s.i., flatwise----------------------------------- 60,000Flexural Strength, p.s.i., lengthwise-------------------------------------- 79,000Flexural Strength, p.s.i., crosswise--------------------------------------- 65,000Modulus of Elasticity in Flexure x 105

Lengthwise--------------------- 15

Crosswise----------------------- 12Impact Strength, IZOD Edgewise ft. lb./in. Notch, lengthwise-------------------------- 12.0 ft. lb./in. Notch, crosswise--------------------------- 8.0Rockwell Hardness, M Scale--------------------------------------------- 110Bond Strength, lbs.--------------------------------------------------------- 2,300

ELECTRICAL:

Dielectric Strength-perpendicular to laminations Short time, V/mil. .0625” thick----------------------------- 670 Short time, V/mil. .125” thick------------------------------- 525Dielectric Strength-parallel to laminationsKvolts, step by step, 0.125”, Cond. A----------------------------------- 60 Cond. D48/50------------------ 50Dissipation Factor, 106 Cycles, Cond. A-------------------------------- .015 Cond. D24/23--------------------------- .016

Dielectric Constant , 106 Cycles Cond. A------------------------------ 4.79

NOTE: users have reported that this value is variable, and closer to 4.1 @ 1GHz. Request a sample beforehand if this is critical and you can make your own determination.

Insulation Resistance Megohm, Cond. C96/35/90--------------------- 100,000Arc Resistance, Sec.-------------------------------------------------------- 120

PHYSICAL:

Thermal Conductivity, Cal./Sec./cm2/o C/cm--------------------------- 7.0 x 10-4

Specific Heat Cal/gm/ o C-------------------------------------------------- 0.35 - 0.40Heat Resistance o F, Short Time------------------------------------------ 350 Continuous------------------------------------------- 250Thermal Expansion, in./in./ o F x 10-5

Lengthwise--------------------------------------------- 0.90 Crosswise----------------------------------------------- 0.72Water Absorbtion % 24 hours .0625”------------------------------------------------- 0.10 .125”-------------------------------------------------- 0.07 .500”-------------------------------------------------- 0.03

Stock laminate thickness used is 1.6 mm. Others thicknesses available on special order. Stock copper thicknesses are 35um (1oz) for single-sided and 18um (1/2 oz) for double-sided boards.

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