ethernet mii to aui interface adapter
TRANSCRIPT
8502
4-1
MD400157/D
1
98210
850244L PLCCTop View
Pin Configuration
Features Single Chip Connecting MII and AUI Interfaces
AUI Interface to Ethernet Transceiver
MII Interface to Ethernet Controller
MI Interface for Configuration & Status
Few External Components
Meets All Applicable IEEE 802.3 Standards
Interface to External E 2PROM for AutomaticPreloading of MI Serial Port Bits
Many User Features and Options - Full Duplex - Powerdown - Transmitter Disable/Powerdown - Loopback - MII Disable - Link and Jabber Status Passthrough - Multiple Register Access
LED Outputs - Activity, Transmit, Receive - Collision - Link - User Programmable
44L PLCC
8502Ethernet MII to AUI
Interface Adapter
DescriptionThe 8502 is a interface IC that provides a single chip linkbetween an Ethernet AUI (Attachment Unit Interface) andan Ethernet MII (Media Independent Interface). The 8502is in a 44L package.
The 8502 consists of Manchester encoder, AUI transmit-ter, AUI receiver, Manchester decoder, Media Independ-ent Interface (MII) to an external controller, and Manage-ment Interface (MI) serial port.
The 8502 can access five 16 bit registers though the MIserial port. These registers contain configuration inputs,status outputs, and device capabilities.
The 8502 is ideal for external PHY's that connect AUI orother media to MII. They are also ideal as an AUI interfaceto MII based Ethernet controllers in adapter cards,motherboards, and hubs.
10
9
8
7
11
15
14
13
12
16
17
RXD1
EE_DI
RXD0
EE_DO/RCV_LED
NC
COL
CRS
RX_DV
RX_CLK
EE_CLK/XMT_LED
21201918 22 26252423 27 28
NC
VC
C2
CI–
CI+
DI–
DI+
RB
IAS
NC
DO
–
DO
+
GN
D2
44123 43456 42 41 40T
X_E
N
MD
C
GN
D1
NC
OS
CIN
NC
RX
D2
PLE
D1
VC
C1
RX
D3
PLE
D0
36
37
38
39
35
31
32
33
34
30
29
LINKI
MDIO
NC
EE_CS
Note: Check for latest Data Sheet revisionbefore starting any designs.
SEEQ Data Sheets are now on the Web, atwww.lsilogic.com.
This document is an LSI Logic document. Anyreference to SEEQ Technology should beconsidered LSI Logic.
This datasheet has been downloaded from http://www.digchip.com at this page
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8502 Table of Contents
1.0 Pin Description
2.0 Block Diagram
3.0 Functional Description
3.1 General
3.2 Media Independent Interface (MII)
3.2.1 General
3.2.2 MII Disable
3.3 Manchester Encoder
3.4 Manchester Decoder
3.5 AUI Transmitter
3.5.1 Transmitter
3.5.2 Transmit Activity Indication
3.5.3 Transmit Disable
3.5.4 Transmit Powerdown
3.6 AUI Receiver
3.6.1 Receiver
3.6.2 Squelch
3.6.3 Receive Activity Indication
3.7 Collision
3.7.1 General
3.7.2 Collision Detect Algorithm
3.7.3 Collision Indication
3.7.4 Collision Test
3.8 SOI (Start of Idle)
3.9 Full Duplex Mode
3.10 Loopback
3.11 Link
3.11.1 General
3.11.2 Link Algorithm
3.11.3 Link Indication
3.12 Jabber
3.13 Reset
3.14 Powerdown
3.15 Oscillator
3.16 LED Drivers
3.17 MI Serial Port
3.17.1 Signal Description
3.17.2 Timing
3.17.3 Multiple Register Access
3.17.4 Bit Types
3.17.5 Frame Structure
3.17.6 Register Structure
3.17.7 Link Status Bit
3.17.8 Jabber Detect Bit
3.18 Register Description
3.19 External EEPROM Interface (EEI)
3.19.1 General
3.19.2 Signal Description
3.19.3 Frame Structure
3.19.4 EE_CS Cycle Structure
3.19.5 Timing
4.0 Application Information
4.1 Example Schematics
4.2 AUI Transmit Interface
4.3 AUI Receive Interface
4.4 Controller Interface
4.4.1 General
4.4.2 Output Drivers
4.4.3 MII Disable
4.5 MI Serial Port
4.5.1 General
4.5.2 Multiple Register Access
4.5.3 Serial Port Addressing
4.6 Reset
4.7 External EEPROM
4.8 Oscillator
4.9 Programmable Led Drivers
4.10 Link Passthrough
4.11 Jabber Passthrough
4.12 Power Supply Decoupling
5.0 Specifications
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Pin # Pin Name I/O Description44L
8502
2 VCC2 — Positive Supply. +5 +/-5% Volts.23 VCC1
1 GND2 — Ground. 0 Volts.24 GND1
25 DO+ O AUI Transmit Output, Positive.
26 DO- O AUI Transmit Output, Negative.
19 DI+ I AUI Receive Input, Positive.
20 DI- I AUI Receive Input, Negative.
21 CI+ I AUI Collision Input, Positive.
22 CI- I AUI Collision Input, Negative.
28 RBIAS — Internal Bias Current Set. An external resistor connected betweenthis pin and GND will create a reference current for the internalbias circuits.
43 OSCIN I Clock Oscillator Input. There must be either a 20 MHz crystal or a20 MHz clock tied between this pin and GND. TX_CLK output clockis generated from this input.
30 TX_CLK O Transmit Clock Output. This Media Independent Interface outputprovides a clock to the controller. Transmit data from the controlleron TXD and TX_EN is clocked in on rising edges of TX_CLK andOSCIN.
40 TX_EN I Transmit Enable Input. This Media Independent Interface input hasto be asserted active high to indicate that data on TXD is valid andis clocked in on rising edges of TX_CLK and OSCIN.
34 TXD3 I Transmit Data Input. These Media Independent Interface inputs contain33 TXD2 input nibble data to be transmitted on the AUI outputs and are clocked in32 TXD1 on rising edges of TX_CLK and OSCIN.31 TXD0
13 RX_CLK O Receive Clock Output. This Media Independent Interface outputprovides a clock to the controller. Receive data on RXD and RX_DVis clocked out to the controller on falling edges of RX_CLK.
15 CRS O Carrier Sense Output. This Media Independent Interface output isasserted when valid data is detected on the AUI inputsand is clocked out on falling edges of RX_CLK.
14 RX_DV O Receive Data Valid Output. This Media Independent Interface output isasserted active high when valid decoded data is present on the RXDoutputs and is clocked out on falling edges of RX_CLK.
3 RXD3 O Receive Data Output. These Media Independent Interface outputs6 RXD2 contain receive nibble data from the AUI input and are clocked out on7 RXD1 falling edges of RX_CLK.8 RXD0
1.0 Pin Description
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1.0 Pin Description continued
Pin # Pin Name I/O Description44L8502
16 COL O Collision Output. This Media Independent Interface output is assertedwhen collision between transmit and receive data is detected.
41 MDC I Management Interface Clock Input. This Management Interface clockshifts serial data into and out of MDIO on rising edges.
35 MDIO I/O Management Interface Data Input/Output. This bidirectional pin containsserial Management Interface data that is clocked in and out on risingedges of the MDC clock.
36 LINKI I Link Input. The value on this pin is either passed through to the internalPullup MI serial port Link Status output bit In Register 1 or it enables the internal
To Link algorithm.VCC/2
1 = Link Status Bit Is Set To 0 (Link Fail)float = Link Status Bit Determined By The Internal Link Algorithm0 = Link Status Bit Is Set To 1 (Link Pass)
In 28L 8501, the Link Status Bit is always forced to 1 (Link Pass).
37 JABI I Jabber Input. The value on this pin is passed through to the internal MIPullup serial port Jabber Detect output bit In Register 1.
1 = Jabber Detect Bit Is Set To 0 (No Jabber Detect)0 = Jabber Detect Bit Is Set To 1 (Jabber Detect)
In 28L 8501, the Jabber Detect Bit is always forced to 0 (No Jabber Detect).
9 EE_CS O External EEPROM Chip Select Output. During powerup or reset, thispin is a chip select output to an external EEPROM that can preload theMI serial port input bits to values other than the defaults.
11 EE_CLK/ O External EEPROM Clock Output/Transmit LED. During powerup or reset,XMT_LED this pin is serial data clock output to an external EEPROM that can preload the
MI serial port input bits to values other than the defaults. Data is shiftedin and out on EE_DI and EE_DO, respectively, on rising edges ofthe EE_CLK clock.
During normal operation, this pin can be used as Transmit LED and candrive an LED to GND.
0 = No Detect1 = Transmit Activity Detected, On for 50 mS
10 EE_DI I External EEPROM Data Input. During powerup or reset, this pin is aPullup data input from an external EEPROM that can preload the MI serial port
input bit to values other than the defaults.
12 EE_DO/ O External EEPROM Data Output/Receive LED. During powerup or reset,RCV_LED this pin is a data output to an external EEPROM that can preload the MI
serial port input bit to values other than the defaults.
During normal operation, this pin can be used as Receive LED and candrive an LED to GND.
0 = No Detect1 = Receive Activity Detected, On for 50 mS
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5 PLED1 I/O Programmable LED Output/Management Interface Address Input. This(MDA1) O.D. pin can be programmed through the MI serial port to be either a Collision
Pullup Detect output or a user select output. This pin can drive an LED from VCC.During powerup or reset, this pin is high impedance and the value on this pinis latched in as an address for the MI serial port.
When programmed as Collision Detect Output:1 = No Detect0 = Collision Detected, On For 50 mS
4 PLED0 I/O Programmable LED Output/Management Interface Address Input. This(MDA0) O.D. pin can be programmed through the MI serial port to be either a Activity
Pullup Detect output or a user select output. This pin can drive an LED from VCC.During powerup or reset, this pin is high impedance and the value on this pinis latched in as an address for the MI serial port.
When programmed as Activity Detect Output:1 = No Detect0 = Activity Detected, On For 50 mS
17 NC — No Connect. These pins are not connected but should be tied to GND to18 minimize noise.2729383942
1.0 Pin Description continued
Pin # Pin Name I/O Description44L
8502
8502
4-6
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MA
NC
HE
ST
ER
DE
CO
DE
R(P
LL)
10 M
HZ
CO
LLIS
ION
DE
TE
CT
+ –
TR
AN
SM
ITT
ER
DO
+
DO
-M
AN
CH
ES
TE
RE
NC
OD
ER
SO
ID
ET
EC
T
LPF
ILT
ER
+ –++/–
Vth
CI+
CI–
SQ
UE
LCH
LPF
ILT
ER
+ –++/–
Vth
DI+
DI–
+ –
DA
TA
RE
CE
IVE
R
CO
LLIS
ION
RE
CE
IVE
R
SO
ID
ET
EC
T
SO
IG
EN
ER
AT
OR
8502
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3.2 MEDIA INDEPENDENT INTERFACE (MII)
3.2.1 General
The Media Independent Interface, called MII, provides astandardized interface between the 8502 and an externalEthernet controller. The MII is a nibble wide packet datainterface defined in IEEE 802.3 specifications and shownin Figure 2. The 8502 meets all the MII requirementsoutlined in IEEE 802.3 specifications. The 8502 candirectly connect, without any external logic, to any Eth-ernet controllers which also comply with the IEEE 802.3MII specifications.
The MII consists of fourteen signals: four transmit data bits(TXD[3:0]), transmit clock (TX_CLK), transmit enable(TX_EN), four receive data bits (RXD[3:0]), receive clock(RX_CLK), carrier sense (CRS), receive data valid(RX_DV), and collision (COL). The transmit and receiveclocks operate at 2.5 MHz.
On the transmit side, the TX_CLK output runs continu-ously. When no data is to be transmitted, TX_EN input isdeasserted and any data on TXD[3:0] is ignored. WhenTX_EN is asserted on rising edge of TX_CLK, data onTXD[3:0] is clocked into the device on rising edges of theTX_CLK. TXD[3:0] input data is actually nibble widepacket data whose format needs to be the same asspecified in IEEE 802.3 specifications and shown in Figure2. When all the data on TXD[3:0] has been latched into thedevice, TX_EN is deasserted on rising edge of TX_CLK.
On the receive side, when invalid data is sensed on the AUIinputs, the receiver is idle. During idle, RX_CLK followsTX_CLK, RXD[3:0] is held low, and CRS and RX_DV aredeasserted. When a valid packet is detected on the AUIreceive inputs, CRS is asserted and the clock recoveryprocess starts on the incoming data. After the receiveclock has been recovered from the data, the RX_CLK isswitched over to the recovered clock and the data validsignal RX_DV is asserted on a falling edge of RX_CLK.While RX_DV is asserted, valid data is clocked out of
3.0 Functional Description
3.1 GENERAL
The 8502 is a single chip interface IC's for connecting MIIto AUI. MII and AUI are acronyms for Media IndependentInterface and Attachment Unit Interface, respectively.Both of these interfaces are defined by IEEE 802.3 speci-fications.
The 8502 has six main sections: Media IndependentInterface (MII), Manchester encoder, Manchester de-coder, AUI transmitter, AUI receiver, and MI serial port.
On the transmit side, NRZ data is received on the MII froman external Ethernet controller per the MII format de-scribed in Figure 2. The NRZ data is then sent to theManchester encoder for formatting. The Manchesterencoded data is then sent to the AUI transmitter. The AUItransmitter shapes the output and drives a 78 ohm AUIcable. In addition, the transmitter generates start of idle(SOI) pulses.
On the receive side, the AUI receiver receives incomingManchester encoded data from the AUI cable, removeshigh frequency noise from the input, determines if the inputsignal is a valid packet, and then converts the data fromAUI levels to internal digital levels. The AUI receiver alsodetects start of idle (SOI) pulses and implements a squelchalgorithm to reject invalid signals. The output of the AUIreceiver then goes to the Manchester decoder whichrecovers a clock from the AUI data stream, recovers thedata, and converts the data back to NRZ. The NRZ datais then transmitted to an external Ethernet controllerthrough the MII using the format shown in Figure 2.
The MI (Management Interface) serial port is a two pinbidirectional port through which configuration inputs canbe set, and device capabilities and status outputs can beread out.
A crystal oscillator generates a master clock for the device.
Each block plus the operating modes are described inmore detail in the following sections. A block diagram ofthe 8502 is shown in Figure 1.
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IDLE PREAMBLE
PRMBLE SFD DATA 1 DATA N-1 DATA N
STARTOF
FRAMEDELIM.
62 BT
DATA 2
DATA NIBBLES
FIRSTBIT
2 T
TX_EN = 0TX_EN = 1
PRMBLE = [1 0 1 0 ...], 62T LONG
FIRSTNIBBLE
FIRST BIT MAC’s SERIAL BIT STREAM
D0 D1 D2 D3 D4 D5 D6 D7
TXD0 / RXD0
TXD3 / RXD3
TXD2 / RXD2
TXD1 / RXD1
MSB
SECONDNIBBLE
MIINIBBLESTREAM
LSB
[1 1]SFD =
a.) MII Frame Format
b.) MII Nibble Order
Signals Bit Value
TXDO X X 11 1 1 1 1 1 1 1 1 1 1 1 1 1 12 1TXD1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TXD2 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1TXD3 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1TX_EN 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D03 D44
D1 D5D2 D6D3 D71 1
1. 1st preamble nibble transmitted.2. 1st sfd nibble transmittted.3. 1st data nibble transmitted.4. D0 thru D7 are the first 8 bits of the data field.
Signals Bit Value
RXDO X X X X X X X X X X X X 11 1 1 1 12 1RXD1 X X X X X X X X X X X X 0 0 0 0 0 0RXD2 X X X X X X X X X X X X 1 1 1 1 1 1RXD3 X X X X X X X X X X X X 0 0 0 0 0 1RX_DV 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
D03 D44
D1 D5D2 D6D3 D71 1
1. 1st preamble nibble received. Device guaranteed to provide a minimum of 6 preamble nibbles.2. 1st sfd nibble received.3. 1st data nibble received.4. D0 thru D7 are the first 8 bits of the data field.
c.) Transmit Preamble and SFD bits
d.) Receive Preamble and SFD Bits
Figure 2. MII Data Packet Format
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RXD[3:0] on falling edges of the RX_CLK clock. TheRXD[3:0] data has the same packet format as the TXD[3:0]data and is specified in IEEE 802.3 specifications asshown in Figure 2. When the end of packet is detected,CRS and RX_DV are deasserted. CRS and RX_DV alsostay deasserted if the Link Detect bit in the MI serial portbit is set to the Link Fail state.
The collision output, COL, is asserted whenever the colli-sion condition is detected.
3.2.2 MII Disable
The MII inputs and outputs can be disabled by setting theMII disable bit in the MI serial port Control register. Whenthe MII is disabled, the MII inputs are ignored, the MIIoutputs are high impedance, and the AUI transmitter isidle. If the MI address lines, MDA[1:0], are pulled highduring reset or powerup, the 8502 powers up and resetswith the MII disabled. Otherwise, the 8501/8502 powersup and resets with the MII enabled.
3.3 MANCHESTER ENCODER
The Manchester encoder converts the NRZ nibble datafrom the MII into a single Manchester encoded serial datastream and adds a start of idle (SOI) pulse at the end of thepacket as specified in the IEEE 802.3 specifications. TheManchester encoding process combines clock and datasuch that the first half of the data bit contains the comple-ment of the data, and the second half of the data bitcontains the true data, as described in IEEE 802.3 speci-fications. This guarantees that a transition always occursin the middle of the data bit cell. Manchester encoding ofthe data from TXD occurs only when TX_EN is asserted.
3.4 MANCHESTER DECODER
The Manchester decoder converts the serial data streamfrom the AUI receiver into NRZ data for the MII. Thus, theManchester decoder performs clock and data recoveryfrom the Manchester encoded serial data stream. InManchester encoded data, the first half of the data bitcontains the complement of the data, and the second halfof the data bit contains the true data.
Clock recovery is done with a PLL. When valid data is notdetected on the AUI input, an internal 10 MHz clock isapplied to the input of the PLL. When valid data is detectedon the AUI input, the PLL input is switched to the incomingAUI data. The PLL then recovers the clock by locking ontozero crossings of the preamble of the incoming signal fromthe AUI cable. The recovered clock frequency is 10 MHz.The PLL can lock onto the preamble signal in less than 12transitions (bit times) and can reliably perform the data
recovery process with up to ±18 nS of jitter on the AUIinput. While the PLL is in the process of locking onto thepreamble signal, some of the preamble data symbols arelost. The clock recovery process recovers enough pre-amble data symbols to pass at least 6 nibbles to thereceive MII Media Independent Interface as shown inFigure 2.
Data recovery is performed by latching in data from thereceiver with the recovered clock extracted by the PLL.The data is also converted from a single bit stream intonibble data according the format shown in Figure 2.
3.5 AUI TRANSMITTER
3.5.1 Transmitter
The AUI (Attachement Unit Interface) transmitter takesthe Manchester encoded data, shapes it to meet the pulsetemplate outlined in IEEE 802.3 and shown in Figure 3,adjusts the output voltage to meet the IEEE 802.3 requiredlevels for AUI, and drives the 78 Ohm AUI cable.
Figure 3. AUI Transmit Output Voltage Template
V mV1
V mV2
V mV3
mV0
t tttBT or BT/2
16 nsV dm
8 ns
t = 2.5 ns
V < 1315 mV. V > 450 mV
V = 0.89 V
V = 0.82 V
1 3
2
3
1
2
8502
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3.5.2 Transmit Activity Indication
Activity can be programmed to appear on the PLED0 pinby appropriately setting the programmable LED outputselect bits in the MI serial port Configuration register.When the PLED0 pin is programmed to be an activitydetect output, this pin is asserted low for 50 mS every timea transmit or receive packet occurs. The PLED0 output isopen drain with resistor pullup and can drive an LED fromVCC or can drive another digital input.
XMT_LED is transmit activity output during normal opera-tion. This pin is asserted high for 50 mS every time atransmit packet occurs. The XMT_LED output can drivean LED to GND or can drive another digital input.
3.5.3 Transmit Disable
The AUI transmitter can be disabled by setting the transmitdisable bit in the MI serial port Configuration register.When the transmit disable bit is set, the AUI transmitter isforced into the idle state, and no data is transmittedregardless of the state of TX_EN.
3.5.4 Transmit Powerdown
The AUI transmitter can be powered down by setting thetransmit powerdown bit in the MI serial port Configurationregister. When the transmit powerdown bit is set, the AUItransmitter is powered down, the AUI transmit output ishigh impedance, and the rest of the device operatesnormally.
3.6 AUI RECEIVER
3.6.1 Receiver
The AUI (Attachement Unit Interface) receiver convertsAUI levels to internal digital levels. There are two AUIreceivers on the 8502, one for data (DI±) and one forcollision (CI±).
The AUI inputs on the DI± pins are internally biased toabout 3V by internal 10K bias resistors. The AUI inputsfirst pass through a low pass filter designed to eliminatehigh frequency noise on the input. The output of thereceive filter then goes to two different types of compara-tors, threshold and zero crossing. The threshold compara-tor determines whether the signal is valid, and the zerocrossing comparator is used to sense the actual datatransitions once the signal is determined to be valid data.The output of the threshold comparator goes to the
squelch circuit; the output of the zero crossing comparatoris used for clock and data recovery.
The AUI inputs on the CI± pins are internally biased toabout 3V by internal 10K bias resistors. The AUI inputsfirst pass through low pass filter designed to eliminate highfrequency noise on the input. The output of the collisionreceive filter then goes to a collision threshold comparatorwhich converts the CI± inputs to internal digital levels. Theoutput of the collision threshold comparator then goes tothe collision detect circuit.
3.6.2 Squelch
The squelch block determines if the data from the thresh-old comparators (and hence, AUI inputs) contains validdata. The threshold comparator compares the DI± and CI±inputs against a fixed negative threshold, called the AUIsquelch level. If the input voltage to the threshold com-parator does not exceed the fixed negative threshold level,the receiver is in the squelched state. If the input voltageexceeds the negative squelch level for more than 20 nS,the data is considered to be valid and the receiver nowenters into the unsquelch state. In the unsquelch state, theAUI receive threshold level is reduced by approximately30% for noise immunity reasons and is called theunsquelch level. While in the unsquelch state, the receivesquelch circuit looks for SOI (Start Of Idle) pulse to locatethe end of the packet. When the SOI signal is detected, thereceive squelch is turned on again. The AUI receivermeets the AUI receive requirements defined in IEEE 802.3Section 7.
3.6.3 Receive Activity Indication
Activity can be programmed to appear on the PLED0 pinby appropriately setting the programmable LED outputselect bits in the MI serial port Configuration register.When the PLED0 pin is programmed to be an activitydetect output, this pin is asserted low for 50 mS every timea transmit or receive packet occurs. The PLED0 output isopen drain with resistor pullup and can drive an LED fromVCC or can drive another digital input.
RCV_LED is receive activity output during normal opera-tion. This pin is asserted high for 50 mS every time areceive packet occurs. The RCV_LED output can drive anLED to GND or can drive another digital input.
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3.7 COLLISION
3.7.1 General
Collision is detected whenever the collision detect algo-rithm senses a valid 10 MHz signal on the CI± collisioninputs. When collision is detected, the COL output isasserted, CRS is asserted, and RX_DV is deasserted.The collision function is disabled if the device is in the FullDuplex mode or if the Link Status bit in the MI serial portStatus register is set to the Link Fail state.
3.7.2 Collision Detect Algorithm
The collision detect circuit looks for a valid 10 MHz signalby monitoring the period of the waveform from the CI±inputs. If the period of the input waveform on CI± isbetween 77-200 nS, the collision signal is considered to bevalid and collision is asserted. If the period of the inputwaveform on CI± is less than 48 nS or greater than 400 nS,then collision is deasserted. Any high and low pulse widthsless than 10 nS are rejected as noise.
3.7.3 Collision Indication
Collision detect can be programmed to appear on thePLED1 pin by appropriately setting the programmableLED output select bits in the MI serial port Configurationregister. When the PLED1 pin is programmed to be acollision detect output, this pin is asserted low for 50 mSevery time a collision occurs. The PLED1 output is opendrain with resistor pullup and can drive an LED from VCCor can drive another digital input.
3.7.4 Collision Test
The MII collision signal, COL, can be tested by setting thecollision test bit in the MI serial port Control register. Whenthis bit is set, TX_EN is looped back onto COL and the AUItrasmitter is forced to the idle state.
3.8 SOI (START OF IDLE)
The SOI pulse is a positive pulse inserted at the end ofevery transmitted packet to indicate the end of datatransmission and the start of idle.
The AUI transmitter generates an SOI pulse at the end ofdata transmission when TX_EN is deasserted. Thetransmitted SOI output pulse meets the pulse templaterequirements specified in IEEE 802.3 Section 7 andshown in Figure 4.
The AUI receiver detects the SOI pulse by sensing missingdata transitions. Once the SOI pulse is detected, datareception is ended and CRS is deasserted.
3.9 FULL DUPLEX MODE
Full Duplex mode allows transmission and reception tooccur simultaneously without a collision being signalled.When Full Duplex mode is enabled, collision is disabled,COL is deasserted regardless of the input on CI±, and anyloopback of TX_EN to CRS is disabled, if enabled.
The device can be forced into the Full Duplex Mode bysetting the duplex bit in the MI serial port Control register.
3.10 LOOPBACK
Two different loopback modes are available on the 8502:(1) TX_EN to CRS Loopback, and (2) diagnostic loopback.
TX_EN to CRS Loopback is enabled by setting the TX_ENto CRS Loopback bit in the MI serial port Configurationregister. When this loopback mode is enabled, TX_EN islooped back onto CRS during every transmit packet. ThisTX_EN to CRS Loopback is disabled during collision,when the device is placed in the Full Duplex mode, whenthe Link Status bit in the MI serial port Status register is inthe Link Fail state, when the transmit disable bit is set in theMI serial port Configuration register, and any other condi-tions where the transmitter is disabled.
A diagnostic loopback mode can also be selected bysetting the loopback bit in the MI serial port Controlregister. When diagnostic loopback is enabled, TXD[3:0]data is looped back onto RXD[3:0], TX_EN is looped backonto CRS, RX_DV operates normally, and the AUI receiveand transmit paths are disabled.
Figure 4. AUI Transmit SOI Output Voltage Template
0
+Vdm
–Vdm T2
U
T1
RE
T = 200 ns Minimum
T = 8000 ns
U = –100 mV Maximum Undershoot
E = +/– 40 mV Max
R = <200 mV PK – PK
1
2
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3.11 LINK
3.11.1 General
The status of the link is reported with the link status bit inthe MI serial port Status register. The Link Status bit (LINKbit) can either be controlled by an internal link algorithm orexternally with the LINKI pin. The selection of the methodto set the LINK bit is determined by the LINKI pin. TheLINKI input pin is a three level pin. If LINKI=1 or 0, the 1or 0 value is inverted and automatically passed through tothe LINK bit in the MI serial port Status register. If the LINKIpin is left floating, the pin floats to VCC/2 and this levelindicates to the device that the internal link algorithmshould be used for setting the LINK bit.
3.11.2 Link Algorithm
The internal link algorithm is enabled by letting the LINKIpin float. The internal link algorithm starts by setting theLINK bit to the pass state when the device is powered up.This bit stays in the pass state until a packet is transmitted.When a packet is transmitted, the internal link algorithmexpects a corresponding receive packet to arrive at theAUI inputs within 2 µS. If the expected receive packetarrives within 2 µS after the start of a transmission, theLINK bit stays in the Link Pass state. If the expectedreceive packet doesn't arrive within 2 µS, then the LINK bitgoes to the Link Fail state. Since the LINK bit is an R/LLbit (see section 3.18.4), it latches itself whenever it goeslow (Link Fail) and stays low until read out. Once it is readout, then it returns high to the Link Pass state.
3.11.3 Link Indication
Link Detect can be programmed to appear on the PLED1pin by appropriately setting the PLED configuration bit andthe programmable LED output select bits in the MI serialport Configuration register. When the PLED1 pin isprogrammed to be a link detect output, this pin is assertedlow whenever the device is in the Link Pass State. ThePLED1 output is open drain with resistor pullup and candrive an LED from VCC or can drive another digital input.
3.12 JABBER
The Jabber Detect bit in the MI serial port Status registeris used to report the jabber condition. The 8502 does nothave a jabber detect circuit, but the Jabber Detect bit (JABbit) can be controlled externally with the JABI pin. Thus, ifJABI =1 or 0, the 1 or 0 value is inverted and automaticallypassed through to the JAB bit in the MI serial port Statusregister.
3.13 RESET
The 8502 is reset when either VCC is applied to the deviceor when the reset bit is set in the MI serial port Controlregister. When reset bit is set to a 1, an internal power-on reset pulse is generated which resets all internalcircuits, attempts to access an external EEPROM to loadthe MI serial port bits, forces the MI serial port bits to eithertheir default values or to the contents of the externalEEPROM, and latches in the MI physical address valueson PLED[1:0]/MDA[1:0]. After the power-on reset pulsehas finished, the reset bit in the MI serial port Controlregister is cleared to a 0 and the device is ready for normaloperation 500 mS after the reset was initiated.
3.14 POWERDOWN
The 8502 can be powered down by setting the powerdownbit in the MI serial port Control register. In powerdownmode, the AUI outputs are in high impedance state, allfunctions are disabled except the MI serial port, and thepower consumption is reduced to less than 10 mW. Whenthe device goes from powerdown to powerup state, thedevice is ready for normal operation 500 mS afterpowerdown was deaserted (powerdown bit cleared).
3.15 OSCILLATOR
The 8502 requires a 20 MHz reference frequency forinternal signal generation. This 20 MHz reference fre-quency can be generated by either connecting an external20 MHz crystal between OSCIN and GND or an external20 MHz clock on OSCIN.
3.16 LED DRIVERS
The PLED[1:0] outputs are open drain with a resistorpullup. These outputs can drive LED's tied to VCC.
The PLED[1:0] outputs can be individually programmedthrough the MI serial port to do 4 different functions: (1)Normal Function (2) On, (3) Off, and (4) Blink.
PLED[1:0] can be individually programmed by appropri-ately setting the LED output select bits in the MI serial portConfiguration register. When PLED[1:0] are programmedfor their Normal function, these outputs indicate the spe-cific functions described in the MI serial port Configurationregister shown on Table 9 (Collision, Activity, respec-tively). When PLED[1:0] are programmed to be On, theLED output drivers goes low, thus turning on the LEDunder user control. When PLED[1:0] are programmed tobe Off, the LED output drivers will turn off, thus turning off
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the LED under user control. When PLED[1:0] are pro-grammed to Blink, the LED output drivers will continuouslyblink at a rate of 50 mS on, 50 mS off.
The default Normal functions for PLED1 and PLED0 areCollision Detect and Activity, respectively. The Normalfunction for PLED1 can be changed from Collision Detectto Link Detect by setting the PLED1 Configuration Selectbit in the MI serial port Configuration register. When thisbit is set, the Normal function for PLED1 changes fromCollision to Link. That is, for PLED1 to be a Link Detectoutput, the PLED1 Configuration Select and PLED1 Out-put Select bits must all be high.
XMT_LED and RCV_LED outputs can drive LEDs to GNDindicating transmit and receive activity respectively. Theyare asserted high for 50 mS every time a transmit or areceive packet occurs.
3.17 MI SERIAL PORT
3.17.1 Signal Description
The MI serial port has four pins, MDC, MDIO, andMDA[1:0]. MDC is the serial shift clock input. MDIO is abidirectional data I/O pin. MDA[1:0] are address pins forthe MI serial port.
MDA[1:0] inputs share the same pins as the PLED[1:0]outputs, respectively. At powerup or reset, the PLED[1:0]output drivers are high impedance for an interval towardsthe end of the poweron reset time. During this interval, thevalues on these pins are latched into the device, inverted,and used as the MI serial port addresses.
3.17.2 Timing
The MI serial port is idle when at least 32 continuous 1's aredetected on MDIO, and it remains idle as long as continu-ous 1's are detected. During idle, MDIO is in the highimpedance state. When the MI serial port is in the idlestate, a 01 pattern on the MDIO pin initiates a serial shiftcycle. Data on MDIO is then shifted in on the next 14 risingedges of MDC (MDIO is high impedance). If the multipleregister access mode is not enabled, on the next 16 risingedges of MDC, data is either shifted in or out on MDIO,
depending on whether a write or read cycle was selectedwith the bits READ and WRITE. After the 32 MDC cycleshave been completed, one complete register has beenread/written, the serial shift process is halted, data islatched into the device, and MDIO goes into high imped-ance state. Another serial shift cycle cannot be initiateduntil the the idle condition (at least 32 continuous 1's) isdetected.
3.17.3 Multiple Register Access
Multiple registers can be accessed on a single MI serialport access cycle with the multiple register access feature.The multiple register access feature can be enabled bysetting the multiple register access enable bit in the MIserial port Configuration register. When the multipleregister access feature is enabled, multiple registers canbe accessed on a single MI serial port access cycle bysetting the register address to 11111 during the first 16MDC clock cycles. There is no actual register residing inregister address location 11111, so when the registeraddress is then set to 11111, all five registers are accessedon the 80 rising edges of MDC that occur after the first 16MDC clock cycles of the MI serial port access cycle. Theregisters are accessed in numerical order from 0 to 16.After all 96 MDC clocks have been completed, all theregisters have been read/written, the serial shift process ishalted, data is latched into the device, and MDIO goes intohigh impedance state. Another serial shift cycle cannot beinitiated until the the idle condition (at least 32 continuous1's) is detected.
3.17.4 Bit Types
Since the serial port is bidirectional, there are many typesof bits. Write bits (W) are inputs during a write cycle and arehigh impedance during a read cycle. Read bits (R) areoutputs during a read cycle and high impedance during awrite cycle. Read/Write bits (R/W) are actually write bitswhich can be read out during a read cycle. R/WSC bits areR/W bits that clear themselves after a set period of time orafter a specific event has completed. R/LL bits are readbits that latch themselves when they go low, and they staylatched low until read. After they are read, they are reset
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3.17.5 Frame Structure
The structure of the serial port frame is shown in Table 2and a timing diagram of a frame is shown in Figure 5. Eachserial port access cycle consists of 32 bits (or 96 bits ifmultiple register access is enabled and REGAD=11111),exclusive of idle. The first 16 bits of the serial port cycle arealways write bits and are used for addressing. The last16(80) bits are to or from one(all) of the five data registers.
The first 2 bits in Table 2 and Figure 5 are start bits andneed to be written as a 01 for the serial port cycle tocontinue. The next 2 bits are a read and write bit whichdetermine if the accessed data register bits will be readfrom or written to. The next 3 bits are upper deviceaddresses and they must be written as 111 for the serial
port access to continue. The next 2 bits are lower deviceaddress and must match the inverted values latched infrom pins MDA[1:0] during the poweron reset time for theserial port access to continue. The next 5 bits are registeraddress select bits which select one or all of the five dataregisters for access. The next 2 bits are turnaround bitswhich are not actual register bits but extra time to switchMDIO from write to read if necessary, as shown in Figure5. The final 16 bits of the MI serial port cycle (or 80 bits ifmultiple register access is enabled and REGAD=11111)are to or from the data register designated in the registeraddress bits REGAD[4:0].
3.17.6 Register Structure
The 8502 has five internal 16 bit registers. All five registersare available for setting configuration inputs and readingstatus outputs. A map of the registers is shown in Table 3.The five registers consist of four registers that are definedby the IEEE 802.3 specification (Registers 0-3) and oneregister that is unique to the 8502 (Register 16).
The structure and bit definition of the Control register isshown in Table 4. This register stores various configura-tion inputs and its bit definition complies with the IEEE802.3 specifications.
The structure and bit definition of the Status register isshown in Table 5. This register contains device capabili-ties and status output information. and its bit definitioncomplies with the IEEE 802.3 specifications.
The structure and bit definition of the PHY ID #1 and #2registers is shown in Tables 6 and 7, respectively. Theseregisters contain an identification code unique to the 8502and their bit definition complies with the IEEE 802.3specifications.
The structure and bit definition of the Configuration regis-ter is shown in Table 8. This register stores variousconfiguration inputs.
3.17.7 Link Status Bit
The Link Status bit in the Status register is controlled byeither the internal link algorithm or by direct pass throughfrom the LINKI pin. Refer to the Link section for furtherdetails.
3.17.8 Jabber Detect Bit
The Jabber Detect bit in the Status register is controlled bydirect pass through from the JABI pin. Refer to the Jabbersection for further details.
Table 1. MI Register Bit Type Definition
Sym. Name Definition
Write Cycle Read Cycle
W Write Input No Operation,Hi ZR Read No Operation, Output
Hi ZR/W Read/ Input Ouput
WriteR/WS Read/ Input OutputC Write Self
Clearing Clears Itself AfterOperationCompleted
R/LL Read/ No Operation, OutputLatching Hi ZLow When Bit GoesLow,
Bit Latched.When Bit Is Read,Bit Updated.
R/LH Read/ No Operation, OutputLatching Hi ZHigh When Bit Goes
High,Bit Latched.When Bit Is Read,Bit Updated.
high. R/LH bits are the same as R/LL bits except that theylatch high. The bit type definitions are summarized inTable 1
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2526
2728
2930
31
D8
D7
D6
D5
D4
D3
D2
D1
D0
DA
TA
[15:
0]
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3.18 Register Description
Table 2. MI Serial Port Frame Structure
<Idle> <Start> <Read> <Write> <PHY Addr.> <Reg. Addr.> <Turnaround> <Data> ....IDLE ST[1:0] READ WRITE PHYAD[4:0] REGAD[4:0] TA[1:0] D[15:0]....
Register 0 ControlRegister 1 StatusRegister 2 PHY ID #1Register 3 PHY ID #2Register 16 Configuration
Symbol Name Definition R/W
IDLE Idle Pattern These Bits Are an Idle Pattern. Device Will Not Initiate An MI WCycle Until It Detects At Least 32 1's.
ST1 Start Bits When ST[1:0]=01, A MI Serial Port Access Cycle Starts. WST0
READ Read Select 1 = Read Cycle W
WRITE Write Select 1 = Write Cycle W
PHYAD[4:0] Physical Device When PHYAD[4:2]=000 and PHY[1:0]=MDA[1:0] Pins Inverted, WAddress The MI Serial Port Is Selected For Operation.
REGAD[4:0] Register Address If REGAD=00000-11111, These Bits Determine The Register From WWhich D[15:0] Is Read/Written. If Multiple Register Access IsEnabled And REGAD=11111, All Registers Are Read/Written.
TA1 Turnaround Time These Bits Provide Some Turnaround Time For MDIO R/WTA0
When READ=1, TA[1:0]=Z0 When WRITE=1, TA[1:0]=ZZ
D[15:0].... Data These 16 Bits Contain Data To/From One Of The Five Registers AnySelected By Register Address Bits REGAD[4:0].
IDLE is shifted in first
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x.6
x.7
8x.
3x.
0x.
5x.
4x.
1x.
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00
W0
00
00
0
ort
Reg
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ST
LX0
00
00
0
CA
P_S
UP
R0
CA
P_N
WY
JAB
AN
EG
_AC
KR
EM
_FLT
EX
RE
GLI
NK
RR
RR
RR
R/L
HR
/LL
00
01
00
01
OU
I12
OU
I11
10O
UI1
5O
UI1
7O
UI1
3O
UI1
4O
UI1
8O
UI1
6
RR
RR
RR
RR
00
00
01
11
PA
RT
2P
AR
T3
T4
RE
V3
RE
V1
PA
RT
1P
AR
T0
RE
V0
RE
V2
RR
RR
RR
RR
00
00
10
00
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Table 4. MI Register 0 (Control) Structure And Bit Definition
0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8
RST LPBK SPEED ANEG_EN PDN MII_DIS ANEG_RST DPLX
R/WSC R/W R/W R/W R/W R/W R/W R/W
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
COLTST 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Symbol Name Definition R/W Def.
0.15 RST Reset 1 = Reset R/W 00 = Normal SC
0.14 LPBK Loopback 1 = Loopback Mode Enabled R/W 0Enable 0 = Normal
0.13 SPEED Speed Select 0 = 10 Mbps Selected, No 100 Mbps Capability R/W 0
0.12 ANEG_EN AutoNegotiation 0 = No Enable, No AutoNegotiation Capability R/W 0Enable
0.11 PDN Powerdown 1 = Powerdown R/W 0Enable 0 = Normal
0.10 MII_DIS MII Interface 1 = MII Interface Disabled, All MII Outputs Hi-z R/W 1[1]
Disable 0 = Normal
0.9 ANEG_RST AutoNegotiation 0 = No Reset, No AutoNegotiation Capability R/W 0Reset
0.8 DPLX Duplex Mode 1 = Full Duplex R/W 0Select 0 = Half Duplex
0.7 COLTST Collision Test 1 = Collision Test Enabled R/W 0Enable 0 = Normal
0.6 Reserved, Must Be 0 R/W 0thru0.0
x.15 Bit Is Shifted First
1. If MDA[1:0] Is Not =11 during reset, then the MII_DIS default value is changed to 0.
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Table 5. MI Register 1 (Status) Structure and Bit Definition
1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8
CAP_T4 CAP_TXF CAP_TXH CAP_TF CAP_TH 0 0 0
R R R R R R R R
1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0
0 CAP_SUPR ANEG_ACK REM_FLT CAP_ANEG LINK JAB EXREG
R R R R R R/LL R/LH R
Bit Symbol Name Definition R/W Def.
1.15 CAP_T4 100BaseT4 0 = Not Capable of 100BaseT4 Operation R 0Capable
1.14 CAP_TXF 100BaseTX Full 0 = Not Capable of 100BaseTX Full Duplex R 0Duplex Capable
1.13 CAP_TXH 100BaseTX Half 0 = Not Capable of 100BaseTX Half Duplex R 0Duplex Capable
1.12 CAP_TF 10BaseT Full 1 = Capable of 10 Mbps Full Duplex R 1Duplex Capable
1.11 CAP_TH 10BaseT Half 1 = Capable of 10 Mbps Half Duplex R 1Duplex Capable
1.10 Reserved R 0thru1.7
1.6 CAP_SUPR MI Preamble 0 = Not Capable of MI Preamble Suppression R 0Suppress Capable
1.5 ANEG_ACK AutoNegotiation 0 = No Acknowledgement, No AutoNegotiation R 0Acknowledgemnt Capability
1.4 REM_FLT Remote Fault 0 = No Remote Fault R 0Detect
1.3 CAP_ANEG AutoNegotation 0 = Not Capable of AutoNegotiation Operation R 0Capable
1.2 LINK Link Status 1 = Link Pass R/LL 11
0 = Link Fail
1.1 JAB Jabber Detect 1 = Jabber Detected R/LH 0 2
0 = Jabber Not Detected
1.0 EXREG Extended Register 1 = Extended Registers Exist R 1Capable
x.15 Bit is Shifted First
1. The Default Value of LINK Bit is Determined by the LINKI Pin. 2. The Default Value of JAB Bit is Determined by the JABI Pin.
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Table 6. MI Register 2 (PHY ID #1) Structure and Bit Definition
2.15 2.14 2.13 2.12 2.11 2.10 2.9 2.8
OUI3 OUI4 OUI5 OUI6 OUI7 OUI8 OUI9 OUI10
R R R R R R R R
2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0
OUI11 OUI12 OUI13 OUI14 OUI15 OUI16 OUI17 OUI18
R R R R R R R R
Bit Symbol Name Definition R/W Def.
2.15 OUI3 Company ID, SEEQ OUI = 00 – A0 – 7D R 02.14 OUI4 Bits 3-18 02.13 OUI5 02.12 OUI6 02.11 OUI7 02.10 OUI8 02.9 OUI9 02.8 OUI10 02.7 OUI11 02.6 OUI12 02.5 OUI13 02.4 OUI14 12.3 OUI15 02.2 OUI16 12.1 OUI17 12.0 OUI18 0
x.15 Bit Is Shifted First
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Table 7. MI Register 3 (PHY ID #2) Structure and Bit Definition
3.15 3.14 3.13 3.12 3.11 3.10 3.9 3.8
OUI19 OUI20 OUI21 OUI22 OUI23 OUI24 PART5 PART4
R R R R R R R R
3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0
PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
R R R R R R R R
Bit Symbol Name Definition R/W Def.
3.15 OUI19 Company ID, SEEQ OUI = 00 – A0 – 7D R 13.14 OUI20 Bits 19-24 13.13 OUI21 13.12 OUI22 13.11 OUI23 13.10 OUI24 0
3.9 PART5 Manufacturer's 0216 R 03.8 PART4 Part Number 03.7 PART3 03.6 PART2 03.5 PART1 13.4 PART0 0
3.3 REV3 Manufacturer's 016 R 03.2 REV2 Revision Number 03.1 REV1 03.0 REV0 0
x.15 Bit is Shifted First
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Table 8. MI Register 16 (Configuration) Structure and Bit Definition
16.15 16.14 16.13 16.12 16.11 16.10 16.9 16.8
XMT_DIS XMT_PDN 0 TXEN_CRS MREG 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
16.7 16.6 16.5 16.4 16.3 16.2 16.1 16.0
PLED1_1 PLED1_0 PLED0_1 PLED0_0 PLED1_CFG 0 0 0R/W or R/W or R/W or R/W or R/W R/W R/W R/WR/WSC R/WSC R/WSC R/WSC
Bit Symbol Name Definition R/W Def.
16.15 XMT_DIS AUI Transmit 1 = AUI Transmitter Disabled, Force To Idle R/W 0Disable 0 = Normal
16.14 XMT_PDN AUI Transmit 1 = AUI Transmitter Powered Down R/W 0Powerdown 0 = Normal
16.13 Reserved For Factory Use, Must Be 0 R/W 0
16.12 TXEN_CRS TXEN To CRS 1 = TX_EN Looped Back To CRS While Non-Idle R/W 0Loopback Enable 0 = No Loopback
16.11 MREG Multiple Register 1 = Multiple Register Access Feature Enabled R/W 0Access Enable 0 = No Multiple Register Access
16.10 Reserved For Factory Use, Must Be 0 R/W 016.9 016.8 0
16.7 PLED1_1 Programmable 11 = Collision (PLED1 Is Low For R/W 116.6 PLED1_0 LED Output 100 mS When Collision or 1
Select, Pin Occurs,Then Pin R/WPLED1 Returns High and Bit SC
Clears Itself)
10 = LED Blink (PLED1 Is Toggling 100 mSLow, 100 mS High)
01 = LED On (PLED1 Is Low)00 = LED Off (PLED1 Is High)
16.5 PLED0_1 Programmable 11 = Activity (PLED0 Is Low For 100 mS R/W 116.4 PLED0_0 LED Output When Activity Occurs,Then or 1
Select, Pin Pin Returns High and Bit R/WPLED0 Clears Itself) SC
10 = LED Blink (PLED0 Is Toggling 100 mSLow, 100 mS High)
01 = LED On (PLED0 Is Low)00 = LED Off (PLED0 Is High)
16.3 PLED1_CFG PLED1 1 = PLED1 Is Link Detect When PLED1_[1:0]=11 R/W 0Configuration 0 = PLED1 Is Collision When PLED1_[1:0]=11Select
16.2 Reserved For Factory Use, Must Be 0 R/W 0
16.1 Reserved For Factory Use, Must Be 0 R/W 0
16.0 Reserved For Factory Use, Must Be 0 R/W 0
x.15 Bit is Shifted First
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EG
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EA
D E
EP
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3.19 EXTERNAL EEPROM INTERFACE (EEI)
3.19.1 General
The default values of the MI serial port registers can bemodified externally through the External EEPROM Inter-face, called EEI. The EEI will automatically fetch datastored in an external EEPROM (or equivalent) and use thisdata to overwrite the default values in the MI registers.This automatic fetch and write function is initiated whenVCC is applied to the device or when the MI serial portreset bit is set. The EEI can overwrite all the bits in the MIregisters including the read bits (with the exception ofRESET, JAB, and LINK).
The EEI is intended to interface to the 9346 family ofEEPROM's.
3.19.2 Signal Description
The EEI consists of four pins, EE_CS, EE_CLK, EE_DI,and EE_DO. EE_CS is a chip select output. EE_CLK is aserial shift clock output. EE_DI and EE_DO are the datain and data out pins, respectively.
3.19.3 Frame Structure
Each EEI frame consists of six individual accesses of theexternal EEPROM memory, called EE_CS cycles. Adiagram of the frame structure is shown in Figure 6.
Each EE_CS cycle (exclusive of the first cycle) accessesone 16 bit register in the external EEPROM and moves thecontents of that EEPROM register into one of the five MIregisters. The correspondance of EE_CS cycle number towhich EEPROM register is read to which MI register iswritten to is shown in Table 9 as well as Figure 6.
The first EE_CS cycle is used by the 8502 to determine ifthere is an EEPROM or equivalent connected to the EEI;it does not load any data into any MI register. Thisidentification of an EEPROM or equivalent on the EEI isdone by examination of a specific EEPROM register for aspecific data pattern. If the contents of the first EEPROMregister accessed (EEPROM register 000001) is A07D16 ,then the remainder of the EEPROM data is fetched andwritten into the MI registers as described. If the content ofEEPROM register 000001 is not A07D16 , the EEI frame isterminated, the contents of the EEPROM are not writteninto the MI registers, and the default values remain in theMI registers.
Table 9. EEI To MI Register Correspondance
EE_CS EEI MI Register Written ToCycle Register
Read Out(REG[5:0]) Address Name
1 000001 ----- -----
2 000011 00000 Control
3 000111 00001 Status
4 001111 00010 PHY ID #1
5 011111 00011 PHY ID #2
6 111111 10000 Configuration
3.19.4 EE_CS Cycle Structure
A description of the EE_CS cycle structure is shown inTable 10 and in Figure 6. Each EE_CS cycle consists of25 bits. The first 9 bits of an EE_CS cycle are always readbits and are used to provide instructions and registeraddressing to the external EEPROM. The last 16 bits arewrite bits and are loaded from the external EEPROM intoone of the MI registers per Table 9 and Figure 6.
The first bit in a EE_CS cycle is read out on the EEI as a1 and instructs the external EEPROM to start an accesscycle. The next two bits are read out as a 10 and containthe opcode instruction for the external EEPROM toexecute a read cycle. The next 6 bits are one of six registeraddresses read out to the external EEPROM and containthe address of the 16 bit register in the external EEPROMwhere the data is to be fetched. On the same clock cyclethat the last register address bit is read out to the externalEEPROM, the external EEPROM may also send back a"0" on EE_DO. The 8502 ignores this "0" data. The next16 bits are written into the 8502 from the EEPROM and arewritten into a specific MI register as shown in Table 9 andFigure 6.
There are three individual MI bits whose value will not bemodified or should not be modified through the EII: (1)Reset, bit 0.15, (2) Link Detect, bit 1.2, and (3) JabberDetect, 1.1. The Reset bit should not be modified throughthe EEI and should only be set to a 1 via a MI write to thatbit; the Link Detect and Jabber Detect bits will not bemodified by the EEI, so refer to the Link and Jabbersections for more details how these bits are set and reset.
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3.19.5 Timing
The total EEI cycle consists of six individual EE_CScycles, one for each register accessed over the EEI.Before a reset is initiated, the EEI is in the idle state. Duringidle, EE_CS=0, EE_DO is in the high impedance state,EE_DI is ignored, and EE_CLK clock output is held low.When a reset is initiated, then EE_CS is asserted high,EE_CLK clock output is enabled, and a serial shift cycle isinitiated between the external EEPROM and the 8502.Data on EE_DO is then shifted out from the 8502 to theEEPROM on the first 9 falling edges of EE_CLK. On thenext 16 falling edges of EE_CLK, data is shifted into the
8502 from the EEPROM on EE_DI (EE_DO is highimpedance). After 25 EE_CLK cycles have been com-pleted, EE_CS goes low, EE_DO goes to high impedance,EE_DI stops latching in data, the last 16 data bits shiftedin are latched into the 8502, and the serial shifting processis halted. This process is repeated five more times, oncefor each of the five internal MI registers as shown in Tables10 and 11 and Figure 6. Once all six EE_CS access cycleshave been completed, then the EEI returns to the idlestate.
Table 10. EEI EE_CS Cycle Structure
<1> <10> <Register Addr.> <Data>START OP[1:0] A[5:0] D[15:0]
000001 Identification000011 MI Register 0000111 MI Register 1001111 MI Register 2011111 MI Register 3111111 MI Register 16
Symbol Name Definition R/W
START Start Bit 1 Read Out To EEPROM On Every EE_CS Cycle R
OP[1:0] EEPROM Opcode 10 Read Out To EEPROM On Every EE_CS Cycle RInstruction
A[5:0] EEPROM EEPROM Register Address Where Data Will Be Fetched on RRegister Address Each of the 6 EE_CS Cycles and Loaded into the MI Registers
as Shown in Table 10 And Figure 6.
D[15:0] MI Data These 16 Bits Contain Data Written from the External EEPROM W into the MI Registers According to Table 10. The FirstRegister Written from Regad = 000001 must ContainA07d16 for the Access to Continue.
START is Shifted Out First
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Figure 7. External MII-AUI Schematic Using 8502
MIICONNECTOR
TX_CLK
TXD3
TXD2
TXD1
TXD0
TX_EN
COL
RX_CLK
RXD3
RXD2
RXD1
RXD0
CRS
RX_DV
MDC
MDIO
8502
OSCIN
20 MHz
V [2:1]CC
DO+
DO–
1:1
DI+
DI–
1:1
CI+
CI–
1:1
391%
391%
24.91%
1.5K5%
V / GNDCC2
8502
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27
Figure 8. External MII-AUI Schematic Using 8502 with EEPROM and LED’s
RX_DV
MDC
MDIO
OSCIN
20 MHz
DO+
DO–
DI+
DI–
CI+
CI–
DB15
1:1
1:1
1:1
391%
MIICONNECTOR
TX_CLK
TXD3
TXD2
TXD1
TXD0
TX_EN
COL
RX_CLK
RXD3
RXD2
RXD1
RXD0
CRS
8502
V [2:1]CC24.91%
1.5K5%
/ GND2
8502
4-28
MD400157/D
28
Figure 9. External MII-Coax PHY Schematic Using 8502
MIICONNECTOR
TX_CLK
TXD3
TXD2
TXD1
TXD0
TX_EN
COL
RX_CLK
RXD3
RXD2
RXD1
RXD0
CRS
RX_DV
MDC
MDIO
8502
OSCIN
20 MHz
V [2:1]CC
DO+
DO–
DI+
DI–
CI+
CI–
GND [2:1]
11
REXT
24.91%
1.5K5%
SEEQEM2C
V / GNDCC2
8502
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29
Figure 10. Network Interface Card Schematic Using 8502
SEEQ80C300
ETHERNETCONTROLLER
TX_CLK
TXD3
TXD2
TXD1
TXD0
TX_EN
COL
RX_CLK
RXD3
RXD2
RXD1
RXD0
CRS
RX_DV
MDC
MDIO
8502
OSCIN
20 MHz
V [2:1]CC
DO–
DI–
CI–
1:1
1:1
1:1
DB15COMPUTERBUS
V / GNDCC2
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30
4.3 AUI RECEIVE INTERFACE
Receive data is typically transformer coupled into thereceive inputs on DI± and terminated with an externalresistor as shown in Figures 7-10.
The AUI transformer specifications for the receiver areshown in Table 11. Some sources for the AUI transformerare listed in Table 12, but most standard AUI transformersshould meet these requirements.
Table 12. AUI Transformer Sources
Vendor Part Number
Valor ST7033
NanoPulse 5421-30
Pulse Engineering PE65728
Belfuse S553-1006-AE
PCA EPA 1885-6
The receive input needs to be terminated with 78 Ohms inorder to meet input impedance requirements of IEEE802.3 Section 7. Notice that in Figures 7, 8 and 10 thereceive input has this input termination resistor broken upinto two 39 ohm 1% resistors with a 0.1µF capacitor tiedbetween the center points and GND. This capacitorattenuates common mode input noise. The 0.1µF capaci-tor is optional and is only needed if the device is requiredto meet the receive common mode input AC voltagespecification in IEEE 802.3 Section 7. The 0.1µF capaci-tors are not needed if the AUI is embedded, that is,restricted to a PCB or other piece of equipment wherecommon mode noise is small on the AUI inputs. If thecapacitor is not needed, then the two termination resistorscan be lumped into one 78 Ohm 1% resistor across DI±.
In order to minimize noise pickup into the receive path,loading on DI± should be minimized and both inputsshould be loaded equally.
4.0 APPLICATION INFORMATION4.1 EXAMPLE SCHEMATICS
Typical examples of the 8502 used in external MII-AUI,external PHY, and Network Interface Card application areshown in Figures 7-10. Figure 7 is the 8502 used in anexternal MII-AUI application. Figure 8 is the 8502 used inan external MII-AUI application with LED's and externalEEPROM. Figure 9 is the 8502 used in an external MII-COAX PHY application. Figure 10 is the 8502 in a NetworkInterface Card application.
4.2 AUI TRANSMIT INTERFACE
The interface between the AUI outputs on DO± and theAUI cable requires a transformer as shown in Figures 7-10. A 10K resistor is also needed between RBIAS pin andGND to provide internal bias for the transmitter. Forproper AUI output levels, the DO± outputs must be con-nected to a 78 Ohm cable or some other 78 Ohm load. Noother external components are required.
The AUI transformer specifications for the transmitter areshown in Table 11. Some sources for the AUI transformerare listed in Table 12, but most standard AUI transformersshould meet these requirements.
Table 11. AUI Transformer Specification
Parameter Specification
Turns Ratio 1:1
Inductance 75(µH Min)
Leakage Inductance 0.4(µH Max)
Capacitance (pF Max) 10
DC Resistance 0.25(Ohms Max)
To minimize noise pickup, the loading on DO± should beminimized and both outputs should always be loadedequally.
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4.4 CONTROLLER INTERFACE
4.4.1 General
The 8502 will connect to any Ethernet controller withoutany glue logic provided that the external Ethernet control-ler has a MII interface that complies with IEEE 802.3.
4.4.2 Output Drivers
The digital outputs on the 8502 MII signals can meet theexternal MII driver characteristics specified in IEEE 802.3and shown in Figure 11 if external 24.9 ohm 1% termina-tion resistors are added. These termination resistors areonly needed if the outputs have to drive a MII cable or othertransmission line type load, such as in the external MIIapplications shown in Figures 7-10. If the 8502 is used ininternal MII applications such as adapter cards or on amotherboard, then these termination resistors are notneeded, as shown in the schematic in Figure 10.
Figure 11. MII Output Driver Characteristics
4.4.3 MII Disable
The MII inputs and outputs can be disabled by setting theMII disable bit in the MI serial port Control register. Whenthe MII is disabled, the MII inputs don't respond to any inputsignals and the MII outputs are placed in the high imped-ance state. The default value of this bit when the devicepowers up or is reset is dependent on the device address.If the device address latched into MDA[1:0] at reset is not11, it is assumed that the device is being used in applica-tions where it is the only device on the MII bus, like adaptercard, and the device powers up with the MII enabled. If thedevice address latched into MDA[1:0] at reset is 11, it isassumed that the device is being used in application wheremany devices could be sharing the same MII bus, like anexternal PHY, and the device powers up with the MIIdisabled.
V3I 3
I 4
V4
Rol min
Iol
VolVoh
VCC
I 2V2
I 1
V1
Rol min
Ioh
I - V I (mA) V (Volts)
I1, V1 –20 1.10
I2, V2 –4 2.4
I3, V3 4 0.40
I4, V4 43 3.05
Rohmin Rolmin equals 40 ohms
8502
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4.5 MI SERIAL PORT
4.5.1 General
The 8502 has a MI serial port to set all of the devices'sconfiguration inputs and read out the status outputs. Anyexternal device that has a IEEE 802.3 compliant MI inter-face can connect directly to the 8502 without any gluelogic, as shown in Figures 7-10.
As described earlier, the MI serial port consists of 4 lines:MDC, MDIO, and MDA[1:0]. However, only 2 lines, MDCand MDIO, are needed to shift data in and out. MDA[1:0]are provided for convenience only.
The MDA[1:0] addresses are inverted inside the 8502before going to the MI serial port block. For example, theMDA[1:0] pins would have to be pin strapped to 11 exter-nally in order to successfully match the MI physical ad-dress bits PHYAD[1:0]=00 internally.
4.5.2 Multiple Register Access
If the MI serial port needs to be constantly polled in orderto monitor changes in status output bits, all registers canbe accessed on a single MI serial port access cycle bysetting the register address REGAD[4:0]=11111 with themultiple register access mode enabled. This eliminatesthe need to poll registers individually. Multiple registeraccess is normally disabled but can be enabled by settingthe multiple register access bit in the MI serial port Configu-ration register.
4.5.3 Serial Port Addressing
The device address for the MI serial port is selected bytying the MDA[1:0] pins to the desired value. MDA[1:0]share the same pins as the PLED[1:0] outputs, respec-tively, as shown in Figure 12a. At powerup or reset, theoutput drivers are high impedance for an interval called thepoweron reset time. During the power on reset interval, thevalue on these pins is latched into the device, inverted, andused as the MI serial port address. The LED outputs areopen drain with internal resistor pullup to VCC.
If an LED is desired on the LED outputs, then an LED andresistor are tied to VCC as shown in Figures 12b. If a highaddress is desired, then the LED to VCC automaticallymakes the latched address value a high. If a low value forthe address is desired, then a 50K resistor to GND must beadded as shown in Figure 12b.
If no LED's are needed on the LED outputs, the selectionof addresses can be done without any external compo-nents as shown in Figure 12c. If a high address is desired,the pin should be left floating and the internal pullup will pullthe pin high during power on reset and latch in a highaddress value. If a low address is desired, then the outputpin should be tied to GND or tied to GND through an
optional 10K resistor as shown in Figure 12c. The optional10K resistor allows the pin to be used as a digital outputunder normal conditions.
4.6 RESET
The reset function in the 8502 resets all the internal timers,sets all the input configuration bits in the MI serial port totheir default values, loads data into the MI from an externalEEPROM (if connected), and latches in the physical ad-dress values for the serial port on MDA[1:0]. Reset can beinitiated internally or externally.
An internal reset automatically occurs when VCC isapplied to the 8502 or when the device comes out of thepowerdown state.
An external reset can be initiated by setting the reset bit inthe serial port Control register. Setting this bit will createa reset and this bit will clear itself automatically when thereset is completed.
It is not necessary to use the reset function in normaloperation; it is available if external control of reset isdesired.
4.7 EXTERNAL EEPROM
The EEI is intended as an inexpensive and convenient wayto override the MI serial port default values with a userdefined set. The EEI provides a glueless interface to theindustry standard 9346 EEPROM. The 8502 can auto-matically detect whether an external EEPROM is present,so no configuration is necessary. The schematic in Figure8 shows how an external 9346 EEPROM can be con-nected directly to the 8502. A device other than the 9346can be connected to the EEI provided it complies with thetiming and frame structure of the EEI.
One unique feature of the EEI is that it can modify thedefault values of the read bits in the MI. Normally, when theread bits are accessed through the MI, they can only beread out and cannot be written into. When the read bits areaccessed through the EEI, however, they become writebits and can be overwritten by the contents of theEEPROM. This feature allows the user to modify the OUIand other capability bits to match the characteristics of theend equipment, not the 8502 itself.
If an external EEPROM or other device is used with the EEIto override the MI register default values, the EEPROMneeds to be programmed according to the EEPROMmemory map shown in Table 14. In Table 14, the namesfor individual bit locations correspond to the MI register bitnames, and values in these register locations in theEEPROM will be automatically loaded into the corre-sponding MI bit locations when a reset is initiated.
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33
Note that the value of the Reset bit should always bewritten as a 0 from the EEI; if it is written to a 1, the devicewill be resetting for eternity. Also note that the Link Detectand Jabber Detect bits are not overwritten by the EEI. Alsonote that there are some reserved bits in the Configurationregister that must be written to specific values for thedevice to function properly.
4.8 OSCILLATOR
The 8502 requires a 20 Mhz reference frequency forinternal signal generation. This 20 Mhz reference fre-quency can be generated by either connecting an external20 MHz crystal between OSCIN and GND or by applyingan external 20 MHz clock to OSCIN.
If the crystal oscillator is used, it needs only an externalcrystal, and no other external capacitors or other compo-nents are required. The crystal must have the character-istics shown in Table 13. The crystal must be placed asclose as possible to OSCIN and GND so that parasitics onOSCIN are kept to a minimum.
Table 13. Crystal Specifications
Parameter Spec
Type Parallel Resonant
Frequency 20 Mhz +/- 0.01%
Equivelent Series 25 ohms maxResistance
Load Capacitance 18 pF typ
Case Capacitance 7 pF max
Power Dissipation 1mW max
The normal function for PLED1 can be changed fromCollision to Link Detect by setting the PLED1 configurationselect bit in the MI serial port Configuration register.
The On and Off functions allow the LED driver to becontrolled directly through the MI serial port to indicate anyfunction that is desired under external control. The Blinkfunction allows the same external control of the LED driverand also offers the provision to blink the LED without theneed for any external timers.
The PLED[1:0] outputs can also drive other digital inputs.Thus, PLED[1:0] can also be used as digital outputswhose function can be user defined and controlledthrough the MI serial port.
4.10 LINK PASSTHROUGH
The LINKI pin can be used to force the status reported onthe MI serial port Link Status output bit. If LINKI is tied tothe Link Status output pin from an external transceiver, thelink status from the external transceiver will be invertedand passed through to and be reported on the Link Statusbit in the MI Status register.
4.11 JABBER PASSTHROUGH
The JABI pin is can be used to force the status reported onthe MI serial port Jabber Detect output bit. If JABI is tiedto the Jabber Detect output pin from an external trans-ceiver, the Jabber Detect status from the external trans-ceiver will be inverted and passed through to and bereported on the Jabber Detect bit in the MI Status register.
4.12 POWER SUPPLY DECOUPLING
There are two VCC's on the 8502 (VCC[2:1]) and twoGND's (GND[2:1]).
Both VCC's should be connected together as close aspossible to the device with a large VCC plane. If the VCC'svary in potential by even a small amount, noise and latchupcan result. The two VCC's should be kept to within 50 mVof each other.
Both GND's should also be connected together as close aspossible to the device with a large ground plane. If theGND's vary in potential by even a small amount, noise andlatchup can result. The two VCC's should be kept to within50 mV of each other.
A 0.01-0.1 µF decoupling capacitor should be connectedbetween each VCC/GND set as close as possible to thedevice pins, preferably within 0.5". The value of thedecoupling capacitor should be selected based onwhether the noise on VCC-GND is high or low frequency.A conservative approach would be to use two decoupling
4.9 PROGRAMMABLE LED DRIVERS
The PLED[1:0] outputs can drive LED's tied to VCC asshown in Figure 6. The PLED[1:0] outputs can be pro-grammed through the MI serial port to do 4 differentfunctions: (1) Normal Function (2) On, (3) Off, and (4)Blink. PLED[1:0] can be programmed by appropriatelysetting the LED output select bits in the MI serial portConfiguration register. When PLED[1:0] is programmedfor its Normal function, these outputs indicate the specificfunctions described in the MI serial port Configurationregister shown on Table 10 (Collision, Activity). WhenPLED[1:0] is programmed to be On, the LED output drivergoes low, thus turning on the LED under user control.When PLED[1:0] is programmed to be Off, the LED outputdriver will turn off, thus turning off the LED under usercontrol. When PLED[1:0] is programmed to Blink, the LEDoutput driver will continuously blink at a rate of 100 mS on,100 mS off.
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5.0 Specifications
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are limits beyond which maycause permanent damage to the device or affect devicereliability. All voltages are specified with respect to GND,GND unless otherwise specified.
VCC Supply Voltage ........................................ –3V to 7V
All Inputs and Outputs ............................ –3V to VCC+.3V
Input Latchup Current ..................................... +/-25 mA
Package Power Dissipation ................... 3 Watt @ 25°C
Storage Temperature .............................. –65 to +150°C
Operating Temperature ............................. –65 to +85°C
Lead Temperature (Soldering, 10 Sec) ................ 250°C
capacitors on each VCC/GND set, one 0.1µF for lowfreuqency and one 0.001µF for high frequency noise onthe power supply.
The PCB layout and power supply decoupling discussedabove should provide sufficient decoupling to acheive thefollowing when measured at the device: (1) the resultantAC noise voltage measured across each VCC/GND setshould be less than 100 mVpp, (2) all VCC's should bewithin 50 mVpp of each other, and (3) all GND's should bewithin 50 mVpp of each other.
Figure 12. MI Serial Port Address Selection
a.) OUTPUT DRIVER / INPUT ADDRESS CORRESPONDENCE
b.) SETTING ADDRESS WITH LEDs
c.) SETTING ADDRESS WITHOUT LEDs
500 500
50 K
HIGH LOW
PLED1
PLED0
PLED1
PLED0
HIGH LOW
FLOAT PLED1
PLED0
PLED1
PLED0
MDA1
MDA0
PLED1
PLED0
10 K(OPTIONAL)
8502
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35
x.6
x.7
8x.
3x.
0x.
5x.
4x.
1x.
2
M M
emor
y M
ap
01
11
11
10
CO
LTS
TLX
OU
I12
OU
I11
0O
UI1
5O
UI1
7O
UI1
3O
UI1
4O
UI1
8O
UI1
6
PA
RT
2P
AR
T3
T4
RE
V3
RE
V1
PA
RT
1P
AR
T0
RE
V0
RE
V2
AN
EG
_AC
KC
AP
_SU
PR
CA
P_N
WY
RE
M_F
LTLI
NK
EX
RE
GJA
B
00
00
0
00
0
8502
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MD400157/D
36
DC Electrical Characteristics
Unless otherwise noted, all test conditions are as follows:
1. TA = 0 to 70°C 2. VCC = 5V +/-5% 3. 20 MHz +/- 0.01% 4. RBIAS = 10K +/- 1%, no load
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
VIL Input Low Voltage 0.8 Volt All except OSCIN, MDA[1:0], LINKI
VCC–1.0 Volt MDA[1:0]
1.5 Volt OSCIN
0.5 Volt LINKI
VIM Input Intermediate 1.5 VCC–1.5 Volt LINKIVoltage
VIH Input High Voltage 2 Volt All except OSCIN, MDA[1:0],LINKI
VCC– 0.3 Volt MDA[1:0]
3.5 Volt OSCIN
VCC– 0.5 Volt LINKI
IIL Input Low Current -1 µA VIN = GNDAll Except MDA[1:0], OSCIN,EE_DI, LINKI
-12 -50 µA VIN = GNDEE_DI
- 5 -25 µA VIN = GND MDA [1:0]
-150 µA VIN = GND OSCIN, LINKI
IIH Input High Current 1 µA VIN = VCCAll Except OSCIN, LINKI
150 µA VIN = VCCOSCIN, LINKI
VOL Output Low Voltage 0.4 Volt IOL = _4mAAll except PLED[1:0]
1 Volt IOL = -20 mAPLED[1:0]
VOH Output High Voltage VCC - 1.0 Volt IOH = 4 mAAll except PLED[1:0], XMT_LED, RCV_LED
VCC - 1.0 Volt IOH = 10 mA, XMT_LED, RCV_LED
2.4 Volt IOH = 4µAPLED[1:0]
CIN Input Capacitance 5 pF
ICC VCC Supply Current 85 110 mA Transmitting
1.3 3.06 mA Powerdown Mode
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37
AUI CHARACTERISTICS, TRANSMIT
Unless otherwise noted, all test conditions are as follows:
1. TA = 0 to 70°C 2. VCC = 5V +/-5% 3. 10 MHz +/- 0.01% 4. RBIAS = 10K +/- 1% 5. 78 ohm, 27µH load across DO±
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
TOV DO± Differential 550 1200 mV pkOutput Voltage
TOVT DO± Differential Output See Figure 3Voltage Template
TORF DO± Output Rise And 5 nS tr, tf measured at –450 mV and +450Fall Time mV points
TOJ Transmit Output Jitter ± 0.5 nS
TOIV DO± Differential Output +/– 40 mVIdle Voltage
TOVU DO± Differential Output –100 mVUndershoot During Idle
TCMD DO± Common Mode VCC/4 mV pk Voltage on Either DO+ or DO–DC Output Voltage +0.5 Relative to GND
8502
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38
AUI CHARACTERISTICS, RECEIVE
Unless otherwise noted, all test conditions are as follows:
1. TA = 0 to 70°C 2. VCC = 5V +/-5% 3. 10 MHz +/- 0.01% 4. RBIAS = 10K +/- 1% 5. 10 MHz sinewave on DI±, C±
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
RST DI±, CI± Squelch –175 –325 mVThreshold
RUT DI±, CI± Unsquelch –100 –225 mVThreshold
ROCV DI±, CI± Input Open 3.0 Volt Voltage on Either DI+/CI+ or DI–/CI–Circuit Voltage ±0.5 Relative to GND.
RCMR DI±, CI± Input ROCV VoltCommon Mode Voltage ±0.5Range
RDR DI±, CI± Input GND VCC Volt Voltage on Either DI+/CI+ or
Differential Voltage DI–/CI– Relative to GND.Range
RIR DI±, CI± Input 5K OhmResistance
RIC DI±, CI± Input 10 pFCapacitance
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39
AC Test Timing Conditions
Unless otherwise noted, all test conditions are as follows:
1. TA = 0 to 70°C 2. VCC = 5V +/-5% 3. 20 MHz +/- 0.01% 4. RBIAS = 10K +/- 1%, no load 5. Input conditions: All Inputs: tr, tf <= 10nS, 20-80% 6. Output Loading DO±: 78 Ω, 27 µH Open Drain Outputs: 1K Ω Pullup, 50 pF All Other Digital Outputs: 50pF 7. Measurement Points: DO±, DI±, CI±: 0.0V During Data, ±0.3V at start/end of packet All other inputs and outputs: 1.5 Volts
20 MHz Clock Timing Charateristics
Refer To Figure 13 For Timing Diagram
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
t1 OSCIN Cycle Time 49.995 50 50.005 nS
t2 OSCIN High Time 15 nS OSCIN Driven by External Clock
t3 OSCIN Low Time 15 nS OSCIN Driven by External Clock
t4 OSCIN To TX_CLK 20 nSDelay
Figure 13. 20 MHz Clock Timing
TX_CLK
t 1
OSCIN
t 4 t
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40
Transmit Timing Charateristics
Refer To Figure 14 For Timing Diagram
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
t11 TX_CLK Cycle Time 399.96 400 400.04 nS
t12 TX_CLK High Time 160 200 240 nS
t13 TX_CLK Low Time 160 200 240 nS
t14 TX_CLK Rise/Fall Time 10 nS
t15 TX_EN Setup Time 40 nS
t16 TX_EN Hold Time 0 nS
t17 CRS During Transmit 40 nS TXEN_CRS=1Assert Time
t18 CRS During Transmit 40 nSDeassert Time
t19 TXD Setup Time 40 nS
t20 TXD Hold Time 0 nS
t23 Transmit Propagation 200 nSDelay
t24 Transmit Output Jitter ± 0.5 nS
t25 Transmit SOI Pulse 225 350 nSWidth To 0.3V
t26 Transmit SOI Pulse 7000 nSWidth to 40 mV
t27 PLED0 Assert Time 55 mS PLED0 Programmed For Activity
t28 PLED0 Pulse Width 45 55 mS PLED0 Programmed For Activity
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41
TXD [3:0]
t
PLED0
TX_CLK
TXEN
CRS
DO±
t 27
t 19
t 16t 15 t
t 17 t18
N0 N3N2N1
t 20
PREAMBLE PREAMBLE
t 23
SOI
[1]
Note 1. CRS is asserted only when TX_EN to CRS Loopback select bit is programmed in MI Serial Port. Default is TX_EN to CRS Loopback Disabled.
Figure 14. Transmit Timing
8502
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42
Receive Timing Charateristics
Refer To Figures 15 And 16 For Timing Diagram
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
t31 Start Of Packet To CRS 100 nSAssert Delay
t32 End Of Packet To CRS 250 nSDeassert Delay
t33 Start Of Packet To 2000 nSRX_DV Assert Delay
t34 End Of Packet To 900 nSRX_DV Deassert Delay
t36 Start Of Packet To First 7300 nS Data Nibble Delay
t37 RX_CLK To RX_DV, 0 25 nSRXD Delay
t38 RX_CLK High Time 180 200 220 nS
t39 RX_CLK Low Time 180 200 1200 nS
t40 Minimum SOI Pulse 125 200 nS Measure On DI± from last zero crossWidth Required For Idle in Middle of Manchester Bit Cell toDetection 0.3V point.
t41 Receive Input Jitter ±18.0 nS Data
±12.0 nS Preamble
t42 PLED0 Assert Time 55 mS PLED0 Programmed For Activity
t43 PLED0 Pulse Width 45 55 mS PLED0 Programmed For Activity
t44 RX_CLK, RXD, CRS, 10 nSRX_DV Output RiseAnd Fall Times
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Figure 16. Receive Timing, End of Packet
RX_DV
DI±
CRS
RX_CLK
t 32
t 34
RXRXRX RXRXRXRX TX
DATADATA DATADATA DATA
tt
t 40
SOI
RXD [3:0] DATA DATADATADATADATADATADATA
Figure 15. Receive Timing, Start of Packet
RX_DV
t
PLED0
DI±
CRS
RX_CLK
RXD [3:0]
t 42
t 31
t 38
t 33
DATA
TX TX TX TX TX
t
t
RX
t
t 36
DATA
8502
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44
Collision Timing Characteristics
Refer To Figures 17 and 18 For Timing Diagram
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
t51 CI± Start To COL 200 nSAssert Time
t52 CI± Stop To COL 400 nSDeassert Time
t53 CI± Start To CRS 200 nSAssert Time
t54 Minimum CI± Pulse 10 35 nSWidth Required ForCollision Detection
t55 CI± Minimum Cycle 48 77 nS
Time Required ForCollision Detection
t56 CI± Maximum Cycle 200 400 nSTime Required ForCollision Detection
t57 COL Rise And Fall 10 nSTime
t58 PLED1 Assert Time 55 mS PLED1 Programmed For Collision
t59 PLED1 Pulse Width 45 55 mS PLED1 Programmed For Collision
t60 Collision Test Assert 100 nSTime
t61 Collision Test Deassert 40 nSTime
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45
Figure 18. Collision Test Timing
Figure 17. Collision Timing
CI±
COL
CRS
PLED1
t 55 t 56
t 54 t 54t 51 t 52
t 53
t 58 t 59
t 60
COL
t 61
TX_EN
8502
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46
LED Driver Timing Characteristics
Refer To Figure 19 For Timing Diagram
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
t66 PLED[1:0] XMT_LED, RCV_LED, On Time 45 55 mS
t67 PLED[1:0] XMT_LED, RCV_LED, Off Time 45 55 mS
Figure 19. LED Driver Timing
t 66
PLED [1:0]
t 67
t 66
XMT_LED
t 67
RCV_LED
8502
4-47
MD400157/D
47
MI Serial Port Timing Characteristics
Refer To Figure 20 For Timing Diagram
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
t71 MDC High Time 20 nS
t72 MDC Low Time 20 nS
t73 MDIO Setup Time 10 nS Write Bits
t74 MDIO Hold Time 10 nS Write Bits
t75 MDC To MDIO Delay 20 nS Read Bits
t76 MDIO Hi-Z To Active 20 nS Write-Read Bit TransitionDelay
t77 MDIO Active To HI-Z 20 nS Read-Write Bit TransitionDelay
t78 Frame Delimiter (Idle) 32 Clocks MDC Clocks With MDIO=1's
Figure 20. MI Serial Port Timing
MDIO(READ)
MDIO(WRITE)
DATA 15TA0
tt
t 7673t 74t
REGAD0ST1 ST0
TA0 DATA 15TA1ST0ST1 REGAD0
73t 74t
TA1
t 71
MDC 0 131 14 15 16
t 72
8502
4-48
MD400157/D
48
EEI Timing Characteristics
Refer To Figure 21 For Timing Diagram
LIMIT
SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
t81 EE_CS Setup Time 1800 nS
t82 EE_CS Hold Time 50 nS
t83 EE_CLK High Time 3800 4000 4200 nS
t84 EE_CLK Low Time 3800 4000 4200 nS
t85 EE_CLK To EE_DO 500 nS Read BitsDelay
t86 EE_DI Setup Time 500 nS Write Bits
t87 EE_DI Hold Time 0 nS Write Bits
t88 EE_DO Hi-Z To Active 500 nS Write-Read Bit TransitionDelay
t89 EE_DO Active To HI-Z 500 nS Read-Write Bit TransitionDelay
t90 EE_CS Deassert Time 7600 8000 8400 nS
8502
4-49
MD400157/D
49
t 90
910
1112
2324
t 82
t 86t 87
D15
D14
D13
D0
D1
Fig
ure
21.
EE
I Tim
ing
8502
4-50
MD400157/D
50
Ordering Information
Revision History
9/23/96
Page 11, First Paragraph:- Reference to 75-200 nS has been changed to 77-200 nS.- Reference to 50 nS has been changed to 48 nS.- Reference to 15 nS has been changed to 10 nS.
Page 26, Figure 7: References to 49 1 % resistors has changed to 39 1%.Page 27, Figure 8: References to 49 1 % resistors has changed to 39 1%.
- Figure 8 Resistors 500 and LEDs have been flipped.Page 29, Figure 10: References to 49 1 % resistors has changed to 39 1%.Page 32, First column, last paragraph copy has been added, end of paragraph now reads:
- ...tied to GND or tied to GND through an optional 10K resistor as shown in Figure 12c. The optional 10K resistor allows the pin to be used as a digital output under normal conditions.
Page 34, Figure 12b. Resistors 500 and LEDs have been flipped.- Figure 12c. Setting Address Without LEDs:- 10K Resistor (Optional) has been added.
Page 36, DC Electrical Characteristics:- VIL (max) 0.8 Conditions now reads, All except OSCIN, MDA[1:0], LINKI.- VIL (max) 0.5, row has been added.- VIM (max) has changed from 3.0 to VCC–1.5.- VIH (min) 3.5 Conditions is now OSCIN.- VIH (min) VCC–0.5, row has been added.- VIH (min) VCC–0.5, row has been added.- IIL (min) –12 Conditions is now VIN = GND, EE_DI.- IIL (min) –5, row has been added.- IIH Conditions has been changed from VIN = VCC C to VIN = VCC.- VOH (min) 4 Conditions, has been changed from IOL = 4mA to IOH = 4mA.- VOH (min) 2.4 Conditions, has changed from IOL = 12µA to IOH = 5µA.- ICC (max) has been changed from 85 to 70.- ICC (max) has been changed from 0.1 to 1.0.- ICC (max) 35 row has been deleted.
N
PACKAGETYPE
TEMPERATURERANGE
PART TYPE
Q – 0°C to +70°C Ethernet MII to AUIInterface Adapter
8502Q
Chip Carrier N = Plastic Leaded
8502
4-51
MD400157/D
51
Page 37, AUI Characteristics, Transmit:- TOV (max) is now 1200.- TOV (unit) is now mV pk.- TCMD (min) VCC/3–0.5 has been deleted.- TCMD (typ) has changed VCC/3 to VCC/4 ±0.5.- TCMD (max) VCC/3 + 0.5 has been deleted.- TCMD Conditions now reads; Voltage on Either DO+ or DO– Relative to GND.- TCMA has been deleted.- TOR has been deleted.- TOC has been deleted.
Page 38, AUI Characteristics, Receive:- ROCV Parameter now reads; DI±, CI± Input Open Circuit Voltage.- ROCV (min) has been deleted.- ROCV (typ) has changed from VCC/2 to VCC2 ± 0.5.- ROCV (max) has been deleted.- ROCV Conditions is now; Voltage on Either DI+/CI+ or DI–/CI_ Relative to GND.- RCMR (min) has been deleted.- RCMR (typ) is now; VCC/2 ± 1.0.- RCMR (max) has been deleted.- RDR Conditions is now; Voltage on Either DI+/CI+ or DI–/CI– Relative to GND.
Page 39, 20 MHz Clock Timing Characteristics- t2 Conditions is now; OSCIN Driven by External Clock.- t3 Conditions is now; OSCIN Driven by External Clock.
Page 40, Transmit Timing Characteristics:- t15 (min) has changed from 25 to 40.- t19 (min) has changed from 25 to 40.- t25 (min) has changed from 250 to 225.- t27 (max) has changed from 105 to 55.- t28 (min) has changed from 95 to 45.- t28 (max) has changed from 105 to 55.
Page 43, Figure 15: RXD[3:0] has changed; additional DATA reference.Page 44, Collision Timing Characteristics:
- t52 (max) has changed from 450 to 400.- t53 Parameter now reads; CI± Start to CRS Assert Time.- t53 (max) has changed from 400 to 200.- t54 Parameter now reads; Minimum CI± Pulse Width Required for Collision Detection.- t54 (min) has changed from 17.6 to 10.- t55 (min) has changed from 50 to 48.- t55 (max) has changed from 75 to 77.- t58 (max) has changed from 105 to 55.- t59 (min) has changed from 95 to 45.- t59 (max) has changed from 105 to 55.- t60 (max) has changed from 5.12 to 100.- t60 (unit) has changed from µS to nS.
Page 45, Figure 17; CRS has changed.Page 46, LED Driver Timing Characteristics:
- t66 (min) has changed from 95 to 45.- t66 (max) has changed from 105 to 55.- t67 (min) has changed from 95 to 45.- t67 (max) has changed from 105 to 55.
Revision History
8502
4-52
MD400157/D
52
Page 48, EEI Timing Characteristics:- t86 (min) is now 500.- t86 (max) has been deleted.- t87 (min) is now 0.- t87 (max) has been deleted.
6/23/97
Document Revision Changed to MD400157/B
Page 1, Features:- LED Outputs, Activity; has been changed to Activity, Transmit, Receive.- NOTES 1. 8502 only, has been added. Refers to features, LED Outputs, and Interface to External E2
PROM for Automatic Preloading of MI Serial Port Bits.- Pin Configuration 8502 44 PLCC; Pin #11 EE_CLK has been changed to EE_CLK/XMT_LED, and Pin #12 EE_DO has been changed to EE_DO/RCV_LED.
Page 4, Pin Description continued:- Pin #11, Pin Name; EE_CLK has been changed to EE_CLK/XMT_LED- Pin #11, Description, copy change; External EEPROM Clock Output has been changed to External EEPROM Clock Output Transmit LED.- Pin #11, Description, copy; During normal operation, this pin can be used as Transmit LED and can drive an LED to GND.
0 = No Detect 1 = Transmit Activity Detected, On for 50 mS.
copy has been added.
- Pin #12, Pin Name; EE_DO has been changed to EE_DO/RCV_LED- Pin #12, Description, copy change; External EEPROM Clock Output has been changed to External EEPROM Clock Output Receive LED.- Pin #12, Description, copy; During normal operation, this pin can be used as Receive LED and can drive an LED to GND.
0 = No Detect 1 = Receive Activity Detected, On for 50 mS.
copy has been added.
Page 5, 1.0 Pin Description continued:- Pin #5 Description; reference to 100 mS has been changed to 50 mS.- Pin #4 Description; reference to 100 mS has been changed to 50 mS.
Page 6, Figure 1. 8501, 8502 Block Diagram:- References to EE_CLK has been changed to EE_CLK/XMT_LED and EE_DO has been changed to EE_DO/RCV _LED.
Page 10, Section 3.6.2 Transmit Activity Indication:- First paragraph, reference to 100 mS has been changed to 50mS.- New second paragraph copy; XMT_LED is transmit activity output during normal operation. This pin is asserted high for 50 mS every time a transmit packet occurs. The XMT_LED output can drive an LED to GND or can drive another digital input.- Paragraph three copy has been changed from ... The PLED0 pin is only available on the 8502 (44L) ... to... The PLED0 and XMT_LED pins are only available on the 8502 (44L).- Section 3.7.1 Receiver; Paragraphs 2, and 3 references to VCC/2 have been changed to, about 3.
Revision History
8502
4-53
MD400157/D
53
Page 10, Section 3.7.3 Receive Activity Indication; reference to 100 mS has been changed to 50 mS.- New paragraph two copy; RCV_LED is receive activity output during normal operation. This pin is asserted high for 50 mS every time a receive packet occurs. The RCV_LED output can drive an LED to GND or can drive another digital input.- Paragraph three copy has been changed from ...The PLED0 pin is only available on the 8502 (44L)... to ...The PLED0 and RCV_LED pins are only available on the 8502 (44L).
Page 11, Section 3.8.3 Collision Indication- Reference to 100 mS has been changed to 50 mS.
Page 12, - Section 3.15 POWERDOWN; Reference to 0.5 mW has been changed to 10 mW.- Section 3.17 LED DRIVERS; Paragraph 3, reference to 100 mS have been changed to 50 mS.- New paragraph; XMT_LED and RCV_LED outputs can drive LEDs... has been added.
Page 13, Section 3.18.1 Signal Description second paragraph; copy has change from ...PLED[1:0] output drivers are high impedance for an interval called the poweron reset time. During the poweron reset interval... to ...PLED[1:0]output drivers are high impedance for an interval towards the end of the poweron reset time. During this interval,
Page 14, Section 3.18.5 Frame Structure, copy change, first paragraph; copy has been change from...The last 16/80 bitsare from one/all of the five data registers... to ...The last 16(80) bits are to or from one(all) of the five data registers.- Second paragraph, copy has been change from ...accessed data register bits will be read or write. The next 3 bits are upper device ... to ... accessed data register bits will be read from or written to. The next 3 bits are upper device...- Second paragraph, copy has been change from ... The next 5 bits are register address select bits which select one of the five data registers for access ... to ... The next 5 bits are register address select bits which select one or all of the five data registers for access....- Second paragraph, copy has been change from ... cycle (or 80 bits if multiple register access is enabled and REGAD=11111) come from the data register ... to ... cycle (or 80 bits if multiple register access is enabled and REGAD=11111) are to or from the data register ...- Table 2. MI Register Bit Type Definition, R/WS C Definition; Clears Itself After Operation Completed, has been moved from Write Cycle to Read Cycle.
Page 15, Figure 5. MI Serial Port Frame Timing Diagram- References to ST, OP, PHYAD, REGAD, TA, DATA have been changed to ST[1:0], OP[1:0], PHYAD[4:0], REGAD[4:0], TA[1:0], DATA[15:0]
Page 27, Figure 8. External MII -AUI Schematics Using 8502 with EEPROM and LED's- References to EE/DO and EE_CLK have been changed to EE_DO/RCV_LED and EE_CLK/XMT_LED.- 1K Resisters and LEDs have been added to EE_DO/RCV_LED and EE_CLK/XMT_LED.
Page 36, DC Electrical Characteristics- IIL Conditions MDA[1:0] has been changed to VIN = GND MDA[1:0].- IIL Conditions OSCIN LINKI has beeen changed to VIN = GND OSCIN LINKI.- VOH Limit (Min) has been changed from 4 to VCC - 1.0.- VOH Conditions, XMT_LED, RCV_LED have been added.- New VOH Row, Limit (MIN) = VCC -1.0, Limit (UNIT) = Volt, Conditions IOH = 10µA XMT_LED, RCV_LED has been added.- ICC Transmitting Limit (Typ) is now 85.- ICC Transmitting Limit (Max) has been changed from 85 to 110.- ICC Powerdown Mode Limit (Typ) is now 1.3.- ICC Powerdown Mode Limit (Max) is now 3.06.
Page 38, AUI Characteristics Receive- ROCV Limit (TYP) has changed from VCC/2 ±0.5 to 3.0 ± 0.5.- RCMR Limit (TYP) has changed from VCC/2 ± 1.0 to ROVC ± 0.5
Page 39, Figure 13. 20 MHz Clock Timing- TX_CLK Timing has been changed.20 MHz Clock Timing Characteristics- t4 Limit (Max) has been changed from 10 to 20.
Revision History
8502
4-54
MD400157/D
54
Page 45, Figure 18. Collision Test Timing- Timing reference to t69 has been changed to t61.
Page 46, LED Driver Timing Characteristics- t66 Parameter, XMT_LED RCV_LED has been added.- t67 Parameter, XMT_LED RCV_LED has been added.Figure 19. LED Driver Timing- XMT_LED RCV_LED, Timing has been added to illustration.
Page 47, Figure 20. MI Serial Port Timing- MDIO(READ) and MDIO(WRITE), timing labels have changed.- MDIO(WRITE) DATA 0 rising edge, is now rising falling.- t74 reference now extends to MDC timing.
Page 55, 44 Pin PLCC Dimension Diagram has been added.Page 56, 28 Pin PLCC Dimension Diagram has been added.
7/14/97
Document Revision Changed to MD400157/C
Page 5, Pin 4, Pin Name:- Corrected error, (MDA) changed to (MDA0).
Page 22, Bit 16.5, 16.4, Definition- Corrected error, reference to PLED1 has been changed to PLED0.
7/29/97
Document Revision Changed to MD400157/D
Global change: All references to VCC = 5 ± 10%, has been changed to VCC = 5 ± 5%.
Global change: All references to 8501 have been deleted or changed to 8502.
Page 36, DC Electrical Characteristics, SYM VOH Conditions: Reference to IOH = 5µA has been changed to IOH 4µA.
Revision History
8502
4-55
MD400157/D
55
Surface Mount Packages
44 Pin Plastic Leaded Chip Carrier
Notes1. All dimensions are in inches and (millimeters).2. Dimensions do not include mold flash. Maximum allowable flash is .008 (.20).3. Formed leads shall be planar with respect to one another within 0.004 inches.
PIN NO. 1
PIN NO. 1 IDENTIFIER.048 (1.22) x 45°.042 (1.07) x 45°
.656 (16.66)
.650 (16.51)
.695 (17.65)
.685 (17.40)
.656 (16.66)
.650 (16.51)
.695 (17.65)
.685 (17.40)
.056 (1.42)
.042 (1.07)
.050 (1.27)BSC
.500 (12.70)REF.
NQ
80220N
Q8502