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© 2017 Microsemi Corporation. Company Proprietary 1 Power Matters. TM Enhanced Prediction of Interconnect delays for FPGA Synthesis using MATLAB Geetesh More (Sr. Software Engineer) Kristofer Vorwerk (Principal Software Engineer) Arun Kundu (Director, Software Engineering)

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Page 1: Enhanced Prediction of Interconnect Delays for FPGA

© 2017 Microsemi Corporation. Company Proprietary 1

Power Matters.TM

Enhanced Prediction of Interconnect delays for FPGA Synthesis using MATLAB

Geetesh More (Sr. Software Engineer) Kristofer Vorwerk (Principal Software Engineer) Arun Kundu (Director, Software Engineering)

Page 2: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 2© 2017 Microsemi Corporation. Company Proprietary

Problem Statement

Approach used to solve the problem

Tools used

Statistical data gathering

Results achieved

Key Takeaways

Outline

Page 3: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 3© 2017 Microsemi Corporation. Company Proprietary

Interconnect delay modeling is used early in the circuit design flow to estimate post-routed silicon delays.

The performance of a circuit is typically dependent on parameters like wire resistance and capacitance, but approximation techniques are required to estimate timing prior to circuit layout, as these parameters are unavailable.

Introduction (1 of 3)

Page 4: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 4© 2017 Microsemi Corporation. Company Proprietary

Improving the accuracy of circuit delay modeling in early phases of the design process is key to producing faster circuit implementations.

Net delay estimation strongly impacts the final result – an overly-optimistic interconnect delay model can cause bad floor planning and congestion during routing.

An overly-pessimistic interconnect delay model can lead to chip area wastage and un-placeable design.

Introduction (2 of 3)

Page 5: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 5© 2017 Microsemi Corporation. Company Proprietary

In our work, we show that the fan-out of the nets in a circuit can be employed to guide an experimentally-derived numerical model for estimating pre-layout circuit performance.

Prior approaches to pre-layout circuit estimation have employed simplistic functions of fan-out.

Our approach gathers data from thousands of statistical runs of a commercial FPGA layout tool flow, then employs MATLAB to analyze the data and derive a set of high-quality, piece-wise functions which estimate pre-layout timing with strong correlation.

Introduction (3 of 3)

Page 6: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 6© 2017 Microsemi Corporation. Company Proprietary

Due to noise in statistical data, residual plot were used to figure out the error in data.

Once the data is stable, smoothing is done using MATLAB.

Final fit is obtained using curve fitting tool box.

Approach

Page 7: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 7© 2017 Microsemi Corporation. Company Proprietary

MATLAB

Curve Fitting Tool Box

Microsemi Libero® Place and Route Tool

Tools Used

Page 8: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 8© 2017 Microsemi Corporation. Company Proprietary

Sample Output of the Statistical data obtained:

1st row here implies that a net driving 0 Lut pin, 0 FF:D pin, 0 FF:Ctrl pin, 0 Sram pin, 2 Uram pin and 1 Math pin is having the delay of 445ps.

Categories:

• DataType = LUT + FF:D

• Control Pin Type = FF:Ctrl

• IP Type = Sram+Uram+Math

• IP Type1 = SRAM

• IP Type2 = URAM

• IP Type3 = MATH

Statistical Data Gathering

Page 9: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 9© 2017 Microsemi Corporation. Company Proprietary

The circuit netlist is represented as a graph G = (V,E), where V is a set of a circuit elements in a design and E is a set of a connections(nets) among them.

Each net e ε E is a hyper-edge of a graph and is represented as a subset of a circuit elements, which are connected each other. Hence, |e|, the cardinality of net e, denotes the number of pins on the net.

Figure below shows the hyper-edge with a Driver and 4 sinks. Here the Fan-out of the net is 4.

What are Fan-outs?

Page 10: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 10© 2017 Microsemi Corporation. Company Proprietary

Sample Net from a placed circuit:

Net with a delay of 279ps is driving the input of 4 Combinatorial element(LUT).

• Tabular representation of the statistical data for this net:

LUT FF_D FF_Ctrl SRAM URAM MATH Delay

4 0 0 0 0 0 279

Page 11: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 11© 2017 Microsemi Corporation. Company Proprietary

Piece Wise model for our Interconnect Delays:

• For lower fan-out, the model is two-term Exponential.

• For intermediate fan-out, the model is linear.

• For high fan-out, the model is linear with low slope.

The resultant model produced a strong correlation between pre-layout & post-layout timing..

Results (1 of 7)

Page 12: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 12© 2017 Microsemi Corporation. Company Proprietary

Circuit delay prediction model for Type I (LUT+FF_D) Data Points:

Results (2 of 7)

Page 13: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 13© 2017 Microsemi Corporation. Company Proprietary

Circuit delay prediction model for Type II (FF Ctrl Pins) Data Points:

Results (3 of 7)

Page 14: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 14© 2017 Microsemi Corporation. Company Proprietary

Circuit delay prediction model for Type III (SRAM+URAM+MATH IP blocks) Data Points:

Results (4 of 7)

Page 15: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 15© 2017 Microsemi Corporation. Company Proprietary

Circuit delay prediction model for Type IV (SRAM IP Block) Data Points:

Results (5 of 7)

Page 16: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 16© 2017 Microsemi Corporation. Company Proprietary

Circuit delay prediction model for Type V (URAM IP Block) Data Points:

Results (6 of 7)

Page 17: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 17© 2017 Microsemi Corporation. Company Proprietary

Circuit delay prediction model for Type VI (MATH IP Block) Data Points:

Results (7 of 7)

Page 18: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 18© 2017 Microsemi Corporation. Company Proprietary

Using the curve fitting toolbox of MATLAB, we obtain a strong correlation between pre-layout & post-layout timing.

Conclusions

Page 19: Enhanced Prediction of Interconnect Delays for FPGA

Power Matters.TM 19© 2017 Microsemi Corporation. Company Proprietary

Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for

aerospace & defense, communications, data center and industrial markets. Products include high-performance and

radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;

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devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and

scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design

capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees

globally. Learn more at www.microsemi.com

©2017 Microsemi Corporation. All rights reserved.

Microsemi and the Microsemi logo are registered

trademarks of Microsemi Corporation. All other

trademarks and service marks are the property of

their respective owners.

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for

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sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical

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