energy efficient a/d converter design - matsuzawa … amp cmp dac-+ - + op amp 1st stage 2nd stage...

2011.06.18 A. Matsuzawa，Titech

1

Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

Energy efficient A/D converter design

Akira Matsuzawa

Tokyo Institute of Technology


2Outline

• Overview of ADCs

• OpAmp based ADC design

• Comparator based ADC design : SAR ADCs

• Flash and sub-ranging ADCs

• Summary


3Performance and architectures of ADCs

4 6 8 10 12 14 16

10M

1M

100k

10k

100M

1G

10G

184 6 8 10 12 14 16

10M

1M

100k

10k

100M

1G

10G

18

Con

vers

ion

freq

uenc

y (H

z) Flash

Pipeline

Delta-sigmaSAR

Sub-ranging

Resolution (bit)

ADC has a suitable performance domain.SAR ADC expands the performance area

OpAmp based

Comparator based


4Strategy of energy efficient ADC design

Reducing static powerResistor DAC Capacitor DACOpAmp based Dynamic comparator based

2DDd CVE

Reducing capacitance

Flash Sub-range SAR# of CMP

TR sizeG

T CV 1

Large TR Small TR with compensation

Noise

CVn

1

Use complementally ckt.

Clock Use self clocking

Reducing voltageEffective to digital gates

Use forward or adaptive body biasing


5SNR vs. signal bandwidth

50

60

70

80

90

0.1 1 101 102

135 dB/Hz

143 dB/Hz

150 dB/Hz

BCDEFGHIJK

[8] VCO[9] VCO[10]CT[11]DT[12]CT[13]CT/DT[14]DT[15]CT[16]CT[17]DT

BCDEFGHIJK

[8] VCO[9] VCO[10]CT[11]DT[12]CT[13]CT/DT[14]DT[15]CT[16]CT[17]DT

fb (MHz)

SN

R (d

B)

bfdBSNRdBSNR log10)()( 0

N

s

PPdBSNR log10)(

bNN fnsityspectrumdePP )('

bN

s fPPdBSNR log10'

log10)(

SNR0

bfdBSNRdBSNR log10)()( 0

SNR of ADCs is inversely proportional to signal bandwidth, fb. Higher bandwidth results in lower SNR and effective resolution.


6Fundamental power of sampling circuit

Signal

Switch Capacitor

Track Hold

NFSqn

qnVV

P 2

22

21212

NFS

qnVV2

TCVn k21

21 2

Sampling circuit

Electrical energy=Thermal energy

CTVn

k2

Quantization voltage

Quantization noise power

qnn PV 2

2

22k12FS

N

VTC

C C

NsFSsd TfCVfP 22 2k242

Noise balance

Capacitance

Pd of sampling circuit

Nss TfP 22k24Fundamental power of sampling is often used.

However this neglects power for comparison.


7Energy consumption of ADC

Timmy Sundstrom, PhD thesis, Linkoping 2011.

Nss TfP 22k24

Ns

s

s TEfP 22k24

Energy of ADC is reaching 100x of the fundamental sampling energy,and 10x of the fundamental ADC energy consumption.

Consumed energy of ADC is mainly determined by the resolution.

192 102 NsE

Es

192 102 NADC NE

EADC

Conventional fundamental sampling energy

Fundamental ADC conversion energyinvolving energy consumption of comparator


8

OpAmp based ADC design


9Mega-technology trend of ADCs

2C

4C

8C

16C

16CC

Major conversion scheme is now changing from pipeline to SAR.

Pipeline ADC

SAR ADC

CMPDAC

-

-+

+

Op amp

CMPDAC

-

-+

+

Op amp

1st stage 2nd stage

Sample Amplify

Cf

Cs

Cf

Cs

1st stage 2nd stage

OpAmp based design

Comparator based design

Consumes static power

No static power


10Amplifier for pipeline ADC

Vsig

VDAC

Cf

Vout

Cs

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1

1stage

OpAmp

Vref

Comp

DataVsig

Vou

t

221 DAC

sigDACf

s

f

ssigout

VVVCC

CCVV

Conventionally Cs=Cf=C0

0,refDAC VV

Unit conversion circuit

I/O transfer characteristics

An OpAmp realizes an accurate voltage amplification.


11Low voltage OpAmp: Headroom and Pd

n

VkTVNf

VIVP

II

thn

effcDDtotDDda

tot

25

25

2_

2

nV

kTVNfVNfCI

NfCVIg

NfCgGBW

thn

effceffc

ceff

m

cm

22

2

424

2_

02

02

2

0

2

VDDVbp

Out

Vbn

In Vs

Veff

Veff

Two stage OpAmp

gm2

gm1

I1

I2

I2I1

n=4

n

VkTVNf

VPPthn

effcDDdampdpipe 2102 2

_

effDDpps VVV 22_ TGSeff VVV

VVeff 15.0

Total Pd of ADC

A two stage cascade OpAmp can realize low voltage operation.However, the output voltage swing become lower at low voltage operation.

2_

0 2thnV

kTnC

1212 44 IIgg mm


12Required performances

222

22

31

231

N

effDDNsig

q

VVVV

12222_ ENOB

qthn VV

2_

0 2thnV

kTnC

Quantization voltage

Thermal noise

Unit capacitance

31:

#:2:

factorfeedbackβ

sourcesnoiseofntcoefficiennoiseγ

cNfGBW

106)( NG dB70dB: 10b94dB: 14b

N: Resolutionfc: Conversion freq.

Open loop gain

ENOB: Effective # of bit

GBW

Required gain and bandwidth of OpAmp and capacitance are determined bythe resolution and conversion frequency.

idealfromnDegradatioENOB :


13C0 and Pd at low voltage operation

12bit, 100MHz ADC

Capacitance should be larger at low voltage operation to keep sufficient SNR. This results in rapid increase of power dissipation.

effDDpps VVV 22_ kT

VVCkTVC

SNR effDDpps2

02_0 22

20 2 effDD VVSNRkTC

eff

Dmc VC

ICgGBWf

00

2

20 2 effDD

DDeffcDDeffcDDDd VV

VSNRVTfVVfCVIP

Low voltage doesn’t make sense for pipeline ADC.

0.4 0.6 0.8 1 1.21 10 12

1 10 11

1 10 10

1 10 9

Vdd

C0

(F)

20 21

effDD VVC

P d(W

)

0.4 0.6 0.8 1 1.20.01

0.1

1

10

Vdd

22 effDD

DDd VV

VP


14FoM: Figure of Merit of ADC

22

2

2122230

effDD

DDeffENOB

N

cd VVVVkTnNfP

Nc

ENOBd

ENOBc

d

fP

fPJFoM

22

2)(

idealfromnDegradatioENOB : 22 212

2230effDD

DDeffENOB

ENOB

VVVVkTnFoM

0.4 0.6 0.8 1 1.21 10 13

1 10 12

1 10 11

FoM

(J/c

onv.

ste

ps)

VDD (V)

FoM stands for consumed energy normalized by the effective steps.

12bit, 100MHz ADC

Low voltage operation for OpAmp based ADC increases FoM.


15

Comparator based ADC design : SAR ADC


16Basic idea for low energy analog design

sDDd

LDD

stogle

IVPCVIf

CML, OpAmp

VDD

Vi+ Vi-

Vo-CL

RL

CL

RLVo+

Is

RO

CL

Vi Vo

VDD

CMOS

2DDL

dtogle VC

Pf

2

21

DDLdd VfCfEP

Conventional analog circuits consume larger energy. Dynamic circuits doesn’t consume larger energy.

2

21

DDLd VCE

CMOS: Consumed energy is independent of delay time.

Lortogle CRTf 11

Lotogle CRf 1


17SAR ADC

Vin

Vref

Comparator Logic

Switches

Capacitors

S11 S12 S13 S14 S15

S2

S0

2C

4C

8C

16C

16C

VrefVin

NA

C

Cn1

nC

10 n

refsigx VnVV Vx

NA

Sample 2

21

refCVE

SAR can be designed to consume no static power.

Generating subtracted signal

No resistorsNo static current !Potentially full swing

inCVQ

SAR can realize larger signal swing compared with pipeline ADC.

Not OpAmp based,but comparator based


18Performance overview of SAR ADCs

FoM has lowered rapidly due to the progress of SAR ADC.

1/200 during three years.

FoM trend of 10bit ADC

0.1

1

10

100

1000

2005 2006 2007 2008 2009 2010

Recent FoM rangeFoM

(fJ/c

onv.

ste

ps)

stepsconvfJseveral ./10


19Issue of comparator for SAR ADCs

5b Charge Redistribution (CR) SAR ADC

INp SAR0/1Vin

CLK

Vref

Vref

INn

113 3

Noise Distribution

Comparator Threshold

b0 b4b3b2b1

1 11 0 1

INp

INn

OK!

27

b0 b4b3b2b1

1 01 1 0

INp

INn

ERROR!

28

A comparator has noise and this results in conversion error.

V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. van der Plas, and J. Craninckx, “An 820uW 9b 40MS/s Noise Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” IEEE ISSCC 2008, Dig. of Tech. Papers, pp.238-239, Feb. 2008.


20Dynamic comparator

CLK

CLK CLK

CLK

INP

SPSN

INNFN FP

2iV

2iVID ID

CL

CL

VDD

A dynamic comparator is widely used to reduce static power.

The difference in input voltages causes a difference in discharging speed.

D. Schinkel, E. Mensink, E. Klumperink, Ed Van Tuijl, B. Nauta,

“A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup-Hold Time,” ISSCC Dig. of Tech. Papers, pp.314-315, Feb., 2007.


21Deriving noise equation

12

2

eff

dd

ds

Lt V

VIkTC

d

2

02

22

22 1

d

d

t

nD

vnD

Lt dti

IIC

22

222 k,k

D

L

L

D

nt

Ln I

TC

CI

vδ

CTv

d

1) Sampling noise of Switch

2) Transistor noise

dt

nL

n dtiC

v0

1

Noise voltage of output by current noisevICtD

L

td

ni

VDD

VDD/2

td

td

VL

time

Vi VL

ni ID CL

S

VDDimVg

Equivalent circuit

TR noiseVoltage and timing

Transistornoise

Samplingnoise

1

k422

222

eff

dd

ddL

eff

d

tdeffin V

VαγVCα

TVtδ

αV

Vδ

A. Matsuzawa," IEEE 8th International Conference on ASIC(ASICON), pp. 218-221, Oct. 2009.


22Match with noise simulation

DDL

effin VC

kTVV

2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0 10 20 30 40

CL [fF]

δV

in（σ

） [

mV

]

Estimation（α=2）Estimation（α=1）Simulation

0

10

20

30

40

50

60

70

80

90

100

-1.0 -0.6 -0.2 0.2 0.6 1.0

ΔVin [mV]

P (out=

hig

h) [%

]

The derived equation has a good match with simulation.

Noise in comparator

1

k422

22

eff

dd

ddL

effin V

VαγVCα

TVVδ


23Required capacitance and consumed Energy

6 7 8 9 10 11 12 13 140.1

1

10

100

1 103

1 104

1 105

CL(

fF),

Ec(

fJ)

Resolution (bit)

CL

Ec

VDD=1V, Veff=0.2V

Node capacitances should be increased to realize higher ADC resolution.This results in increase of consumed energy of the dynamic comparator.

2fF & 4fJ @8bit40fF & 80fJ @10bit0.6pF & 1pJ @12bit10pF & 20pJ @14bit

Flash ADC: Ec determines the minimum FoMSAR ADC: Ec cannot be neglected for higher resolution ADC

Ec: conversion energy


24Noise improvement of dynamic comp.

CLK

VINP_a VINP_b VINN_b VINN_a

Gate weighted interpolation

Offset CALVdd

Voutp

VoutnWPa WNaWNbWPb

0.0

1.0

2.0

3.0

4.0

0.4 0.5 0.6 0.7 0.8 0.9Vcm [V]

V n(

) [m

V]

Proposed

Conventional

M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," A-SSCC, Nov. 2008.

Yusuke Asada, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, and Akira Matsuzawa, "A 6bit, 7mW, 250fJ, 700MS/s Subranging ADC," A-SSCC, 5-3, pp. 141-144, Taiwan, Taipei, Nov. 2009. 90nm CMOS

Dynamic comparatorNoise of comparator

Noise of comparator can be reduced by complementary ckt. and an optimizationof the node capacitance.

CMOS input


25Pd estimation of SAR ADC

Vin

Vref

Comparator Logic

Switches

Capacitors

222 DDLcdc VCfNp 22 DDscds VCfp

22 DDgcdc VCNfp

Cs: Total sampling capacitanceCL: Load capacitance of comparatorCg: Effective capacitance of gates and switches

Cg: const

2

22

DD

N

s VC 3

22

DD

N

L VC

1) S/H&CDAC 2) Comparator

2) Logic gates and switch drivers

Divide SAR ADC into three different circuits.

Akira Matsuzawa, ISSCC Forum, San Francisco, CA, Feb. 2011.


26Equations to estimate the ADC performance

222 DDLcdc VCfNp

22_ 14

DD

eff

eff

DD

Lthn V

VVV

CkTV

22

231

N

DDq

VV

222_ 12 q

ENOBthn VV

2

2_

14

DD

eff

eff

DD

thnL V

VVV

VkTC

N

c

ENOBdgdcds

fPPP

FoM2

2

2_

4

thns V

kTC

22 DDscds VCfp

22 DDgcdg VCNfp

Quantizationvoltage

Permitted thermalnoise

ThermalNoise of COMP.

Sampling capacitor

LoadCapacitorOf COMP.

Pd of S/H

Pd of COMP.

Pd of Gate


27C, Pd, and FoM vs. VDD

0.4 0.6 0.8 1 1.21 10 13

1 10 12

1 10 11

Vdd

0.4 0.6 0.8 1 1.21 10 5

1 10 4

1 10 3

0.01

Vdd

Cs,

CL

(F)

VDD (V) VDD (V)

P d(W

)

Cs

CL S/H

Comp

Logic

Cg=0.1pF

Cg=0.3pF

2

1

DDs V

C

3

1

DDL V

C

DDdc VP 1

2DDdg VP

.constPds

Sampling capacitance Cs and load capacitance CL increase with reducing VDD,since the quantization voltage decreases with reducing VDD.

Pd of S/H is constant for VDD,however Pd of comparator increases with reducing VDD.Pd of logic gate decreases rapidly with reducing VDD.


28FoM vs. VDD

0.4 0.6 0.8 1 1.21 10 15

1 10 14

VddVDD (V)

FoM

(J)

Cg=0.1pF

Cg=0.3pF

VVKT

bitENOBMHzF

bitN

eff

c

15.03002

5.010012

FoM can be lowered by reducing VDD, if Pd of logic gate is dominant.

Thus the voltage lowering is effective to reduce Pd for low resolution ADC,However, it is still difficult to reduce Pd by reducing VDD for high resolution ADC,even if SAR ADC architecture is used.

Gate dominant

COMP dominant


29Example: An ultra-low power CDC

We have developed an ultra-low power Capacitance to Digital Converter.

1. 10b SAR like architecture2. Self-clocking3. Single to differential

① ②③

3nA @ 30 times/secTuan Minh Vo,Yasuhide Kuramochi, Masaya

Miyahara,Takashi Kurashina, and Akira Matsuzawa“A 10-bit, 290 fJ/conv. Steps, 0.13mm22, Zero-Static

Power, Self-Timed Capacitance to Digital Converter.”SSDM 2009, OCT.


30Self clocking technique

b

Comparison is ended if the output voltages are not same.

Output voltage of dynamic comparator

Self-clocking scheme

Self-clocking scheme is very useful

1) Reducing power consumption (Clock circuits, routing clock, )2) Just an enable command signal is required. No need of clock.

Suitable for micro controller.


31

Flash and sub-ranging ADCs


32Flash ADC

Comparator Array

1

1

0

0

• Expecting highest speed• Comparator determines the ADC performance

6b: 63 NFS

qVV2

Vq=16mV, Mismatch <3mV

Flash ADC

Offset mismatch

Offset mismatch mainly determines the effective resolution.Thermal noise can be neglected because of low resolution.

6b: 63 VFS=1.0V

6N


33FoM of Flash ADC

ENOBcENOBN

s

Nsc

ENOBs

d Ef

fEf

PFoM

22

22

Ec: Energy/Comparator

FoM of flash ADC is determined by energy consumption of unit comparator and the degradation of effective bit.

Reduction of consumed energy and increase of ENOB are very important.

2DDc CVE

2

q

n

2

q

off2

)()(121log21

VV

VVENOB

Offset mismatch Thermal noise (can be neglected)


34Performance of flash ADC

2

q

off2

)(121log21

VVENOB

N

ENOBd

fP

22FoM

c

FoM is degraded by the offset mismatch voltage of the comparator.Offset mismatch voltage should be reduced at low voltage operation.

ENO

B [

bit]

Voff(): Offset mismatch

Vq : 1LSB voltage


35Tradeoff: mismatch and energy consumption

Transistor size (um2)

0

5

10

15

20

25

0 0.2 0.4 0.6 0.8 1

0

50

100

150

200

250

300

350

オフセット

消費電力

Offs

et m

ism

atch

(mV)

E c(fJ

)

LWVo

1)(ffset

LWCE cc

Serious tradeoff between mismatch of transistor and gate area. Larger transistor is required to reduce mismatch voltageand results in increase of gate area and consumed energy.

2

1

offsetc VE

Ec=50fJ3mV

Mismatch compensation

Example

6bit ADC: Voff<3mVEC<50fJ0.1um2Voff=20mVNeeds mismatch compensation20mV 3mV


36FoM vs. Area

0.01

0.1

1

10

0.01 0.1 1 10

Area (mm2)

FoM

(pJ/

conv

.ste

p)

Occupied area should be reduced to lower the FoM.We must pay much attention to the occupied area.

AreaCEc

5bit and 6bit ADCs


37Digital calibration methods for mismatchResistor ladder type Capacitor array type

Binary weighted capacitor array

Y. Asada, K. Yoshihara,T. Urano, M. Miyahara and A. Matsuzawa,

“A 6bit, 7mW, 250fJ, 700MS/s Subranging ADC” A-SSCC, pp. 141-144, Nov. 2009.


38Effect of digital mismatch compensation

Measured resultV o

ffset

Voffset

Voffset

The mismatch voltage can be reduced from 14mV to 1.7mV.

M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," A-SSCC, Nov. 2008.


39Area comparisonPenalty area for digital compensation will be reduced with technology scaling.

Comprator CAP Array

Register 4b

5m

65 m

25 m 10 m 30 m

5m

85 m

Comprator

25 m 30 m 30 m

Register 4bDecorderMUX

4.5m

Comprator

30 m

120 mStrage Capacitor & Charge Pump

90 m

2.9m

41 m

UpDownCounter5b

22 m

Comprator &Cap Array

19 m

90 nm

40 nm

Resistor ladder

Capacitor array

Capacitor array


40Issue of resistor DAC to generate VREF

T/HIN

7

7

7

7

15

Upper bit

Lowerbit

Coarsescale

Previousfine scale

tLATCH tDAC

Coarse conversion

Fine conversion

tCLK

Fine scale

Resistor DAC consumes static power and has a serious tradeoff between Pd and speed.

pronref

refpronref CR

IV

CRR

44max Iτ 1


41Advantage of capacitor DAC to generate VREF

Operating as S/H circuit• No static power consumption ( 360W@1GHz )• Smaller Cu realize faster settling time

(tDAC= 3.4 ronCU < 80ps @ rON = 1k, CU= 15fF)

REFIN

tot

pout VnV

CCV

1

1 CRon2DDd CVE

Capacitor DAC doesn't consume static power and has no trade offbetween Pd and speed.


42Settling time and power

CDAC realizes faster settling time to RDACwith low power consumption.

0

20

40

60

80

100

120

140

160

180

0 50 100 150 200

time [ps]

α=0.5 vout(CDAC)

α=5 vout(CDAC)

α=10 vout(CDAC)

RDAC

0

200

400

600

800

1000

1200

1400

1600

1800

RDAC

CDAC

CDAC

CDAC

Time response Power dissipation


436bit sub-ranging ADC using CDAC

6 bit ADC has been realized in a 90 nm 10M1P CMOS technology with a chip area of 0.13mm2

Y. Asada, K. Yoshihara,T. Urano, M. Miyahara and A. Matsuzawa,

“A 6bit, 7mW, 250fJ, 700MS/s Subranging ADC” A-SSCC, pp. 141-144, Nov. 2009.


44Performance comparison

[1] C-Y. Chen, VLSI Circuits 2008.[2] B-W. Chen, A-SSCC 2008.[3] F. C. Hsieh, A-SSCC 2008.[4] Z. Cao, ISSCC 2008.[6] Y. C. Lien, A-SSCC 2008.

[1] [2] [3] [4] [6] This WorkResolution(bit) 6 6 6 6 6 6fs(GS/s) 0.8 1.2 0.7 1.25 1 0.7SNDR(DC/Nyq.) 35/32 34/33 31/30 34/28 35/33 35/34Pd (mW) 12 75 24 32 30 7Active area(mm 0.13 0.43 0.052 0.09 0.18 0.13VDD(V) 1.2 1.2 1.2 1.2 1.2/1.0 1.2FoM(pJ) 0.44 2.17 1.31 1.22 0.8 0.25CMOS Tech.(nm 65 130 130 130 90 90Architecture Flash Flash Pipeline 2b-SAR Subrange Subrange

Attain lowest FoM at that time


45Voltage lowering: FoM vs. VDD

VDD (V)

Ec (fJ)

FoM (fJ)

mVVoff 6)( =

ENOB

)(bitENOB cfSVIV

VCE

TcDD

2DDcc

exp

Ec:Energy consumption for each comparator and followed logic circuits.

FoM can be reduced drastically by reducing supply voltage VDD.

ENOBcE

2FoM

ENOB is degraded by the reduction of VDD, however little affects the FoM.

Energy reduction by reducing VDD is dominant.

2

2

)(121log

21

q

off

VV

ENOB


46FoM delay (FD) product

TDD

DDd VV

VkT

Delay time

The FD product suggests the balance between the number of interleaving and decrease of energy consumption.

VT = 0.4 V DelayFoMFD

Delay is increased and the operating speed is lowered by reducing VDD

We should investigate the optimum VDD by FD product.

Optimum range


47Forward body biasingForward body biasing can decrease the delay time (1/2)and can be used easily at 0.5 V operation.

VDD

IN OUT

0

2

4

6

8

10

12

0.4 0.6 0.8 1 1.2 1.4Supply voltage (V)

BB

FBB

BBW/O FBB

W/ FBB (0.5V)VTN = 100mV

VTP = 60mV

Increased leakage current in the proposed ADC is 0.32 mAby forward body biasing.

1/2


48ADC Structure

Block diagram of ADC Chip microphotograph

5bit 0.5V 600MSps Flash ADC is designed and fabricated in 90nm CMOS.

S/H circuits use gate boosted switches.

M. Miyahara , J. Lin, K. Yoshihara, and A. Matsuzawa,“A 0.5 V, 1.2mW, 160fJ, 600 MS/s 5 bit Flash ADC”A-SSCC, pp. 177-180, Nov. 2010.


49Performance Summary

Reference # [7] [8] [9] [10] This workResolution (bit) 5 5 5 5 5fs (GS/s) 0.5 1.75 1.75 0.06 0.6SNDR (dB) 26 30 30 26 27Pd (mW) 5.9 2.2 7.6 1.3 1.2Active area (mm2) 0.87 0.017 0.03 - 0.083Vdd (V) 1.2 1 1 0.6 0.5FoM(fJ) 750 50 150 1060 160CMOS Tech. (nm) 65 90 90 90 90Architecture SAR Fold+Flash Flash Flash Flash

[7] B. P. Ginsburg, J. Solid-State Circuits 2007.[8] B. Verbruggen, ISSCC 2008.[9] B. Verbruggen, VLSI Circuits 2008.[10] J. E. Proesel, CICC 2008.

FoMFmax = 160fJ @ 600MSpsFoMBest = 110 fJ @ 360MSps

A high speed and low FoM 0.5V flash ADC has been realized.


50Summary of energy efficient ADC design

Reducing static powerResistor DAC Capacitor DACOpAmp based Comparator based

2DDd CVE

Reducing capacitance

Flash Sub-range SAR# of CMP

TR sizeG

T CV 1

Large TR Small TR with compensation

Noise

CVn

1

Use complementally ckt.

Clock Use self clocking

Reducing voltageEffective to digital gates and low resolution ADC

Use forward or adaptive body biasing

energy efficient a/d converter design - matsuzawa … amp cmp dac-+ - + op amp 1st stage 2nd stage...

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