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Denis Molaro – Sincrotrone Trieste Elettra digital control PS Bipolar digital control 30 A – 20 V PS Denis Molaro POCPA3 – DESY, May 21-23, 2012

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POCPA3 – DESY, May 21-23, 2012. Elettra digital control PS. Bipolar digital control 30 A – 20 V PS Denis Molaro. Content. [email protected] low current PS requirements Why digital? Resolution & Limit cycles DPWM Resolution H-Bridge Toggle Technique ADC Synchronization - PowerPoint PPT Presentation

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Elettra digital control PSBipolar digital control 30 A 20 V PSDenis MolaroPOCPA3 DESY, May 21-23, 2012Denis Molaro Sincrotrone Trieste Today Im going to present the digital control low current PS we develop for Fermi (the XFEL Linac) that has been working for the last three years1ContentPOCPA3 DESY, 21-23/05/[email protected] low current PS requirementsWhy digital?Resolution & Limit cyclesDPWM ResolutionH-Bridge Toggle Technique ADC [email protected] 20 A and 5 A PSINFN Frascati, SPARC PSConclusion & ConsiderationDenis Molaro Sincrotrone Trieste Im gonna talk about these PS requirements and why we decide to make them digital control. Than I gonna talk about the major issue in the divelopment of a digital control systemThan I gonna present the 20A and 5 A PS and the last evolution we develop for the SPARC [email protected] PS requirementsPOCPA3 DESY, 21-23/05/2012Four-quadrant: 5 A, 10 V and 20 A, 20 V Max Ripple: 30 ppm/FSLong term stability (8h): 50 ppm/FSStandard Ethernet interfaceOutput current resolution: 16 bitCurrent set point update rate: 50 Hz (for feedback)Load range: 0.5 2 and 0.5 400 mHNumber of channels: more than 300Denis Molaro Sincrotrone Trieste Two range are required five A and twenty A, the maximum ripple allowed is therty part per million, long therm stability is better than one hundred ppm full scale.Our control group require a standard Ethernet interface for the remote control.Resolution is the usual 16bit.The correctors are used for stabilize the beam path along the referance traiectory, to do so the PS have to be able to accept a set point reference every 20 milliseconds (50 Hz)The two PS types are used to supply wide range of magnets, and differnt PID parameters are needed. 3Why digital?Easy of PID modification (wide load range for the same current range)Step response optimization for all PS-magnet combination.

POCPA3 DESY, 21-23/05/2012Galvanic isolation between current sensor and control electronics

Denis Molaro Sincrotrone Trieste ...so why did we decide to make them digital? Because of the easy way to change PID parameters since we have to menage a lot of different magnets with the same current range so with the same PS type. One other issue is that these PS require fast setting time (or step respons) becouse they are used in the beam position feedback. PID have to be well tune to guarantee that in 20 ms the PS get the referance value with the precision required.Digital control simplifie the current sensing circuit becaus a galvanic isoletion is more simple with digital signals. In our topology (full bridge) due to EMI consideration we decide to place the Bulk to gound with the digital card, so the current sensing circuit must be galvanically isolated.4Resolution & Limit CyclesPOCPA3 DESY, 21-23/05/2012Digital controls are affected by limit cycles

Denis Molaro Sincrotrone Trieste One important issue of digital control system is limit cycles in stady state condition due to the discretisation of the input and output variables. Limit cycles cause output to oscillate around the refance value with a frequency that dipends on the compensation loop frequency.5Resolution & Limit CyclesPOCPA3 DESY, 21-23/05/2012Three conditions are required to avoid Limit Cycles[1]Output min step < reading min step (i.e. output resolution > reading resolution)0 < Integral Gain (Ki) < 1Loop stability (with ADC gain)

[1] A.V. Peterchev, S.R. Sanders: Quantization resolution and limit cycling in digitally controlled PWM converters IEEE Transaction on Power Electronics, Volume 18, Issue 1, Part 2, Jan. 2003, pp. 301-308PID parametersHardware

Denis Molaro Sincrotrone Trieste Three condition have to be sadisfied to avoid stady state limit cycles: 1 2 3The last two are depending on the pid parameters (this mean firmware parameters) and the first one is depending on hardware resolution and says that limit cycles may result from the presence of signal amplitude quantization like the ADC and DPWM modules in the feed back loop. So it put the condition that quantization output variable (in our case the current) must be lower than quantization reading.6Resolution & Limit CyclesPOCPA3 DESY, 21-23/05/2012

When output min step > reading min step

Limit cyclesDenis Molaro Sincrotrone Trieste Lets see what happen when the system output quantization step is higher than reading step. This graph plot a possible reproduction of the output voltage (with current the principle is the same) where as DAC levels correspond to the output levels, and ADC levels to the reading levels.If the reference voltage is this bit >< that should correspond to the 0 bit error in the difference with the voltage output, we can see that this quantization level is not achievable by the output driver (DAC level) because not any of the DAC level is inside to this region, and the output start to oscillate between the closest quantization levels. So this system is affected by limit cycles condition.7Resolution & Limit CyclesPOCPA3 DESY, 21-23/05/2012When output min step < reading min step

Stady state stableDenis Molaro Sincrotrone Trieste When the system output quantization step is lower than reading step, the reference value is achievable so the voltage reference minus the output voltage quantized can be zero and the system is stable.8Resolution & Limit CyclesPOCPA3 DESY, 21-23/05/2012Output min step (H-Bridge):

Reading min step:

Example (5A PS):VDC-Link = 12 V IoutRANGE = 10 AADC-RES = 16 bit

Denis Molaro Sincrotrone Trieste Lets define the minimum step for the full bridge converter: this is the maximum output current range divided by the number of DPWM steps.And the reading minimum step is the the output current range, that is dependents by the transducer circuit ( shunt operational amplifier gain) divided by the ADC resolutiom.So in the example of the we have9Resolution & Limit CyclesLimit cycle condition for VDC-Link= 12 V, IoutRANGE = 10 A and ADC-RES = 16 bit

POCPA3 DESY, 21-23/05/2012

IoutMIN-STEP [A]RLOAD []

Due to wide range of resistive load a 19 bit of DPWM resolution is requiredDenis Molaro Sincrotrone Trieste We can plot a graph that represent the output current min step versus the resistive part of the load, for different DPWM resolution.For the 5 Amps PS we got a limit of reading step that is 153 micro amps which we can not exceed with the output min step.And we can see that lower is the resistive load, higher must be the DPWM resolution.In our case we have to drive a minimum load of 0.5 ohm, so in our case a 19bit resolution is required.10DPWM ResolutionDelay-line DPWM has been used (TMS320F2808)

POCPA3 DESY, 21-23/05/2012

Using 4 PWM cycles of dithering17.8 bit resolution has been achieved

Denis Molaro Sincrotrone Trieste Get 19 bit of resolution was not easy, and we merge different solution to achieve this value.We start by choosing a delay-line type DPWM that it was available in the texas instrument dsp F2808 (actually is a microcontroller but i like to call it dsp This dsp have an integrate high resolution DPWM circuit, capable to have 15.8 bit of resolution at the switching frequency of 100kHz.By doing a dithering over 4 switching periods a 17.8 bit of resolution has been achieved.11H-Bridge Toggle TechniqueA further bit of resolution has been added by a Toggle Technique (Patent Pending) between the two legs of the H-Bridge.

POCPA3 DESY, 21-23/05/2012

For instance with VDC-Link=12, RLOAD=1 and mLSB=1/217.8

Denis Molaro Sincrotrone Trieste To get one more bit of resolution a toggle technique has been invented. To explain how this technique works take a full bridge configuration, where the two half branches are dived by the same modulation index, m that can assume values between zero and one. So the output current, function to the modulation index is >< from this we can extrapolate the minimum output step achievable with the last significant bit of modulation index variation.In the example of the 5 A PS with 17.8bit of resolution the output current minimum step is one hundred five micro amps. 12A further bit of resolution has been added by a Toggle Technique (Patent Pending) between the two legs of the H-Bridge.

POCPA3 DESY, 21-23/05/2012

Keeping m1 constant, varying m2 (or vice versa)VDC-Link=12, RLOAD=1 and mLSB=1/217.8

H-Bridge Toggle TechniqueDenis Molaro Sincrotrone Trieste Pleas consider an H-Bridge where two different modulation index are used. M1 and m2 are two modulation index both with a resolution of 17.8 bit, but while one is kept constant the other one is varying alternately. Using this control toggle technique the minimum step is reduced to the half, so in the example of the 5A PS the minimum step is 52.5 micro AIn practice we have add a further bit of resolution getting almost 19 bit of resolution. 13Example of Toggle Technique with 2 bit of dithering.

POCPA3 DESY, 21-23/05/2012

H-Bridge Toggle TechniqueDenis Molaro Sincrotrone Trieste In this slide I report a reproduction of the two modulation index m1 and m2 that correspond to an ideal not quantized modulation index m.We can see how each modulation index is incremented while the other is kept constant. 14 converter has been used (ADS1252: 24 bit, SPI, SOIC 8 package)Problem: ADC hasn't a start of conversion

POCPA3 DESY, 21-23/05/2012ADC Synchronization ADCDSP DPWMH-BridgeSPISPI

ADCMOD.CLOCKDenis Molaro Sincrotrone Trieste For historical reasons we diced to use a sigma delta ADC that have 24 bit of resolution (but we use only the firs15POCPA3 DESY, 21-23/05/[email protected] 5A and 20A PS

Denis Molaro Sincrotrone Trieste POCPA3 DESY, 21-23/05/2012INFN Frascati - SPARC 30A PS

External 24V 3kW Bulk AC mainsMagnetInterlockMagnet/LoadEthernetDenis Molaro Sincrotrone Trieste POCPA3 DESY, 21-23/05/2012INFN Frascati - SPARC 30A PS

Output Current 30 AOutput Voltage 20 VOutput Current Resolution16 bitOutput Current Ripple30 ppm / FSOutput Current Stability50 ppm / FSDC/DC efficiency (full load)95%Switching frequency104 kHzClose Loop Bandwidth1,5 kHzAccuracy0.05 %Max set point update rate 300 HzDenis Molaro Sincrotrone Trieste POCPA3 DESY, 21-23/05/2012INFN Frascati - SPARC 30A PSLocal Control / MonitorGraphic Color Display, 6 LEDs and EncoderExtra-FeaturesHot-SwapPoint-by-Point Current Waveform LoadingUser-definable interlock thresholds, active levels and timingsRemote UpdatesAuxiliary ADCDC Link VoltageGround Leakage CurrentMOSFETs Temperature ShuntTemperatureHardware protectionInput FusesEarth FuseOver-VoltageInternal InterlocksDC Link Under-VoltageMOSFETs Over-TemperatureShunt Over-TemperatureOver-CurrentOver-VoltageEarth Fault CurrentRegulation FaultExcessive Current RippleExternal Interlocks8 Inputs: "dry" contacts3 Outputs: relay-typeCoolingSelf-Regulated FansOutput Current 30 AOutput Voltage 20 VOutput Current Resolution16 bitOutput Current Ripple30 ppm / FSOutput Current Stability50 ppm / FSDC/DC efficiency (full load)95%Switching frequency104 kHzClose Loop Bandwidth1,5 kHzAccuracy0.05 %Max set point update rate 300 Hz

Denis Molaro Sincrotrone Trieste POCPA3 DESY, 21-23/05/2012Conclusion & ConsiderationDigital control is very useful for standardize different range of PS Simplifies the additions of extra features (communication, waveforms...)Requires digital hardware and software experts for development and modificationsIntroduces electronic components not easy to repair-replace (FPGA)Could we roll back to the old and simple POWER SUPPLY and not waveform generator with OLED display, please?

BUTSODenis Molaro Sincrotrone Trieste POCPA3 DESY, 21-23/05/2012Thats all Folks!Thank YouDenis Molaro Sincrotrone Trieste text

PID

H-Bridge

DPWM

IOUT

+

-

VREF

Opto

ADC

Load

DC-Link

text

IOUT

+

-

VREF

Opto

ADC

H-Bridge

Load

DPWM

DC-Link

1

VDC-Link

m

Q1

Q2

Q3

Q4

VP

VN

1

VDC-Link

m1

m2

Q1

Q2

Q3

Q4

VP

VN

t

t

t

TLOOP

ADC: END OF CONVERSION

PROCESSING

PWM

TSW

t

ADC MODULATOR CLOCK

NClock