electrical measurments for microwave devices

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  • 8/14/2019 Electrical Measurments for Microwave Devices

    1/121 ANMEM0902Microwave Support Documentation

    ELECTRICAL MEASUREMENTS

    ELECTRICAL MEASURMENTS FOR MICROWAVE DEVICES

    Selecting a section will link to its page.

    A. GENERAL PRECAUTIONS 2

    B. HANDLING PRECAUTIONS 2

    C. BIAS CIRCUIT 31.) DC SUPPLY CIRCUIT 32.) RF BIAS CIRCUIT 4

    D. MEASUREMENT SYSTEM DIAGRAMS 51.) POWER MEASUREMENT SYSTEM BLOCK DIAGRAM 5

    Discrete and Partially Matched FETs

    2.) POWER MEASUREMENT SYSTEM BLOCK DIAGRAM 6Internally Matched FETs

    3.) IM3 MEASUREMENT SYSTEM BLOCK DIAGRAM 74.) PHASE DEVIATION MEASUREMENT SYSTEM BLOCK DIAGRAM 85.) PULSE POWER MEASUREMENT SYSTEM BLOCK DIAGRAM 9

    Pulsed Drain Bias 6.) NOISE FIGURE AND ASSOCIATED GAIN MEASUREMENT SYSTEM BLOCK

    DIAGRAM 107.) THERMAL RESISTANCE MEASUREMENT SYSTEM BLOCK DIAGRAM AND

    MEASUREMENT PROCEDURE 11

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    ELECTRICAL MEASUREMENTS

    A. GENERAL PRECAUTIONS

    1) Observe recommended operating conditions and absolute maximum ratings:

    VDS, IDS, VGS, IG, TCH.

    Absolute Maximum Ratings are the limits one should not exceed under any conditions and doesnot mean actual applicable bias condition. Fujitsu recommends the following conditions for longlife and reliable operation.

    TCH = 145C maxVDS = See the individual data sheetsVGS = VGS shall be set for the I DS (0.6 I DSS to 0.55 I DSS )IG = See the individual data sheets

    2) Use a sequencing DC power supply.See the individual data sheets or Figure III-1.

    3) Do not apply RF power until the FET is biased on. Turn-off RF power before removing bias.

    4) Use only properly designed RF circuits and decoupling circuits to prevent bias circuit oscillations.Bias oscillations are one of the most common modes of failure for microwave GaAs FETs.Destruction of the FET often occurs in microseconds. Refer to the individual data sheets orFigure III-3 , for the recommended bias circuit configuration.

    B. HANDLING PRECAUTIONS

    GaAs FETS are sensitive to electrostatic discharge. Fujitsu ships all GaAs FETs in electrostaticprotection packaging. User must pay careful attention to the following precautions when takingFETs out of their packaging.

    1) Personnel handling GaAs FETs should be properly grounded by a wristlet chain or equivalent.

    2) When mounting the FET in a circuit, the circuit gate and drain connections should be shorted toground.

    3) When soldering the FET leads, an iron with a grounded tip is required.

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    ELECTRICAL MEASUREMENTS

    10

    5

    -2

    -4

    -6

    Vin: ON Vin: OFF

    +Vout (V)

    -Vout (V)

    10 msec

    +Vout (V)

    -Vout (V)

    Figure III-2. Switching Response of the Bias Circuit

    2) RF Bias Circuit

    The injection of bias voltages into a GaAs FET RF circuit is typically accomplished via a quarter-wave transformer line as shown in Figure III-3. It is intended to provide a DC connection to the GaAsFET gate and drain, while perturbing the RF performance characteristics as little as possible.

    C2

    C3

    C1

    R3 L1 C1, C2: 1000pF, ChipL1, L2 :

    R1R3R4R2 :C3, C4:C5, C6:

    L2

    R4

    R2R1

    -VGS +VDS

    High impedence /4 line

    Low impedence /4 line

    Figure III-3. Connection of the Bias Supply to the GaAs FET's

    Low impedence /4 line

    High impedence /4 line

    C4

    C6

    C5Rg=R1 +R3 x R4

    R3 + R4

    Large inductor atRF frequency or /4 lineChosen for desiredVGS , IDS andgate impedance50 Chip1000pF feed thruabout 10 F

    }

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    ELECTRICAL

    DIRECTIONALCOUPLER

    DC POWER SUPPLY

    +VDD-VGG

    D.U.T. TUNER

    IGS

    VDSVGS

    ATTEN.

    POWERMETER

    POWER

    SENSOR

    RF POWERSOURCE

    TUNERBIASTEE

    BIASTEE

    Rg *

    * Use Fujitsu's recommended gate resistance (Rg) as indicatedon the data sheet for the device under test . Follow device handlingand bias precautions presented at the beginning of this section.

    POWERMETER

    POWER

    SENSOR

    IDS

    50 term.

    D. MEASUREMENT SYSTEM DIAGRAMS

    1. POWER MEASUREMENT SYSTEM BLOCK DIAGRAM

    Discrete and Partially Matched FETs

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    ELECTRICAL MEASUREMENTS

    DIRECTIONALCOUPLER

    DC POWER SUPPLY+VDD-VGG

    IGS

    VDSVGS

    ATTEN.

    POWERMETER

    POWERSENSOR

    POWERMETER

    POWERSENSOR

    RF POWERSOURCE

    BIASTEE

    DCBlock

    50 term.

    BIASTEE

    Rg *

    2. POWER MEASUREMENT SYSTEM BLOCK DIAGRAM

    Internally Matched FETs

    IDS

    DCBlock

    50 term.

    DIRECTIONALCOUPLER

    DIRECTIONALCOUPLER

    RFAMP

    DETECTOR DETECTOR

    SCALERNETWORKANALYZER

    50 term.

    D.U.T.

    * Use Fujitsu's recommended gate resistance (Rg) as indicatedon the data sheet for the device under test . Follow device handlingand bias precautions presented at the beginning of this section.

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    ELECTRICAL MEASUREMENTS

    POWERMETER

    POWERSENSOR

    DC POWER SUPPLY+VDD-VGG

    IGS

    VDS

    ATTEN.

    POWERMETER

    POWERSENSOR

    RF POWERSOURCE

    Freq.=f

    DCBlock

    50 term.

    BIASTEE

    Rg *

    IDS

    DCBlock

    50 term.

    DIRECTIONALCOUPLER

    SPECTRUMANALYZER

    ATTEN.

    3 dBHybrid

    RF POWERSOURCEFreq.=f+ f

    RFAMP

    50 term.

    Be sure that the power level of signals input to the spectrum analyzer remain in the linearrange of the analyzer's internal mixer.

    3. IM3 MEASUREMENT SYSTEM BLOCK DIAGRAM

    EFFECT OF A DRIVER AMPLIFIER ON TOTAL IMD

    Degradation in IM3 = 20 log 1+10

    where IM3(D) is the driver stage IM3IM3(F) is the final stage IM3

    ( )

    IM3 (D) IM3 (F)

    6

    4

    2

    0 10 20 30IM3 (F) - IM3 (D)

    D e g r a

    d a

    t i o n

    i n I M 3 ( d B ) example: IM3 (D) = -40dBc

    IM3 (F) = -30dBcIM3 = -30 + 2.4

    = -27.6dBc

    [ [IM3(D) - IM3(F)

    20

    50 term.

    RFAMP

    50 term.

    VGS

    VAR.ATTEN.

    BIASTEE

    DIRECTIONALCOUPLER D.U.T.

    * Use Fujitsu's recommended gate resistance (Rg) as indicatedon the data sheet for the device under test . Follow device handlingand bias precautions presented at the beginning of this section.

    50

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    ELECTRICAL MEASUREMENTS

    50 term.

    DCBlock

    4. PHASE DEVIATION MEASUREMENT SYSTEM BLOCK DIAGRAM

    DIRECTIONALCOUPLER

    DC POWER SUPPLY

    +VDD-VGG

    D.U.T.

    IGS

    VDSVGS

    POWERMETER

    POWERSENSOR

    RF POWERSOURCE

    BIASTEE

    Rg *

    IDS

    DIRECTIONALCOUPLER

    RFAMP

    VECTORNETWORKANALYZER

    50 term.

    50 term.

    ATTEN.

    VAR.ATTEN.

    CONVERTER/ TEST SET

    REF TEST

    VAR.ATTEN.

    PHASESHIFTER

    DCBlock

    ATTEN.BIASTEE

    DIRECTIONALCOUPLER

    POWERMETER

    POWERSENSOR

    LOWPASS

    FILTER

    * Use Fujitsu's recommended gate resistance (Rg) as indicatedon the data sheet for the device under test . Follow device handlingand bias precautions presented at the beginning of this section.

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    ELECTRICAL MEASUREMENTS

    5. PULSE POWER MEASUREMENT SYSTEM BLOCK DIAGRAM

    Pulsed Drain Bias

    DC POWER SUPPLY

    +VDD-VGG

    IGS

    VGS

    PEAKPOWERMETER

    POWERSENSOR

    RF POWERSOURCE

    Rg *

    RFAMP

    PULSEGENERATOR

    ATTEN.

    OSCILLO-SCOPE

    PEAKPOWERMETER

    Trig.CH-1CH-2

    PulsedDrainBias

    PULSEMODULATOR

    D.U.T.BIASTEE

    BIASTEE

    DIRECTIONALCOUPLER

    50 term.

    VAR.ATTEN.

    50 term.

    50 term.

    DCBlock

    DCBlock

    PULSEDRIVER

    POWERSENSOR

    * Use Fujitsu's recommended gate resistance (Rg) as indicatedon the data sheet for the device under test . Follow device handlingand bias precautions presented at the beginning of this section.

    Package Outlines

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    ELECTRICAL MEASUREMENTS

    DC POWER SUPPLY

    +VDD-VGG

    D.U.T. TUNER

    IGS

    VDSVGS

    NOISE FIGUREAND GAIN

    METER

    TUNERBIASTEE

    BIASTEE

    Rg *

    LOCALOSCILLATOR

    LOW NOISEAMPLIFIER

    IDS

    50 term. 50 term.

    6. NOISE FIGURE AND ASSOCIATED GAINMEASUREMENT SYSTEM BLOCK DIAGRAM

    MIXER

    NOISESOURCE

    * Use Fujitsu's recommended gate resistance (Rg) as indicatedon the data sheet for the device under test . Follow device handlingand bias precautions presented at the beginning of this section.

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    ELECTRICAL MEASUREMENTS

    MEASUREMENT PROCEDURE

    Open and close switches S1, S2, S3, and S4 according to the timing diagram illustrated in Figure 2. The heatinterval should be much longer than the thermal response time of the device under test (10 seconds). Themeasurement interval should be as short as possible (less than 50 sec.). The constant measurement current(IM) is a small current so selected that the measurement power dissipation may be neglected compared to theheat power dissipation.

    The measurement is made in the following manner:

    a. VDS is set to a specified value.b. VGS is set to a specified value, or adjusted

    to obtain a specified drain current I DS.c. VGS1 is measured during the pre-heatmeasurement interval.

    d. VGS2 is measured during the post-heatmeasurement interval.

    Then thermal resistance is calculated as follows:

    Rth(Channel-Case) = (V GS 1-VGS 2)/(K x VDSx IDS )Where K is the thermal coefficient of V GS (mV/ C)

    K is obtained in the following manner:

    a. Short the DUT drain and source to ground.b. Adjust the gate forward current to the value IM.c. Measure V GS at two different ambient temperatures less than 100 C.

    Then K is calculated as follows:

    K=(VGSa -VGSb )/(Tb-Ta) where Tb>Ta

    VGS Detector

    DC POWER SUPPLY

    +VDS-VGS

    D.U.T.

    IMIDS

    S1 S2S4

    S3

    S1

    S2

    S3

    S4

    Figure 2. Switch Timing Diagram

    VGS1 Heat Interval V GS2

    MeasurementInterval

    MeasurementInterval

    Note: DC bias conditions and accept/reject criteria shall be included in individual device specifications.

    7. THERMAL RESISTANCE MEASUREMENT SYSTEM BLOCK DIAGRAMAND MEASUREMENT PROCEDURE

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    for further information please contact:

    FUJITSU COMPOUND SEMICONDUCTOR, INC.2355 Zanker Rd.San Jose, CA 95131-1138, U. S. A.TEL: (408) 232-9500FAX: (408) 428-9111www.fcsi.fujitsu.com

    FUJITSU QUANTUM DEVICES EUROPE, LTD.Network HouseNorreys DriveMaidenhead, Berkshire SL6 4FJUnited KingdomTEL: +44 (0) 1628 504800FAX: +44 (0) 1628 504888

    FUJITSU QUANTUM DEVICES SINGAPORE PTE LTD.HONG KONG BRANCHRm. 1101, Ocean Centre, 5 Canton Rd. Tsim Sha Tsui,Kowloon, Hong KongTEL: +852-2377-0227FAX: +852-2377-3921

    FUJITSU QUANTUM DEVICES LIMITEDBusiness Development Division11th Floor, Hachioji Daiichi-Seimei Bldg.3-20-6 Myojin-choHachioji-city, Tokyo, 192-0046, JapanTEL: +81-426-43-5885FAX: +81-426-43-5582

    2001 FUJITSU COMPOUND SEMICONDUCTOR, INC.

    Printed in U.S.A. FCSI012001M3.5K