eInfochips Semiconductor Solutions

Overview

Semiconductor Division

Semiconductor Offerings

Tools Expertise

Client Relationships

Success Stories

Agenda

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Overview

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Product Innovation Partner

Spec-to-Silicon Expertise

50+ Verification and Design IPs

14 VIPs for EDA Companies

Strategic EDA Alliances

40+ Tape-outs including 16nm Tech.

12 Long term ODCs

Semiconductor Division

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150+First Pass Success

12Tier-1 ODCs

16+Years of Experience

20+Design IPs

30+Verification IPs

Globally #1 in Silicon Design Services

Offerings

Silicon Design Reference Design Product Design

Partner with R&D to tape-out flawless

Silicon on schedule

Empower Sales to showcase features of new silicon platforms

Enable your Clients to build custom products

using latest Silicon

SoC / ASIC Design

SoC Verification

Physical Design

Silicon Validation

Reference Design

EVM Development

Proof of Concepts

GTM by Technology showcase

Electronic Hardware Design

Embedded SW

Industrial Design

QA and Certification5

eInfochips’ Design Solutions

Quick Prototyping for multi-million ASIC into multiple FPGAs 20+ Proven Design IPs, Expertise in Low Power IP Integration

Proven, well defined Internal methodologies 25+ FPGA/ASIC Design Projects, 60% from existing clients

Cross domain expertise in Networking, Avionics, & Video Multi FPGA DO 254 Compliant ssafety critical system

Architecture &optimization techniques across FPGA/CPLD Close relationship with Xilinx, Altera and Actel

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Fast Track IP Development Computing algorithms (WRED, trTCM, DEFLATE) , Protocols (MIPI, Storage)

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eInfochips’ Verification Solutions

30% Cost benefit by re-usable components

One of few to develop Verification IPs for EDA Vendors 14 VIPs and 50 variants, 50+ customers worldwide

Faster Debug & Root Cause Analysis Verification Infrastructure with Messaging techniques for faster debug

Strategically focused on Verification beyond services Scalable & reusable Verification Environ., 30+ in-house VIP

Well Defined Methodologies Ensures verification effectiveness, adopted by leading EDA

27+ defects in market-proven VIPs, deployed for more than 2 years

Mature Checklist ensures ZERO Post Silicon bugs

eInfochips’ Physical Design Solutions

Achieved Tape out with, 90% Area Utilization, 80% High VT Cells on wireless SoC 7 ECOs in 3 weeks on 50Mn Gate count SoC Timing closure on 150 Mn gate count ASIC on unusual rectilinear shapres of Floorplan

Complete Turnkey Ownership 75+Silicon Tape-outs across 180nm to 16nm

Technical Expertise Dedicated experts for each design stage, methodology, & tools Interface: SerDes, MIPI, DDR, High Speed CPUs

Domain Expertise Projects across Networking, CE, Telecom, Mobile Area, Power & Time optimization for domain specific require.

Comprehensive Internal checklist for Sign off Netlist to GDSII in < 3 iterations

eInfochips ConfidentialeInfochips

Confidential

eInfochips Board Design Solutions

• 400+ Product Design• 150+ Hardware Design to Prototype/Production• 15+ CMs in 6 Countries

Summary

• Multi-core SoC design• Multi-processor (8 dual-core on a single board)

designs• FPGA based designs

Processors

• Size: 1.5 to 140+ square inches• Layers: Up to 16 Layer PCB• Frequency: Few KHz to 3.0 Gbps• Technology: HDI (2-level micro vias, Via on Pad)

Board

• 4200 + with 25 BGAs• - 1031 pins with 0.65mm pitch

Components

5.26%2.63%

71.05%

21.05% Layout density

>10.5 to 0.90.1 to 0.490.05 to 0.09<0.05

31%

28%

41%PCB layer count

Up to 8 layers 8 to 10 layers10 to 16 layers

38%

35%

26%

Board Frequencies>1GHz

500MHz to 1GHz

<500MHz

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eInfochips ConfidentialeInfochips

Confidential

Tools & Platforms Expertise

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Design Tools

• Cadence OrCAD• Mentor DxDesigner• Allegro• PADS• Expedition• Betasoft• Hyperlinx• Spectra-Quest

VertexSpartan

Kintex

CycloneFlexNios

A3P Series

ASIC Design

•QuestaSim•Modelsim•VCS•Design & DFT Compiler•PT

FPGA Design

•Synplify-Pro•Xilinx-ISE •Altera-QuartusII•Actel-Libero•ChipScope•SignalTapII•Leonardo Spectrum•PCie Analyzer•Logic Analyzer•O-Scope•CHIPit-PlatinumV4•HAPS Board•Palladium, EVE

Verification

• IUS•NC-Sim•Conformal•Questasim•Modelsim•Formality•FinSim, VeriLint•exploreRTL, LEDA•Verix, SureCov•CoverMeter•HDLScore•NextGen MVRC• IUS LP, CLP LEC

Implementation

•Magma Talus•Blast & Quartz•Synopsys DC• ICC, Astro•PrimeTime, PTSI•TetraMAX•StarRC XT•MG Calibre•SoC Encounter•Celtic, Nanoroute•Virtuoso, Conformal LEC

5 out of Top 10 global semiconductor companies trust us with complete offshore ownership for turnkey projects

Client Trust

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95% of business from Offshore Delivery Centers (ODCs)

Development centers in Ahmedabad, Bangalore and Pune

• A majority of projects delivered out of Ahmedabad - ensures low

attrition and knowledge continuity for client projects

• Bangalore and Pune centers attract talent and ensure proximity

to clients

Client Relationships

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8 of our Top-10 Clients have been with us for 3+ years

• Average engagement duration for top-10 client ODCs is 4.5 years

• Maximum ODC engagement duration is 12 years, and counting!

• Turnkey Ownership - Value Creation beyond staff-augmentation

• Top semiconductor companies have audited and recommended our ODC infrastructure

and delivery capabilities

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ODC Snapshot

Global Data Networking Giant• 7 Tape-outs, first pass silicon

• Clean GDSII for 150M Gate, 1GHz SoC

• Proven Offshore Checklist and Delivery, < 5% Schedule Variance

• Methodology Enabler for CTS, Floorplan

65nm Router Switch

40nm Multiple ASIC Switch

Two 40nm ASICs

Three 28nm ASICs

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ODC Snapshot

A Leading EDA Tools Company • Developed and maintained 13 VIPs, Supported 30 Variants

• Verification Tool Validation, validation of latest Low Power Features

OpenVera VIP

UMM / VMM Enabled 8 VIPs

Memory Models 2 VIPs

Low Power, Tool Validation 5 VIPs

Accolades

“Appreciate eInfochips for their thoroughness in DO-254 compliant development, which

delighted our end customer”- Leading Aerospace Solutions provider

“worked with diligence & appreciate the perseverance in performing the difficult task

of narrowing platform behavior on RTL simulation”

- World's largest semiconductor chip maker

“Would like to thank you for your exemplary efforts in helping us tape out in a timely, efficient and

productive manner.”- Leading manufacturer of networking equipment

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“Thank you all for your support and professional work. It has been a unique experience - I never had any close encounters with your country and culture.”- Japanese electronics conglomerate

Why eInfochips

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Matured Processes and Internal Checklists Evolved over 16 years of delivery excellence in ASIC

Early access to tools & technologies Strategic Alliances with EDA and FPGA companies, to achieve a competitive edge

Proven Design and Verification IPs Ensuring high performance, reliability & manufacturability, at lower cost

Turn KeySpec to Silicon Services

Thank you

For more information, write us at marketing@einfochips.com

or visit www.einfochips.com