efficient multi-channel dsc motor driver 1.0-2008 3 fitipower integrated technology lnc. fp5533...
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1 FP5533-Preliminary 1.0-2008
FP5533fitipower integrated technology lnc.
Efficient multi-channel DSC motor driver
Description FP5533 is an efficient multi-channel DSC motor driver. It has 5 channel, when used in exclusive control mode, it can be used as 5.5 channel motor driver (two of them can’t be operate at the same time).Each channel can provide 600mA current. The control method is flexible. Use the provide code, it can be controlled by an MCU to act as constant voltage(CV) driver, constant current(CC) driver and full swing driver, the output level of CV and CC model is realized by the embedded DACs, which is also controlled by MCU code. Due to the CMOS process and Charge Pump-less topology, the consumption current is low, the package is small TQFN-40(5mm*5mm), so it is suitable for portable product. The protect function includes UVP and Thermal shutdown.
Pin Assignments:
Fig.1 pin assignments
Features Built-in 3ch Schmitt trigger Low operation current: I(VCC)=1mA Low standby and shutdown current: 5uA Internal DAC set CV and CC output accuracy:
±5% Serial digital input control Separated analog vcc and power vm Wide operation power supply, excellent low voltage operation Low on resistance of the driver:1.2Ω typical @VM=5V UVP and thermal shutdown PI on voltage:0.3V@Io=30mA 40 pin 5X5mm small TQFN package
Applications Motor driver for Digital still camera Ordering information
TR: Tape / Reel Blank: Tube G: Green Product Package Type WQ: TQFN-40
FP5533
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Typical Application Circuit
Fig.2 Typical application circuit
Functional Pin Description Pin Name Pin Function Pin Name Pin Function
CS Serial input control NC Not connected
SCLK Serial input clock PI1 PI1 output
SDAT Serial input data PI2 PI2 output
VCC Small signal power supply PI3 PI3 output
DGND Small signal block ground OUT3A CH3 output A
IN5B CH5 input B PGND3 CH3 Power GND
IN5A CH5 input A OUT3B CH3 output B
IN4 CH2/CH4 input B VM3 CH3 power supply
IN3 CH2/CH4 input A STIN2 Schmitt trigger 2 input
IN2 CH1/CH3 input B STOUT2 Schmitt trigger 2 output
IN1 CH1/CH3 input A STIN3 Schmitt trigger 3 input
OUT1A CH1 output A STOUT3 Schmitt trigger 3 output
PGND12 CH1/CH2 Power GND OUT4A CH4 output A
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OUT1B CH1 output B RNF4 CH4 current sense(CC) or power GND(CV)
VM12 CH1/CH2 power supply OUT4B CH4 output B
OUT2A CH2 output A VM45 CH4/5 power supply
PGND12 CH1/CH2 Power GND OUT5A CH5 output A
OUT2B CH2 output B RNF5 CH5 current sense
STIN1 Schmitt trigger 1 input OUT5B CH5 output B
STOUT1 Schmitt trigger 1 output RESET Logic reset
Block Diagram
Fig.3 Block Diagram
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Absolute Maximum Ratings VCC to GND---------------------------------------------------------------------------------------------------------------- - 0.3 to + 5.5V
VM12 to DGND------------------------------------------------------------------------------------------------------------ - 0.3 to + 5.5V
VM3 to DGND-------------------------------------------------------------------------------------------------------------- - 0.3 to + 5.5V
VM45 to DGND------------------------------------------------------------------------------------------------------------ - 0.3 to + 5.5V Note:Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device.
Recommended Operating Conditions Supply Voltage, VCC-------------------------------------------------------------------------------------------------------------------- 2.7V-3.6V
Supply Voltage, VM12,VM3,VM45---------------------------------------------------------------------------------------------------- 2.7V-5.5V
RNF4/5 resistor value-------------------------------------------------------------------------------------------------------------------- 1-3Ohm
Operation Temperature Range--------------------------------------------------------------------------------------------------------- - 20°C to + 75°C
Storage Temperature Range------------------------------------------------------------------------------------------------------------ - 40°C to + 150°C
SCLK frequency------------------------------------------------------------------------------------------------------------------------- 5MHz
Note: VCC, VM12, VM3 and VM45 all reference to GND, which connects all PGNDs and DGND
Electrical Characteristics (TA = 25°C, VM=5V VCC=3.3V if not otherwise noted)
Parameter Symbol Test Conditions Min Typ Max Units Note
SUPPLY SECTION
Operation current I_op All driver’s on, no protections 0.4 1 mA
Stand by and reset current I_off Reset=L or soft reset by SW 0 5 uA
Stand by and reset current(VM) I_M Reset=L or soft reset by SW, or VCC=0V 0 5 uA All the sum of
VMs
Low voltage detection voltage UVLO_L 1.6 1.8 2.0 V
Low voltage recovery voltage UVLO_H 1.8 2.0 2.2 V
FULL SWING DRIVER SECTION
ON Resistance 1 Ron_1 At VM=5V,Io=100mA 1.2 1.6 Ω
ON Resistance 2 Ron_2 At VM=3V,Io=100mA 1.5 2.0 Ω
Turn on time TfONH 0.5 2 uS
Turn off time TfOFFH 0.1 0.5 uS
Output rise time Tfr 0.1 0.3 1 uS
Output fall time Tff
RM=50Ω Io=100mA(see Fig4)
0.05 0.2 uS
CONSTANT VOLTAGE DRVER(ON resistance same to full swing part)
Turn on time TvONH 12 20 uS
Turn off time TvOFFH 0.1 2 uS
Output rise time Tvr 0.1 3.0 10 uS
Output fall time Tvf
RM=50Ω Io=100mA(see Fig4)
0.05 1 uS
Constant voltage output Vout No load -5.0 0 +5 %
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CONSTANT CURRENT DRIVER SECTION
ON Resistance 1 RIon_1 At VM=5V,Io=100mA RNF=0V 1.2 1.6 Ω
ON Resistance 2 RIon_2 At VM=5V,Io=100mA RNF=0.2V 1.2 1.65 Ω
ON Resistance 3 RIon_3 At VM=5V,Io=100mA RNF=0.3V 1.25 1.68 Ω
ON Resistance 4 RIon_4 At VM=3V,Io=100mA RNF=0V 1.5 2 Ω
Turn on time TIONH 5 10 uS
Turn off time TIOFFH 0.05 2 uS
Output rise time Tir 4 8 uS
Output fall time Tif
RM=50Ω Io=100mA(see Fig4)
0.03 1 uS
RNF voltage VRNF1 RNF=1Ω DAC accuracy -5.0 0 5.0 %
THSD SECTION
Thermal shutdown temperature TTSD 130 150 170
Thermal return on temperature TTSDL 100 120 140
INPUT PIN SECTION
High level input current I_ih VIN=VCC=3.3V -1 0 1 uA Terminal of SCLK and SDAT
Low level input current I_il VIN=VCC=3.3V -1 0 1 uA
High level input current I_ih1 VIN=VCC=3.3V 20 33 47 uA Terminal of RESET and CS
Low level input current I_il1 VIN=VCC=3.3V -1 0 1 uA
Input pull down resistance RIND 70 100 130 KΩ
High level input current I_ih2 VIN=VCC=3.3V -1 0 1 uA
Terminal IN1~IN4,IN5A
and IN5B while standby and
reset
Low level input current I_il2 VIN=VCC=3.3V -1 0 1 uA
Input pull down resistance RIND1 ∞ ∞ KΩ
High level input current I_ih3 VIN=VCC=3.3V 20 33 47 uA
Terminal IN1~IN4,IN5A
and IN5B while active
Low level input current I_il3 VIN=VCC=3.3V -1 0 1 uA
Input pull down resistance RIND2 70 100 130 KΩ
High level input voltage V_ih VCC=2.7~3.6V Vcc*0.7 - Vcc V
Low level input voltage V_il VCC=2.7~3.6V 0 - Vcc*0.3 V
Hysterisis voltage V_hys 250 mV Terminal of
CS,SCLK and SDAT
PI DRIVER SECTION On voltage V_pion Io=30mA - 0.3 0.5 V V(PI*) <=VCC Leak current while off I_pioff VCC ≥ PIOUT -2.0 0 2.0 uA
Output rise time T_pir RL=150Ω(see Fig5) - 0.1 1 uS
Output fall time T_pif - 0.1 1 uS
SCHMITT TRIGGER SECTION
Threshold voltage high level V_sthh 1.3 - 2.2 V
Threshold voltage low level V_sthl 0.6 - 1.3 V
Hysteretic voltage V_shys 0.3 - 1.2 V
Output high voltage V_soh Io=-24mA 2.2 - - V
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Output low voltage V_sol Io=24mA - - 0.55 V
Input current I_sic STIN*=0~VCC -5.0 0 5.0 uA
Switching delay time T_ssd CL=30pF, RL=500ohm(see Fig5) - - 6 uS
Fig.4 Driver wave characteristics
VIN
IDRIVER
tON
tOFF
tOFF
tON
tf
tr
tr
0%
0%
100%
100%
100%
90%
50% 50%
50%
10%
90%
50%
10%
-10%
-50%
-90%
-100%
-50%
-90%
-10%
tf
Fig.5 PI/STOUT response characteristics
CS/STIN*
PI*/STOUT* output
tf
0%
100%
50%
50%
tr
100% 0% 50%
0%
100%
50%
100%
CS/STIN*
PI*/STOUT* output
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Control Function
Fig.6 Serial control signal pattern
Serial control code Address Data No. Item
b7 b6 b5 b4 b3 b2 b1 b0
A0 1,2,3ch control mode setup 0 0 0 12 ch mode setup 3ch mode setup 123ch exclusive control
A1 4,5ch control mode setup 4ch CC/CV mode change 0 0 1 4 ch mode setup 5ch mode setup 4ch CC/CV
A2 1,2ch disable bit control 3,4ch serial control 0 1 0 12ch
disable 3ch serial control 4ch serial control
A3 1,2ch dac setup 1,2ch FS/CV mode change 0 1 1 1,2ch DAC 12ch FS/CV
A4 3ch DAC setup 3ch FS/CV mode change 1 0 0 3ch DAC 3ch FS/CV
A5 4ch DAC setup 4ch FS/CV drive mode change 1 0 1 4ch DAC 4ch FS/CV
A6 5ch DAC setup Parallel Input Select 1 1 0 5ch DAC Input Select
A7 PS, RESET control PI driver control
1 1 1 PS PI1 control
PI2 control
PI3 control SW reset
Reset table:
Reset (Pin40) SW Reset (soft reset) Chip logic
L X Initial clear
H 0 Enable
H 1 Initial clear
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Detailed control function A0:1, 2, 3ch mode setup
Address Data
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 1,2ch mode setup 3ch mode setup 1,2,3ch exclusive mode set
Bit Name Function
b4b3 1,2ch mode
setup
12ch input mode
00: EN/IN control
01: IN/IN control
10: 3lines control (STM 1-2 phase drive)
11: 2lines control (STM 1-1 phase drive)
b2b1 3ch mode setup
3ch input mode
00: EN/IN control
01: IN/IN control
10: serial control
11: no meaning
b0 1,2,3ch exclusive
mode select
Combination control select:
0: normal mode
1: exclusive mode
A1:4,5ch mode setup Address Data
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1 4ch mode setup 5ch mode setup 4ch CC/CV
Bit Name Function
b4b3 4ch mode setup
4ch input mode
00: EN/IN control
01: IN/IN control
10: serial control
11: 3lines control (4,5ch CC 2phase drive)
b2b1 5ch mode setup
5ch input mode(note)
00: EN/IN control
01: IN/IN control
10: 1lines control (forward)
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11: 1lines control (reverse)
b0 4ch CC/CV mode
select
0: CC mode
1: CV or FS mode (depends on b0 in A5)
Note: The 1lines control b2b1=10 or 11 only effective while IN5A=H, if these two code is set and IN5A=L the CH5 state is off, ie:
IN5A b2b1 OUT5A OUT5B 5CH
L - High impedance High impedance off
H 10 H L forward
H 11 L H reverse
A2:1,2ch disable/3,4ch serial control Address Data
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1,2ch disable 3ch serial control 4ch serial control
Bit Name Function
b4b3 1,2ch disable
1,2ch disable setting(effective only when 1,2ch works in 2lines or 3lines control mode:A0-b4b3=10or 11)
0: disable
1: enable
b2b1 3ch serial control
3ch drive mode control (effective only when 3ch works in serial control mode:A0-b2b1=10)
00: off
01: forward
10: reverse
11: brake
b0 4ch serial control
4ch drive mode control(effective only when 3ch works in serial control mode:A1-b4b3=10)
00: off
01: forward
10: reverse
11: brake
A3:1,2ch DAC setup and 1,2ch FS/CV set Address Data
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1 1,2ch DAC 1,2ch FS/CV
Bit Name Function
b4b3
b2b1
1,2ch DAC to set
1,2ch CV output
1.8~4.8V
0000:4.80V 1000:3.20V
0001:4.60V 1001:3.00V
0010:4.40V 1010:2.80V
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0.20V/step 0011:4.20V 1011:2.60V
0100:4.00V 1100:2.40V
0101:3.80V 1101:2.20V
0110:3.60V 1110:2.00V
0111:3.40V 1111:1.80V
b0 1,2ch drive mode
select
0: CV
1: FS
A4:3ch DAC setup and 3ch FS/CV set
Address Data
b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 3ch DAC 3ch FS/CV
Bit Name Function
b4b3
b2b1
3ch DAC to set
3ch CV output
1.8~4.8V
0.20V/step
0000:4.80V 1000:3.20V
0001:4.60V 1001:3.00V
0010:4.40V 1010:2.80V
0011:4.20V 1011:2.60V
0100:4.00V 1100:2.40V
0101:3.80V 1101:2.20V
0110:3.60V 1110:2.00V
0111:3.40V 1111:1.80V
b0 3ch drive mode
select
0: CV
1: FS
A5:4ch DAC setup and 4ch FS/CV set
Address Data
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 4ch DAC 4ch FS/CV
Bit Name Function
b4b3
b2b1
4ch DAC to set
4ch CV output
1.8~4.8V
0.20V/step
4ch CC RNF
CV mode CC mode:
0000:4.80V 1000:3.20V 0000:300mV 1000:220mV
0001:4.60V 1001:3.00V 0001:290mV 1001:210mV
0010:4.40V 1010:2.80V 0010:280mV 1010:200mV
0011:4.20V 1011:2.60V 0011:270mV 1011:190mV
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output
150mV~300mV
10mV/step
0100:4.00V 1100:2.40V 0100:260mV 1100:180mV
0101:3.80V 1101:2.20V 0101:250mV 1101:170mV
0110:3.60V 1110:2.00V 0110:240mV 1110:160mV
0111:3.40V 1111:1.80V 0111:230mV 1111:150mV
b0 4ch drive mode
select
only effective when A1-b0=1
0: CV
1: FS
A6:5ch DAC setup
Address Data
b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 5ch DAC -
Bit Name Function
b4b3
b2b1
5ch DAC to set
5ch CC RNF
output
150mV~300mV
10mV/step
0000:300mV 1000:220mV
0001:290mV 1001:210mV
0010:280mV 1010:200mV
0011:270mV 1011:190mV
0100:260mV 1100:180mV
0101:250mV 1101:170mV
0110:240mV 1110:160mV
0111:230mV 1111:150mV
b0 Parallel Input
Select
IN1/IN2/IN3/IN4
0: IN1A/IN1B/IN2A/IN2B in effect
1: IN3A/IN3B/IN4A/IN4B in effect
A7: PS, RESET and PI control
Address Data
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 PS PI1 control PI2 control PI3 control S/W reset
Bit Name Function
b4 Power save 0: power off (standby)
1: power on (active)
b3 PI1 control 0: output off: high impedance
1: output on: low impedance
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b2 PI2 control 0: output off: high impedance
1: output on: low impedance
b1 PI3 control 0: output off: high impedance
1: output on: low impedance
b0 S/W reset 0: normal working, no action
1: all the data in the register set to 0
Note: CH1-5 use H bridge output structure
Fig.7 H bridge output structure
For ch1-5, direction forward means current from OUTA to OUTB, PA and NB conduct current while PB and NA cut off; reverse means current from OUTB to OUTA, PB and NA conduct current while PA and NB cutoff Off means all MOS are cutoff, output is high impedance to both VM and PGND Brake means NA and NB active to pull OUTA and OUTB to gnd, PA and PB cut off. Output is low impedance to PGND but high impedance to VM
Parallel function table Note: IN1* and IN2* can’t be synchronous in effect with IN3* and IN4*, which lie on the “Parallel Input Select” bit setup. While IN5* is independent unit.
CH1~5 EN/IN control
IN*A IN*B OUT*A OUT*B MODE
0 - Z Z off
1 0 H L forward
1 1 L H reverse
H: high level L: low level Z: high impedance
CH1~5 IN/IN control
IN*A IN*B OUT*A OUT*B MODE
0 0 Z Z off
1 0 H L forward
0 1 L H reverse
1 1 L L brake
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1,2ch 3lines STM control
IN1A IN1B IN2A OUT1A OUT1B OUT2A OUT2B mode 1CH 2CH mode2
1 1 0 H L H L 1 forward forward 1
0 1 1 Z Z H L 2 off forward
0 1 0 L H H L 3 reverse forward 2
0 0 1 L H Z Z 4 reverse off
0 0 0 L H L H 5 reverse reverse 3
1 0 1 Z Z L H 6 off reverse
1 0 0 H L L H 7 forward reverse 4
1 1 1 H L Z Z 8 forward off
1,2ch 2lines STM control
IN1A IN1B OUT1A OUT1B OUT2A OUT2B mode 1CH 2CH
1 1 H L H L 1 forward forward
0 1 L H H L 2 reverse forward
0 0 L H L H 3 reverse reverse
1 0 H L L H 4 forward reverse
At the timing while mode2 of 3lines control=mode of 2lines control the mode can be changed.
4,5ch 3lines control
IN4A IN4B IN5A OUT4A OUT4B OUT5A OUT5B 4CH 5CH
0 - - Z Z Z Z off off
1 0 0 H L H L forward forward
1 0 1 H L L H forward reverse
1 1 0 L H H L reverse forward
1 1 1 L H L H reverse reverse
12-3ch exclusive control
1ch EN/IN control 1ch IN/IN control IN1A IN1B
OUT1A OUT1B OUT3A MODE OUT1A OUT1B OUT3A MODE
0 0 Z Z Z off Z Z Z off
0 1 Z Z Z off L Z H reverse
1 0 H Z L forward H Z L forward
1 1 L Z H reverse L Z L brake
Current direction OUT1A->OUT3A is forward
2ch EN/IN control 2ch IN/IN control IN2A IN2B
OUT2A OUT2B OUT3B MODE OUT2A OUT2B OUT3B MODE
0 0 Z Z Z off Z Z Z off
0 1 Z Z Z off L Z H reverse
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1 0 H Z L forward H Z L forward
1 1 L Z H reverse L Z L brake
Current direction OUT2A->OUT3B is forward 12-3ch exclusive control (resemble 4ch driver, which make this IC “5.5 CH” driver) configuration:
Fig.8 Exclusive control mode
Schmitt trigger 1~3 control table
STIN* STOUT*
H L
L H
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Application Circuits
CS
SCLK
SDA
T
VC
C
DG
ND
IN5B
IN5A
IN4
IN3
IN2
STOUT1
STIN1
OUT2B
PGND12
OUT2A
VM12
OUT1B
PGND12
OUT1A
IN1
NC
PI1
PI2
PI3
OU
T3A
PGN
D3
OU
T3B
VM
3
STIN2
STOU
2
RESET
OUT5B
RNF5
OUT5A
VM45
OUT4B
RNF4(PGND4)
OUT4A
STOUT3
STIN3
STM
DCM
VCC=3.3V
VM=5V
Control
signals
Fig.9 CH1/CH2/CH3 Application Circuit 1
IN1 and IN2 for STM 2 lines phase control; IN1, IN2 and IN3 for STM 3 lines phase control
Serial data for CH3 DCM control
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CS
SCLK
SDA
T
VC
C
DG
ND
IN5B
IN5A
IN4
IN3
IN2
STOUT1
STIN1
OUT2B
PGND12
OUT2A
VM12
OUT1B
PGND12
OUT1A
IN1
NC
PI1
PI2
PI3
OU
T3A
PGN
D3
OU
T3B
VM
3
STIN2
STOU
2
RESET
OUT5B
RNF5
OUT5A
VM45
OUT4B
RNF4(PGND4)
OUT4A
STOUT3
STIN3
DCM
VCC=3.3V
VM=5V
Control
signals
DCM
DCM
Fig.10 CH1/CH2/CH3 Application Circuit 2
IN1, IN2, IN3 and IN4 for CH1, 2 DCM EN/IN or IN/IN control
Serial data for CH3 DCM control
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STOUT1
STIN1
OUT2B
PGND12
OUT2A
VM12
OUT1B
PGND12
OUT1A
IN1RESET
OUT5B
RNF5
OUT5A
VM45
OUT4B
RNF4(PGND4)
OUT4A
STOUT3
STIN3
VCC=3.3V
VM=5V
DCM
DCM
Fig.11 CH1/CH2/Ch3 Application Circuit 3
IN1, IN2, IN3 and IN4 for CH1/3, 2/3 DCM EN/IN or IN/IN control
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STOUT1
STIN1
OUT2B
PGND12
OUT2A
VM12
OUT1B
PGND12
OUT1A
IN1RESET
OUT5B
RNF5
OUT5A
VM45
OUT4B
RNF4(PGND4)
OUT4A
STOUT3
STIN3
VCC=3.3V
VM=5V
STM STM
Fig.12 CH1/CH2/CH3 Application Circuit 4
IN1 and IN2 for STM 2 lines control
IN1, IN2 and IN3 for STM 3 lines control
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CS
SCLK
SDA
T
VC
C
DG
ND
IN5B
IN5A
IN4
IN3
IN2
NC
PI1
PI2
PI3
OU
T3A
PGN
D3
OU
T3B
VM
3
STIN2
STOU
2
Control
signals
Fig.13 CH4/CH5 Application Circuit 5
IN3 and IN4 for IRIS EN/IN or IN/IN, FS/CV control, or serial data control IRIS
IN5A and IN5B for SHUTTER EN/IN or IN/IN, FS control
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CS
SCLK
SDA
T
VC
C
DG
ND
IN5B
IN5A
IN4
IN3
IN2
NC
PI1
PI2
PI3
OU
T3A
PGN
D3
OU
T3B
VM
3
STIN2
STOU
2
Control
signals
Fig.14 CH4/CH5 Application Circuit 6
IN3 and IN4 for IRIS EN/IN or IN/IN, CC control, or serial data control IRIS
IN5A and IN5B for SHUTTER EN/IN or IN/IN, CC control
IN3, IN4 and IN5A 3 lines control, 2 IRIS simultaneous control
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Outline Information
TQFN- 40 5mm x 5mm Package (Unit: mm)
DIMENSION IN MILLIMETER SYMBOLS
UNIT MIN NOM MAX A 0.70 0.75 0.80
A1 0.00 0.02 0.05
b 0.15 0.20 0.25
C --- 0.20 REF ---
D 4.90 5.00 5.10
D2 3.25 3.30 3.35
E 4.90 5.00 5.10
E2 3.25 3.30 3.35
e --- 0.40 ---
L 0.35 0.40 0.45
y 0.00 --- 0.075
Note 1:Followed From JEDEC MO-220-J.
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Life Support Policy Fitipower’s products are not authorized for use as critical components in life support devices or other medical systems.
Revision History
Version Content Date
0.1 New Issue 2007-06-06
0.2 Change the Ordering information: add G: green product
Correct the unit in the electrical characteristics. 2008-02-13
0.3 Add application circuit 2008-2-29
0.4 Modify outline information 2008-4-29