EEE2243Digital System Design

Chapter 7: Advanced Design Considerations

by Muhazam Mustapha, extracted from Intel Training Slides,April 2012

Learning Outcome

• By the end of this chapter, students are expected to be aware of some advanced timing and power issues in IC design

Chapter Content

• Timing Considerations– Static & Dynamic Timing– Flop & Latch Based Design– Setup & Hold– Design Window

• Power Considerations– Types of Power– Power Reduction Strategies

Timing Considerations

Static vs. Dynamic Timing Analysis

Static Timing Analysis• Non-simulation approach used to analyze

propagation of delays• Computes worst case delays for paths• Based upon possibility of a path existence

– If the path can exist, it is traversed and delay is calculated

– Uses delay to check signal arrival times in order to determine setup and hold margins

• Used more often than dynamic analysis

Static vs. Dynamic Timing Analysis

Dynamic Timing Analysis• Circuit simulation approach• Obtains accurate timing analysis of paths by

using input waveforms and path sensitization, and generating output waveforms– Specific input vectors / sensitization needed to

exercise a particular path

• Used for special circuits

What is a Flip-flop-Based Design?• Simplest implementation sequential circuits• Used for implementation of state machines• Most commonly will utilize rising edge trigger• Characterized by having no transparency• Each flip-flop contains a master and a slave

What is a Flip-flop-Based Design?• Example:

Flip-flop-Based Design• The logic between a and b should be design so

that signal transitions propagate through the logic fast enough to be captured by the receiving flip-flop

• In order for the flip-flop input to be captured at the clock edge, the signal must be stable some period of time before the clock edge

• We call this time the setup time of the flip-flop:– The minimum duration of time for INPUT to be stable

BEFORE the arrival of triggering clock edge

Flip-flop-Based Design• Signal b has maximum delay constraints based

on the setup time of the receiving flip-flop and the timing of the rising edge of clk2

• Maximum delay failures are frequency dependent

• Hold time – a short period of time following the clock edge when a flip-flop could still capture data– The minimum duration of time for INPUT to stay

stable AFTER the arrival of triggering clock edge

Flip-flop-Based Design• Significance of setup time and hold time is that

they put the total shortest time that the data must stay stable for the system to work

• Setup time + Hold time = minimum time for data to stay stable for the system

• This minimum time sets the maximum frequency for the data to change

What is Latch-Based Design?• Latch-based design uses transparent latches

What is Latch-Based Design?• Latch is open transparent when data may pass

freely from the input to the output

Design Windows• Each signal captured by a sequential has both

max-delay and min-delay constraints• Design window is a timing windows into which

the signal timing must conform

Design Windows (cont)

Power Considerations

Why Low Power?• Competitive needs

– The competition is no longer on highest MIPS or performance

• Technology requirement– Smaller form factor– More IO / power pins– Higher power density

• Social responsibility– Green technology

• Consumer preference• Battery life

AF / SP Definition• Activity Factor (AF) is the switching rate of a net

during a given workload clock• AF = 1 indicates that it makes 1 full transition

(up and down) each clock cycle• AF is needed to compute dynamic power• Signal Probability (SP) is the percentage of time

a net spends at logic value 1 vs 0• SP is needed to compute leakage power

AF / SP Definition

Dynamic Power• Power consumed when the device is toggling

• Pdyn = AF × CL × V × V × F = Cdyn × V × V × F

CL

Short Circuit Power• Also known as Rush

Through Power• Power wasted when

current flow directly VCC to VSS momentarily due to input slope transitions slowly

Short Circuit Power• Can be calculated using the circuit’s voltage and

current timing diagram

Glitch Power• Power caused by “unwanted overlap” in input

vectors• Consider the waveform of the inputs and output

of the following multiplexer:

Out

a

b

Sel

Glitch Power

Glitch Power

Power Estimation• Average power dissipation at a gate can be

calculated if we are given the probability of its HIGH level and the power dissipated at the (nodes) output and inputs

• Compute the probability of each input combination

• The probability will be used as weightage for the power at each node

• Power dissipated by the gate is the total of power at all inputs and output

Power Estimation (Example)• Given the following information, calculate the

average power dissipated by the NAND gate

B

AF

Node Probability of Logic 1

Power

A 0.7 2μW

B 0.4 3μW

F 0.7 4μWA B F

0 0 1

0 1 1

1 0 1

1 1 0

P(A=1 & B=1) = 0.3

P(A=1 & B=0) = 0.4

P(A=0 & B=1) = 0.1

P(A=0 & B=0) = 0.2

Power Estimation (Example)

At A=0 B=0 power = 0 + 0 + 4μ×0.2

At A=0 B=1 power = 0 + 3μ×0.1 + 4μ×0.1

At A=1 B=0 power = 2μ×0.4 + 0 + 4μ×0.4

At A=1 B=1 power = 2μ×0.3 + 3μ×0.3 + 0

The average power is the sum of above = 5.4μW

Power Estimation (Exercise)• Given the following information, calculate the

average power dissipated by the AND gateNode Probability of Logic 1 Power

A 0.7 2μW

B 0.4 3μW

F 0.4 4μW

Ans: 4.2μW

• Given the following information, calculate the average power dissipated by the NOR gate

Node Probability of Logic 1 Power

A 0.5 2μW

B 0.4 3μW

F 0.3 4μW

Ans: 2.4μW

Power Estimation (Exercise)• Given the following information, calculate the

average power dissipated by the OR gateNode Probability of Logic 1 Power

A 0.5 2μW

B 0.3 3μW

F 0.6 4μW

Ans: 4.3μW