Chapter 6: Interrupts,

Clock Generation, Resets, and Operation Modes

EE383: Introduction to Embedded Systems

University of Kentucky

Samir Rawashdeh

With slides based on material by H. Huang – Delmar Cengage Learning

1

The HCS12 CPU Registers

7 00 7A B

15 0D

8-bit accumulator A and Bor16-bit double accumulator D

15 0X

15 0Y

Index register X

Index register Y

15 0SP Stack pointer

15 0PC Program counter

Condition code register

CarryOverflow

Zero

Negative

I Interrupt mask

Half-Carry (from bit 3)

X Interrupt Mask

Stop Disable

Figure 1.10 HCS12 CPU registers.

S X H I N Z V C

Fundamental Concepts of Interrupts

What is an interrupt?

� A special event that requires the CPU to stop normal program execution and

perform some service related to the event.

� Examples of interrupts include I/O completion, timer time-out, illegal opcodes,

arithmetic overflow, divide-by-0, etc.

Functions of Interrupts

� Coordinating I/O activities and preventing CPU from being tied up

� Reminding the CPU to perform routine tasks

Interrupt Maskability

� Interrupts that can be ignored by the CPU are called maskable interrupts.

� A maskable interrupt must be enabled before it can interrupt the CPU.

� An interrupt is enabled by setting an enable flag.

� Interrupts that can’t be ignored by the CPU are called non-maskable interrupts.

Interrupt priority

� Allow multiple pending interrupt requests

� Resolve the order of service for multiple pending interrupts

Interrupt Service

� CPU executes a program called the interrupt service routine (ISR).

� A complete interrupt service cycle includes

1. Saving the program counter value in the stack

2. Saving the CPU status (including the CPU status register and some other

registers) in the stack

3. Identifying the cause of interrupt

4. Resolving the starting address of the corresponding interrupt service routine

5. Executing the interrupt service routine

6. Restoring the CPU status and the program counter from the stack

7. Restarting the interrupted program

Interrupt Vector

Starting address of the interrupt service routine

Interrupt Vector Table

A table where all interrupt vectors are stored.

Methods of Determining Interrupt Vectors

1. Predefined locations (Microchip PIC18, 8051 variants)

2. Fetching the vector from a predefined memory location (HCS12, Atmel AVR)

3. Executing an interrupt acknowledge cycle to fetch a vector number in order to

locate the interrupt vector (68000 and x86 families)

Steps of Interrupt Programming

Step 1. Initializing the interrupt vector table

Step 2. Writing the interrupt service routine

Step 3. Enabling the interrupt

HCS12 Exceptions

� Maskable interrupts: including IRQ pin and all peripheral function interrupts.

� Nonmaskable interrupts: including XIRQ pin, SWI interrupt, and unimplemented opcode

trap.

� Resets: including the power-on reset, reset pin manual reset, the COP reset (computer

operate properly), and clock monitor reset.

Maskable Interrupts

� Different HCS12 members implement different number and types of peripheral functions,

and hence may have different number of maskable interrupts.

� One of the maskable interrupts can be raised to the highest priority among the maskable

interrupt group and receive quicker service. This is achieved by programming the

HPRIO register.

IRQ Pin Interrupt

� The only external maskable interrupt for the HCS12.

� IRQ interrupt can be edge-triggered or level-triggered.

� IRQ interrupt has a local enable mask in the IRQCR register.

� The IRQ interrupt is configured by programming the IRQCR register.

� The contents of the IRQCR register are shown in Figure 6.2.

Non-maskable Interrupts

� XIRQ pin, SWI instruction, & unimplemented instruction opcode trap.

XIRQ Pin Interrupt

� XIRQ interrupt is disabled during a system reset and upon entering the service routine of

another XIRQ interrupt.

� After minimal system initialization, software can clear the X bit of the CCR register to

enable the (using the andcc #$BF instruction) XIRQ interrupt. Software cannot reset the X

bit once it has been set.

� When a non-maskable interrupt is recognized, both the X and I bits are set after CPU

registers are saved.

� The execution of an RTI instruction at the end of the XIRQ service routine will restore the

X and I bits to the pre-interrupt request state.

Unimplemented Opcode Trap

� There are 202 unimplemented opcode on page 2 (16-bit opcode).

� These unimplemented opcode share the same vector $FFF8:$FFF9.

Software Interrupt Instruction (SWI)

� Execution of the SWI instruction causes an interrupt without an interrupt request signal.

� The SWI instruction is commonly used in the debug monitor to implement breakpoints

and to transfer control from a user program to the debug monitor.

� A breakpoint in a user program is a memory location where we want program execution

to be stopped and information about instruction execution (in the form of register

contents) to be displayed.

Interrupts in D-Bug12 EVB Mode

� On-chip flash memory locations are not available for user to stored interrupt vectors.

� D-Bug12 monitor provides SRAM-based interrupt vector table.

� The SRAM-based table (in Table 6.3) starts at $3E00 and has 64 entries.

� The interrupt SCI0 has been used by the monitor and is not available to the user.

� Mnemonic names are defined for users to store their interrupt vectors in the table. Both

the hcs12.inc and the vectors12.h (for C language) have the definitions for these entries.

Setting Up the Interrupt Vector

� Assume that the label (or name) of the IRQ interrupt service routine is irqISR.

In assembly language,

For miniIDE (D-Bug12 monitor), the interrupt vector must be stored in SRAM

movw #irqISR,UserIRQ ; store the vector at the designated address

The Stack Order on Entry of an Interrupt

� The HCS12 saves all CPU registers on an interrupt.

� The order of saving CPU registers is shown in Figure 6.3.

The RTI Instruction� RTI is used to terminate interrupt service routines.

� RTI will restore CPU registers from the stack.

� The HCS12 will continue to execute the interrupted program unless there is another

pending interrupt.

Real Time Interrupt

- Main function is to generate periodic interrupt to the MCU.

- The RTI interrupt is enabled by the CRGINT register (shown in Figure 6.11)

- The interrupt interval of RTI is selected by the RTICTL register (shown in Figure 6.16).

- The actual available interrupt periods for RTI are listed in Table 6.4.

Table 6.4 RTI interrupt period (in units of OSCCLK cycle)

RTR[3:0] RTR[6:4]

000(off)

001(210)

010(211)

011(212)

100(213)

101(214)

110(215)

111(216)

0000 (÷1)0001(÷2)0010 (÷3)0011 (÷4)0100 (÷5)0101 (÷6)0110 (÷7)0111 (÷8)1000 (÷9)1001 (÷10)1010 (÷11)1011 (÷12)1100 (÷13)1101 (÷14)1110 (÷15)1111 (÷16)

off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*

210

2×210

3×210

4×210

5×210

6×210

7×210

8×210

9×210

10×210

11×210

12×210

13×210

14×210

15×210

16×210

211

2×211

3×211

4×211

5×211

6×211

7×211

8×211

9×211

10×211

11×211

12×211

13×211

14×211

15×211

16×211

212

2×212

3×212

4×212

5×212

6×212

7×212

8×212

9×212

10×212

11×212

12×212

13×212

14×212

15×212

16×212

213

2×213

3×213

4×213

5×213

6×213

7×213

8×213

9×213

10×213

11×213

12×213

13×213

14×213

15×213

16×213

214

2×214

3×214

4×214

5×214

6×214

7×214

8×214

9×214

10×214

11×214

12×214

13×214

14×214

15×214

16×214

215

2×215

3×215

4×215

5×215

6×215

7×215

8×215

9×215

10×215

11×215

12×215

13×215

14×215

15×215

16×215

216

2×216

3×216

4×216

5×216

6×216

7×216

8×216

9×216

10×216

11×216

12×216

13×216

14×216

15×216

16×216

Computer Operating Properly (COP) Circuit

� Allow the user to determine whether the application software operates properly.

� The COP is a timer circuit that will time out if it is not rearmed within a preset

time limit.

� The COP will reset the MCU when it times out and the user would know if the software

operate properly.

� The application software would include an instruction sequence to prevent the COP

from timing out.

� To prevent the COP from timing out, write $55 and then $AA into the ARMCOP register.

� The time out period of the COP is controlled by the COPCTL register.

� The contents of the COPCTL are shown in Figure 6.17.

Clock and Reset Generation Block (CRG)

� CRG generates the clock signals required by the HCS12 instruction execution and all

peripheral operations.

� The clock signal has the form of square waveform.

� Crystal oscillators are often used to generate clock signals.

� The crystal oscillator output is a sinusoidal wave and must be converted to square wave

before it can be used.

� The HCS12 has internal circuit to do this square up operation.

� The CRG block also has a PLL circuit that can multiply the frequency of the incoming

clock signal.

� The block diagram is shown in Figure 6.4.

� The CRG can also accept oscillator output (square waveform) directly.

Choice of Clock Source

� The user can choose between using the external crystal or oscillator to produce the clock

signal.

� The external crystal is connected between the EXTAL and XTAL pins and needs an

on-chip oscillator circuitry to square it up.

� The external clock source provided by the oscillator is connected to the EXTAL pin and

have a 2.5V peak to peak magnitude for D family.

� The XCLKS signal must be grounded to select the external clock signal.

� The output from the OSC module in Figure 6.4 may bypass or go through the PLL circuit.

� The PLL circuit has the capability to multiply incoming signal frequency and stabilize

its output signal frequency.

� Either the OSCCLK or the PLLCLK can be chosen as the SYSCLK which will be

divided by 2 to derive the bus clock to control the instruction execution and peripheral

operation.

� The HCS12 clock generation circuit is shown in Figure 6.15.

Phase Locked Loop

� The frequency of the PLLCLK is controlled by registers SYNR and REFDY using the

following equation:

(SYNR + 1)

PLLCLK = 2 × OSCCLK × ------------------- (6.1)(REFDV + 1)

reset:

0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

0 0 0 0 0 0 0 0

Figure 6.8 The CRG synthesizer register (SYNR)

01234567

reset:

0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0

0 0 0 0 0 0 0 0

Figure 6.9 The CRG reference divider register (REFDV)

7 6 5 4 3 2 1 0

Selection of PLL for clock generation is controlled by the CRGSEL register.

PLL circuit is also controlled by the PLLCTL register.