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EE241 - Spring 2013Advanced Digital Integrated Circuits

Lecture 3: Features of Modern Technologies

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Agenda

Previous lectureScaling issues

Technology scaling trends

Features of modern technologies

Today’s lectureFinish lithography

Typical 32/28nm process

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C. 32/28nm Technology Features - Lithography

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Litho: How to Enhance Resolution?

1. Immersion

2. Off-axis illumination

3. Resolution enhancement/Optical proximity correction

4. Restricted design rules (RDR)

5. Phase-shifting masks

6. Double patterning

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Litho (1): Immersion

Project through a drop of liquid

nwater = 1.47

IBM

min 1

1930.25 35

1.35nm

CD k nmNA

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Litho (2): Illumination

Amplifies certain pitches/rotations at expense of others

Regular Illumination

Many off-axis designs (OAI)

Annular

Quadrupole / Quasar

Dipole +

or

Based on A.Kahng, ICCAD’03

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Litho (3): Resolution Enhancement

J.Hartmann, ISSCC’07

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OPCOptical Proximity Correction (OPC) modifies layout to compensate for process distortions

Add non-electrical structures to layout to control diffraction of light

Rule-based (past) or model-based

A.Kahng, ICCAD’03

Design Mask

OPC Fracture

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Litho (4): Restricted Design Rules

J.Hartmann, ISSCC’07

Also: note poly density rules

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Litho (5): Phase-Shift Masks

Phase Shifting Masks (PSM)Creates interference fringes on the wafer Interference effects boost contrast Phase Masks can make extremely small lines

conventional maskglass Chrome

Electric field at mask

Intensity at wafer

phase shifting mask

Phase shifter

A.Kahng, ICCAD’03

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Litho (6): Double Patterning

Double exposure double etchDouble exposure double etch

Pitch split

Double exposure single etchDipole decomposition (DDL)

Pack-unpack for contact

Resist freeze technology

Sidewall image transfer (SIT)

From Colburn, VLSI Technology 2008 Workshop

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Double-Exposure Double-EtchStarting layout Line + cut split Cut over line

Result:SRAM image from K. Mistry, IEDM’07

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Pitch Split Double ExposureStarting layout Split pattern Overlay

With overlay misalignment

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32nm Examples

Single exposure Double exposure

IEDM’08

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Litho: Design Implications

Forbidden directionsDepends on illumination type

Poly lines in other directions can exist but need to be thicker

Forbidden pitchesNulls in the interference pattern

Forbidden shapes in PSM

Assist featuresIf a transistor doesn’t have a neighbor, let’s add a dummy

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Litho: Current Options (Beyond 22nm)

Immersion lithographyUse high index (NA ~ 1.6-1.7, k1 < 0.3)

Double patterningNA ~ 1.2-1.35

EUV lithography (?) = 13.5nm

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D. Typical 32/28nm Process

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Some of the Process Features

1. Shallow-trench isolation

2. High-k/Metal-gate technology

3. Strained silicon

4. Thin-body devices (28nm, and beyond)

5. Copper interconnects with low-k dielectrics

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1. Shallow Trench Isolation

Less space needed for isolation

Some impact on stress

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

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2. Hi-k/Metal gate

Replacement gate technology (Intel)

S. Natarajan, IEDM’08

K. Mistry, IEDM’07

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3. Strained Silicon

High Stress

Film

NMOS

SiGe SiGe

PMOS

Compressive channel strain Tensile channel strain30% drive current increase 10% drive current increasein 90nm CMOS in 90nm CMOS

Intel

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Intel’s Strained Si Numbers

90 nm 65 nm

NMOS PMOS NMOS PMOS

20% 55% 35% 90%

IDSAT 10% 30% 18% 50%

IDLIN 10% 55% 18% 80%

Performance gains:

S. Thompson, VLSI’06 Tutorial

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Strained Silicon

No strain Strained Si

OutIn

VDD

M2

M1

OutIn

VDD

M2

M1

W1 = 1

W2 ~ 2

W1 = 1

W2 = 1.6

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5. Thin-Body Devices

28nm FDSOI 22nm finFET

N. Planes, VLSI’2012 C. Auth, VLSI’2012

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5. Interconnect

J. Hartmann, ISSCC’07

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Interconnect: CMP

Ta barrier layerto prevent Cu fromdiffusing into Si

Etch stop (SiN)

Mi

Mi-1

Cu interconnect: Dual damascene process

Metal density rules (20%-80%)

Slotting rules

Also: Antenna rules

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Next Lecture

Device models