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EE241 - Spring 2013Advanced Digital Integrated Circuits

Lecture 23: PLLs

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Announcements

Office hour on Monday moved to 1-2pm and 3:30-4pm

Final exam next Wednesday, in classOpen book open notes

Project reports due May 3, presentations are on May 6 at BWRC

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Project reports

Project reports

6 pages, two columns

ContentTitle, authors, contact

Abstract

Intro

Background

Key idea – what did you do?

What do you base your results on? What did you implement?

Results

Conclusion

Presentations

In BWRC on May 6

1-4:30pm

6min + 4min/person slots

(i.e. single person: 10min, 3 people projects: 18min)

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Outline

Last lectureClock generation

Phase locked loops

This lectureContinue PLL components

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6. Clocks and SuppliesC. PLL Components

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Charge Pump

Converts PFD digital UP/DN signals into charge

Charge is proportional to duration of UP/DNsignals

Qcp = IUP*tUP – IDN*tDN

The LPF converts integrates currents

Charge pump requirements:Match currents IUP and IDN

Reduce control voltage coupling

Supply noise rejection, PVT insensitivity

(Simple or bandgap biased)

LPF

UP

DN

IUP

IDN

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Charge Pump: Better Switches

Unity-gain buffer controls the voltage over switchesCurrent mirrored into Iup/Idn

Transmission gate switches

Young, JSSC 12/92

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Loop Filter

Integrates charge-pump current onto C1 cap to set average VCO frequency (“integral” path).

Resistor provides instantaneous phase correction w/o affecting avg. freq. (“proportional” path).

C3 cap smoothes IR ripple on Vctl

Typical value Rlpf in k

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Loop Filter: Dual CP

Transformation into PI

Dual charge pump architectureproportionalintegral

Maneatis, JSSC 12/96

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Low-Pass Filter Smoothing Cap (C3)

“Smoothing” capacitor on control voltage filters CP ripple, but may make loop unstable

Creates parasitic pole: �p = 1/(R C3)

C3 < 1/10*C1 for stability

C3 > 1/50*C1 for low jitter

Smoothing cap reduces “IR”-induced VCO jitter to < 0.5% from 5-10%

�fvco = KvcoIcpTerr/C3

Larger C3/C1 increases phase error slightly

Fischette, ISSCC’04

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Filter Capacitors

Traditionally thin gate capacitance has been usedBelow 130nm gate leakage is a problem

C1 in the range of tens of pF

Alternative: thick oxide or metal capArea penalty

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Variable Delay Elements

Need:a delay element

a method to vary the delay

Delay elementsinverter

source-coupled amplifier

Methods to vary delaymultiplexing a tapped delay line

varying the power supply to an inverter chain

varying the capacitance driven by each stage

varying the resistive load of a source-coupled amplifier

Characterized bymax and min delay

typically a 2:1 throw

stability (jitter)

td

[Dally]

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Variable Delay Elements

Single-ended vs. differential

In CMOS inverter 1% of change in supply changes the delay by 1%

(keep this in mind when using clock buffering)

Current starved inverters and RC-loaded inverters are worse than 1%-for-1%.

Improve by adding stabilization

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Example VCO

Ring-oscillator-based VCO: RC loaded

Ring-oscillator-based VCO: Current-starved

Jeong, JSSC’87

Hudson, JSSC’88

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Regulated Delay Line

Sidiropoulos’00

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VCO: simple differential delay

Change currentOr better: ResistancesNeed linear, variable resistors

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Delay Elements

Maneatis, JSSC’95

6. Clocks and SuppliesD. Digital PLL in Practice

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Digital PLL

Replace analog functions with digital equivalents

PFD Digital LoopFilter

DCO÷N

U

D

fO

fREF

Digitally-controlled oscillator (DCO)

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Practical Digital PLL

In IBM Power7 processor, per each core

Tierno, VLSI’10

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One PLL with multiple DLLs

Single PLL, and two cores vary frequency through digital frequency dividers (DFDs) and DLLs

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Clock and Supply

Large digital systems can have large voltage transientsCan we filter impact of voltage on a clock generator?

Kurd, JSSC’09

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Clock and Supply

IBM Power7, with one PLL per core

Lefurgy, MICRO’11

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Clock and Supply

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6. Clocks and SuppliesE. Supply Voltage

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Supply Generation

LinearSeries or shunt

Linear regulation

Quiet

Inefficient (unless Vin-Voutis small)

Switching (Capacitive)Limited efficiency

Poor regulation

Voltage ripples

Switching (Magnetic)Efficient

Require external components

Noisy

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Power Delivery

Typical model

Wong, JSSC’06

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Next Lecture

Finish supply voltage

Wrap up