EE178 LectureLecture 3Dr. Tri CaohuuFrom Xilinx/Eric NotesFall 2009

Lecture 3

• Introduction to Design Flows.

Design Flows

• A design flow is a sequence of stepsyou use to turn an idea into reality.

• The basic design flow does not change.

Design Flows

• Idea or Specification: You want to implementyour idea, or someone else’s idea.

• Circuit Design: From this idea, youdesign a representation of it.– Schematics.– Hardware description languages.– Other methods.

Design Flows

• Once you have a representation of the design,you should verify that the design is correct.

• Some form of verification is key.– Simulation with test vectors.– Formal verification.

• How much verification is enough?

Design Flows

• Depends on what you want to achieve...– Spot check.– Peaceful sleep at night.– Coverage of all cases.

• Depends what is at risk...– Your grade.– Your job.– Life and limb.

Design Flows

• Implementation: From the representationof the design you created, go “build it”.

• This step can range from very simple tovery complicated, depending on the typeof implementation you are building.

• In the introduction to digital design course,you simply drop SSI logic devices on aprototyping board and wire them up.

Design Flows

• Test: Once you have an implementation,you will want to turn it on and test it.– Did smoke come out when you power it on?– Does it work as you expect?

• If things do not work as you expect, youmay find yourself going back to any oneof the previous steps.– Can be very expensive to do so.– Verification is the key to saving time and money.

Design Flows

• Example design flow from EE118.– Start with laboratory specification.– Draw schematics, maybe simulate.– Build the design, test it, probably

doesn’t work, fiddle with it, checkthe wires, still doesn’t work.

– Go back and check design, fix anywrong stuff, maybe simulate.

– Rewire, test, hopefully it works.

Design Flows

• Example design flow from EE178.– Start with laboratory specification.– Describe design and test bench in Verilog.– Simulate the design, fix errors in the design.– Synthesize the design using a synthesis tool.– Implement the synthesized design using the

Xilinx physical implementation tools.– Simulate with annotated timing information.– Download design to hardware and test…

Verification

• Verification is becoming increasinglyimportant when doing digital logic design.

• Back in the day, when designs were smallit may have been easier to build the circuitand test it in hardware.

• Today, designs are huge, and delayingverification until hardware exists is anexpensive proposition.

Verification

• Verification is a very broad term usedto cover a number of activities relatedto “correctness checking”.

• Depending on your implementationtechnology, you may be faced witha large number of places where thingscan go wrong.

Verification

• You want to check for correctness.• The verification process has become

the bottleneck in the design process.– Verification can be time consuming.– Common to have more people working

on design verification than actual design.

• Even with powerful tools and lots ofexperience, people still miss errors.

Verification

• Let’s look at various types of verification,with particular focus on the types that arepertinent to this course.– Logical correctness.– Static timing analysis.– In system verification.

• Other types of verification.

Logical Correctness

• Immediately after design entry youcan simulate the design for logicalcorrectness.– Schematic simulators.– HDL simulators.

• The goal is to make sure the designbehaves as you intended before youbegin any further steps in the designflow.

Logical Correctness

• Many schematic capture programsinclude a gate-level logic simulator.

• Gate level logic simulators are slow.• Most bundled simulators require

the designer to create test vectors.– Input stimuli.– Expected outputs.

Logical Correctness

• My personal experience is that thesetypes of simulators are useful for smalldesigns only.– Entry of test vectors is tedious.– Entry of test vectors is error prone.– Output checking ability is limited.

Logical Correctness

• For HDL designs, the HDL serves asboth the design language and the testlanguage.– Design is created using a special subset

of the language, synthesizable constructs,which can be realized in hardware.

– Test environment is created using whatever portions of the language work bestfor the verification to be performed.

Logical Correctness

• The design is connected to the testenvironment (the “test bench”) andthe pair are simulated.– The high level nature of the test bench

allows for elaborate testing and checkingof the design.

– These simulators are at least an order ofmagnitude faster than gate level simulators.

Logical Correctness

• How do you determine what to test?– How much time you have to spend.– How much money you have to spend.– Your tolerance for undetected errors.

• Ways to test logical correctness.– Brute force approach and state explosion.– Decomposition of design into small pieces.– Representative events and responses.

Static Timing Analysis

• Once you have a physical implementationof a design, or a model of it, you may wishto perform static timing analysis.– In addition to logical correctness, most designs

have performance requirements in terms ofminimum clock frequency and input/outputtiming relationships.

• Static timing analysis tells you if the designwill meet the set performance requirements.

Static Timing Analysis

• If the design fails to meet the performancerequirements, there are a number of stepswhich can remedy the situation.– Go back and redesign or optimize the logic

design, which would require a check forlogical correctness again.

– Change the physical implementation of thedesign to meet the performance requirements.• Changes in placement and routing• Changes in design mapping

Static Timing Analysis

• If the design is logically correct, and theperformance requirements cover 100%of the design and pass, then the designshould work!

• Notice that I did not say “will” work!!!• Many design flows allow you to take the

delay data from static timing analysis andannotate that information into a gate levelrepresentation of the design.

Static Timing Analysis

• Using a gate level model of the design and thedelay information, you can simulate again.– This is a good sanity check to make sure you

haven’t bungled anything else along the way.– One can argue this is not necessary if your logic

design is correct and you have performed thecorrect static timing analysis.• Are you perfect?• Are the tools perfect?

In System Verification

• Once you have actual devices, they must betested to make sure they operate as specified.– Verify on an expensive tester.– Verify in the lab with debug equipment.– Verify in the actual system.

Other Verification

• The verification points discussed apply to logicdesign using programmable logic devices.

• Other technologies have other verificationcheckpoints on which I am not qualified tolecture.– Layout verification.– Photolithography mask inspection.– So on and so on...