ecs interface library user guide - laboratoire de...

ECS Interface Library User Guide

1MHz version

Version: Release_v3.1Last modified: 22.10.2008Prepared by: Hui Gong, Alex Gong, Hou Lei, Dai Gang and

Guido Haefeli

Note that this document is strongly related to the TELL1 firmware version!

1

Document status sheet

3.2 12.02.2009 Version increased to be compatiable with firmware. The Velo and ST new compiled.3.1 22.10.2008 Version increased to be compatiable with firmware.3.0 03.10.2008 1． Added a function to check FE data for all sub-detectors. If no FE data

accompanies TTC/ECS trigger, MEP generator will send out empty event. This function is defiantly disabled Add FE_data_check_ctrl_register

2． Added serious error throttle for all sub-detector. 3． Added TTC parity check4． Added periodic NZS bank scheduler.5． Insert forced stop cycles for GBE flow control.6． GBE support auto-negotiation mode7． Add a tell1_selftest routine for hardware test8． L0fe_reset with one clock cycle delay!9． Added new data rate monitor registers for framer allowed data rate10． Added new parameters into the common part of cfg file. 11． Some logic optimized for better timing12． byte calculation error fixed in SL_PP_Linker

New parameters added to the tell1 recipe, all default value can be used._L0013:___ 0x[ 0] _L0030:___ 0x[ 0] _L0031:___ 0x[ 0] _L0032:___ 0x[ 0] _L0033:___ 0x[ 0] _L0041:___ [ 0]Detector specific part13． Re-design the hdl and C codes for L0PUS. 14． Added data generation and error check functionality for L0DU.15． Modified RX readout fsm and the setting of RX event size for L0DU.16． header correction for ST17． arx links f disable or ST.18． error bank parser Corrected for OT.19． EHCAL and PSSPD specific HDL codes received from Nicolas on

May 26. Fixed the fifo underflow bug for PSSPD by Nicolas on May 31.20． Added L0MUON specific HDL codes received from Jean-Pierre on

May 2021． VELO Beetle pseudo header polarity correction22． fix ST/VELO algorithm bugs in both Firmware and Emulator

2

(Pedestal/CMS/Cluster)23． NZS in case of error for VELO/ST (this cause TELL1 data structure

change)

2.7 02.07.2008 Integrate OT specified registers/rams description provided by Mirco.Add No FE data check parameter registerCorrect NZS_BANK_SCHEDULE_CTRL_REG0/1 describritionAdd Pesudo_header_polarity bit for velo in PP_CTRL_REG1Add nzs_for_error_enable bit for velo/st in PP_CTRL_REG1Add GBE_force_idle_cycle in SPI3_RX_CTRL_REG for GBE bandwidth restriction.

2.6 21.5.2008 Added header correction value 4 per link including correction for last two header bits for ST.Added Proc ID register for L0PUS.Added L0DU specific registers and RAMsAdded PP serious error throttle control bit in PP_CTRL_REG1Added SL serious error throttle control bit in THRO_CTRL_REGAdded No FE data check functionality, which can be enabled of disabled by setting bit 30 of SL_CTRL_REG0Added TTC dest IP Parity CheckAdded ARX link control register for STAdded NZS bank schedule register 0 and register 1Add GBE wait after Pause frame in SLAdd ST select PCN, one per PP FPGA

2.5 14.4.2008 1． Fix the bug in C code about the generation of ModelSim simulation init file (set_mem.do) for L0MUON.

2． Correct the wrong definition of bit width of SEP data fifo max usage (from 11 to 14) in C code.Update the ECS document as well: SL_MAX_USE_REG ($0x001054).

3． Fix the bugs that orx link read/write event counts mismatch for L0CAL. 4． Replace two hdl files and fix the bugs that orx link read/write event

counts mismatch for MUON.5． Replace two hdl files for L0Du.6． Change the scheme that pedestal banks are generated.

ECS document and CFG file generation code are modified as well.7． Add two menus under C (tell1 control) in console_tell1:

(d) Disable all orx link(c) Cancel the disable of all orx link

8． Replace detector_specific_vhdl_libraries for EHCAL and PSSPD. Fixed a bug that ZS Link fifo and ZS data fifo will overflow after a few consecutive triggers.

9． Add a tell1 self test function which is called at the beginning of daq_tell1 and can be called by PVSS.

3

10． Fix a bug about the definition of ecs_reg_SL_ERROR_MON_REG_N. ecs_reg_SL_ERROR_MON_REG_N <= X"00"&'0' &pp0_llink_parity_error & pp0_llink_parity_error & -> pp1_llink_parity_errorpp0_llink_parity_error & -> pp2_llink_parity_errorpp0_llink_parity_error & -> pp3_llink_parity_errorqdr_crc_chk_err &mep_info_fifo_underflow &mep_info_fifo_overflow &"000000" &ttc_fifo_error;

11． Check MTU size setting in firmware. If ECS setting value is bigger than 8192, MTU size is assigned with 8192, otherwise, MTU size is equal to ECS setting value but 3 LSB are masked as 0. Notice: ECS setting value is equal to cfg file setting value minus 20.

12． Fix a bug that QDR CRC check state machine doesn’t work well when the length of MEP is too big.

13． Fix a bug that EVT_INFO_FIFO, DEST_IP_FIFO, TRIG_TYPE_FIFO and MEP_END_FIFO will overflow in the case that consecutive ECS triggers are sent too frequently.

14. Reduce the usage threshold of SL PP in fifo to make it safer. 15. Velo: The low threshold is not stored in the cluster para reg anymore, it is in the threshold ram, the document 2.4 was still showing it to be in the register

2.4 5.3.2008 Added the low threshold for Velo per stripAdded the FIR coefficients for VeloAdded header correction value per linkAdded MCMS enable bit for VeloST and VELO header_corr_value link wise, header_corr_threshold per boardST spill_over_threshold, confirmation_threshold instead of sum_th, there is one value per processor channel (2 per Beetle)Add parity check error counter for LLink and QDR Add parity error cnt for Trigger info linksAdded pp_error_mon and sl_error_mon registers

2.3 11.12.2007 Add last sent Dest IP sent by ttc register 0x10010ACAdd test reg in PPs and SL 0x4000010, 0x100001CAdd ecs_error_cnt regs again for PP and SL

4

ECS Interface Library User Guide.............................................................11MHz version.................................................................................................1Version: Release_v2.7............................................................................1Document status sheet...................................................................................21. Memory MAP.........................................................................................82. Registers and RAM for “PP”..................................................................8

2.1 Common Registers....................................................................................................8PP_RESET_REG ($0x000000)..............................................................................................................8PP_CTRL_REG0 ($0x000004)..............................................................................................................9PP_CTRL_REG1 ($0x000008)..............................................................................................................9ORX_CTRL REG ($0x00000C)...........................................................................................................11PPTEST_REG ($0x000010).................................................................................................................12

2.2 Common Monitor registers.....................................................................................12CONSTANT_REG ($0x001000).........................................................................................................12EVT_ASSEM_CNT_REG ($0x001004)..............................................................................................12PP_TRIGGER_CNT_REG ($0x001008).............................................................................................13PP_BANK_CNT_REG0 ($0x00100C)................................................................................................13PP_BANK_CNT_REG1 ($0x001010).................................................................................................13PP_EVENT_CNT_REG ($0x001014).................................................................................................13BER_ERROR_CNT_REG ($0x001018).............................................................................................13BER_RCV_CNT_H_REG ($0x00101C)............................................................................................14BER_ RCV_CNT_L_REG ($0x001020)............................................................................................14INFO_PARITY_ERROR_CNT_REG ($0x001024) reg9..................................................................14PP_ERROR_MON_REG ($0x001028)...............................................................................................14PP_ECS_ERROR_CNT_REG ($0x00102C).......................................................................................15PP_DATE_REG ($0x001034)..............................................................................................................15PP_TIME_REG ($0x001038)...............................................................................................................15PP_VERSION_REG ($0x00103C)......................................................................................................15ORX_PROBE_REG ($0x001040)........................................................................................................15ORX_ SYNC_REG ($0x001044) REALTIME...................................................................................16ORX_ LINK_DISABLE_REG ($0x001048)......................................................................................16FIFO_STATUS_REG ($0x00104C-($0x00104C…0x00104C +11*4)...............................................17

2.3 User Specific Register VELO (starts from 0x002000)...........................................17VELO_ADCCLK_PHY_DLY_REGH ($0x002000)...........................................................................17VELO_ADCCLK_PHY_DLY_REGL ($0x002004)...........................................................................18VELO_ADCCLK_CYC_DLY_REG ($0x002008).............................................................................189 CLUS_PARA_REG ($0x00200C, $0x002010 …$0x00202C).........................................................18ADC_LINK_PROBE_REG ($0x002030)...........................................................................................19ADC_LINK_SYNC_REG ($0x002034).............................................................................................19VELO_PHI_REORDER_STRIP_CNT_REG ($0x002038)...............................................................20VELO_HEADER_CORR_THRESHOLD_REG ($0x00203C)...........................................................20VELO_CLUSTER_NUMBER_MAX_REG ($0x002044)..................................................................20VELO_FIR_COEFFICIENT_REG ($0x002048 …($0x002064 )......................................................20

5

8 Registers.............................................................................................................................................20VELO_HEADER_CORR_VALUE_REG ($0x002068-$0x002084) 8 registers.................................218 Registers last is register 34............................................................................................................21VELO_FIFO_STATUS_REG (access via common monitor registers) 12 registers............................21

2.4 User Specific Register ST (starts from 0x003000).................................................21ST_ARX_LINK_CTRL_REG ($0x003000)........................................................................................2112 CLUS_PARA_REG ($0x003004, $0x003008 …$0x003030)........................................................22Removed register for optical links, they are common registers now !.................................................22ST_HEADER_CORR_THRESHOLD_REG ($0x00303C).................................................................22ST_CLUSTER_NUMBER_MAX_REG ($0x003044)........................................................................22ST_HEADER_CORR_VALUE_LINK0_REG ($0x003048-$0x003074) 12 registers.......................22ST_HEADER_CORR_VALUE_LINK1_REG ($0x003078-$0x0030A4) 12 registers......................23ST_FIFO_STATUS_REG (access via common monitor registers) 12 registers..................................23

2.5 User Specific Register OT (starts from 0x004000)................................................246 OT_OTIS_CTRL_REG ($0x004000 ~ $0x004014).........................................................................24OT_OTIS_STATUS_AB_REG ($0x004018)......................................................................................24OT_OTIS_STATUS_CD_REG ($0x00401C).....................................................................................24OT_ZS_LINKER_ERROR_V_REG($0x004024)...............................................................................25OT_SYNC_CTRL_REG ($0x004028).................................................................................................25OT_OTIS_EVID_MON_REG ($0x00402C).......................................................................................25OT_OTIS_BXID_MON_REG ($0x004030)........................................................................................26OT_OTIS_ID_MON_REG ($0x004034).............................................................................................26OT_OTIS_CNTSTAT_MON_REG ($0x004038)...............................................................................26OT_HIST_CTRL_REG ($0x00403C)..................................................................................................26OT_FIFO_STATUS_REG (access via common monitor registers) 12 registers.................................26

2.6 User Specific Register MUON (starts from 0x006000).........................................276 MUON_TU_TYPE_REG ($0x006000 ~ $0x006014)......................................................................27MUON_HIT_PAD_PROC_CTRL_REG ($0x006018).......................................................................27MUON_ODE_ID_REG1 ($0x00601C)...............................................................................................28MUON_ODE_ID_REG2 ($0x006020)................................................................................................28MUON_ODE_ID_REG3 ($0x006024)................................................................................................28MUON_PAD_MAX_NUM_REG ($0x006028)..................................................................................29MUON_HIT_MAX_NUM_REG ($0x00602C)...................................................................................29MUON_FIFO_STATUS_REG (access via common monitor registers) 12 registers..........................29

2.6’ User Specific Register L0MUON (starts from 0x00C000)...................................30PP_L0MUON_CTRL_REG ($0x00C000)...........................................................................................306 ORX_CONNECTIVITY_TEST_DATA_REG ($0x00C018 ~ $0x00C02C)..................................30

2.7 User Specific Register EHCAL (starts from 0x005000)........................................30CAL_CTRL_REG ($0x005000)...........................................................................................................30EHCAL_FIFO_STATUS_REG (access via common monitor registers) 13 registers.........................30

2.7’User Specific Register L0CAL (starts from 0x00A000)........................................31PP_L0CAL_PARA_REG ($0x00A000)..............................................................................................31L0CAL_FIFO_STATUS_REG (access via common monitor registers) 12 registers..........................31

2.8 User Specific Register RICH (starts from 0x009000)...........................................32RICH_FIFO_STATUS_REG (access via common monitor registers) 12 registers.............................32

2.9 User Specific Register L0PUS (starts from 0x008000).........................................33L0PUS_FIFO_STATUS_REG (access via common monitor registers) 12 registers..........................33L0PUS_PROC_ID_REG ($0x008000)................................................................................................33

2.10 User Specific Register BCM (starts from 0x00C000)..........................................34BCM_FIFO_STATUS_REG (access via common monitor registers) 12 registers.............................34

2.11 User Specific Register L0DU (starts from 0x007000).........................................34L0DU_DAPIN_SPY_REG ($0x007000).............................................................................................34L0DU_SYNC_EVT_CNT_REG ($0x007004)....................................................................................34L0DU_FIFO_STATUS_REG (access via common monitor registers) 12 registers............................35

6

2.12 Common RAM blocks...........................................................................................35DATA_GEN_RAM SectionA (Address range: 0x100000 – 0x1001FF)............................................35DATA_GEN_RAM SectionB (Address range: 0x102000 – 0x1021FF)............................................35DATA_GEN_RAM SectionC (Address range: 0x104000 – 0x1041FF)............................................36DATA_GEN_RAM SectionD (Address range: 0x106000 – 0x1061FF)............................................36DATA_GEN_RAM SectionE (Address range: 0x108000 – 0x1081FF)............................................36DATA_GEN_RAM SectionF (Address range: 0x10A000 – 0x10A1FF)...........................................37TRIGGER_INFO_TEST_RAM (Address range: 0x10C000 – 0x10C1FF).........................................38

2.13 User Specific RAM blocks VELO (starts from 0x200000)..................................388 PEDESTAL RAM (Address range: 0x200000 – 0x2000FF, 0x202000-0x2020FF,….,, 0x20E000 - 0x20E0FF)............................................................................................................................................389 THRESHOLD RAM (Address range: 0x210000–0x2100FF, 0x212000-0x2120FF, … , 0x220000-0x2200FF).............................................................................................................................................38VELO_AVERAGE_HISTOGRAM (Address range: 0x234000–0x237FFF) ram26..........................39VELO_SLOPE_HISTOGRAM (Address range: 0x238000–0x23BFFF) –ram28..............................398 VELO_REORDER_RAM (Address range: 0x23C000–0x23C0FF, … , 0x24A000–0x24A0FF) reserve...................................................................................................................................................39

2.14 User Specific RAM blocks ST (starts from 0x300000)........................................3912 PEDESTAL RAM (Address range: 0x300000 – 0x3000FF, 0x302000-0x3020FF,….,, 0x316000 - 0x3160FF).............................................................................................................................................3912 HIT_THRESHOLD RAM (Address range: 0x318000 – 0x3180FF, 0x31A000-0x31A0FF,….,, 0x32E000 - 0x32E0FF).........................................................................................................................4012 CMS_THRESHOLD RAM (Address range: 0x330000 – 0x3300FF, 0x332000-0x3320FF,….,, 0x346000 - 0x3460FF).........................................................................................................................401 ST_AVERAGE_HISTOGRAM (Address range: 0x348000– 0x349800) –ram36...........................401 ST_SLOPE_HISTOGRAM (Address range: 0x34C000–0x34D800) –ram38.................................40

2.15 User Specific RAM blocks OT (starts from 0x400000).......................................4112 OT_HITNUM_HISTOGRAM (Address range: 0x400000–0x4160FC).........................................41OT_DT_HISTOGRAM (Address range: 0x418000–0x4183FC)........................................................41

2.16 User Specific RAM blocks L0DU (starts from 0x700000)..................................41L0DU_SYNC_SPY_RAM (Address range: 0x700000–0x700400)....................................................41

3. Registers and RAM for “SyncLink”....................................................423.1 Common control registers......................................................................................42

SL_RESET_REG ($0x000000)............................................................................................................42SL_CTRL_REG0 ($0x000004)............................................................................................................42SL_CTRL_REG1 ($0x000008)............................................................................................................44SL_SIMU_CTRL_REG ($0x00000C).................................................................................................45SPI3_TX_CTRL_REG ($0x000010)....................................................................................................45SPI3_RX_CTRL_REG ($0x000014)...................................................................................................46THRO_CTRL_REG ($0x000018)........................................................................................................46SLTEST_REG ($0x00001C)................................................................................................................47MEP_PID_REG ($0x000020)..............................................................................................................47ECS_SIMU_TRIG_NUM_REG ($0x000024).....................................................................................47ECS_SIMU_TRIG_SCHE_REG ($0x000028)....................................................................................47SEP_MSB4_REG ($0x00002C)...........................................................................................................47PEDESTAL_BANK_SCHEDULE_CTRL_REG ($0x000030)..........................................................48BANK_HEADER2_REG ($0x000034)...............................................................................................48SL_TP_REG ($0x000038)...................................................................................................................48MTU_SIZE_REG ($0x00003C)...........................................................................................................49BANK_CLASS_REG ($0x000040).....................................................................................................49NZS_BANK_SCHEDULE_CTRL_REG0 ($0x000044).....................................................................50NZS_BANK_SCHEDULE_CTRL_REG1 ($0x000048).....................................................................50

3.2 Common monitor registers.....................................................................................50SL_PP_PROB_REG ($0x001000)......................................................................................................50

7

SL_EVT_CNT_REG ($0x001004)......................................................................................................50SL_EVT_OUT_CNT_REG ($0x001008)............................................................................................51LLINK_PARITY_ERROR_CNT_REG($0x00100C).........................................................................51SPI3_TX_MEP_CNT_REG ($0x001010)............................................................................................51SPI3_TX_WORD_CNT_REG ($0x001014).......................................................................................51SPI3_TX_SOP_CNT_REG ($0x001018)............................................................................................51SPI3_TX_EOP_CNT_REG ($0x00101C)............................................................................................51TTC_TRIG_CNT_REG ($0x001020) REALTIME............................................................................52TTC_TRIG_TYPE_CNT_REG ($0x001024) REALTIME.................................................................52TTC_DEST_IP_CNT_REG ($0x001028) REALTIME.......................................................................52TTC_RESET_SIG_CNT_REG ($0x00102C) REALTIME.................................................................52SL_TRIG_CNT_REG ($0x001030) REALTIME................................................................................52TRIG_INFO_TX_CNT_REG ($0x001034) REALTIME....................................................................52TRIG_INFO_REQ_CNT_REG ($0x001038) REALTIME.................................................................53TRIG_INFO_FIFO_MON_REG0 ($0x00103C) REALTIME............................................................53TRIG_INFO_FIFO_MON_REG1 ($0x001040) REALTIME.............................................................53MEP_WRITE_CNT_REG ($0x001044).............................................................................................54MEP_READ_CNT_REG ($0x001048)................................................................................................54MEP_MAX_USAGE_REG ($0x00104C)...........................................................................................54SL_ERR_LOG_REG ($0x001050)......................................................................................................54SL_MAX_USE_REG ($0x001054).....................................................................................................56FROZEN_EVID_REG ($0x001058) REALTIME...............................................................................56FROZEN_BCNT_REG ($0x00105C) REALTIME.............................................................................56FRAMER_MAX_USE_REG ($0x001060)..........................................................................................56REAL_RATE_REG0 ($0x001064).....................................................................................................57REAL_RATE_REG1 ($0x001068)......................................................................................................57REAL_RATE_REG2 ($0x00106C).....................................................................................................57REAL_RATE_REG3 ($0x001070)......................................................................................................57REAL_RATE_REG4 ($0x001074)......................................................................................................57SL_FLOWCTRL_MONITOR_REG ($0x001078)..............................................................................58MEP_GT_16K_CNT_REG ($0x00107C)............................................................................................58SL_DATE_REG ($0x001080)..............................................................................................................58SL_TIME_REG ($0x001084)..............................................................................................................59SL_VERSION_REG ($0x001088).......................................................................................................59SL_TRIGGER_FIFO_USED_REG0 ($0x00108C).............................................................................59SL_TRIGGER_FIFO_USED_REG1 ($0x001090)..............................................................................59SL_FEM_DV_CNT_REG ($0x001094) REALTIME.........................................................................59SL_DEST_IP_L0_EVID_LSB_ERROR_CNT_REG ($0x001098)....................................................59THRO_CNT_REG0 ($0x00109C) –REG39........................................................................................60THRO_CNT_REG1 ($0x0010A0).......................................................................................................60THRO_CNT_REG2 ($0x0010A4).......................................................................................................60THRO_CNT_REG3 ($0x0010A8).......................................................................................................60SL_TTC_LAST_DEST_IP_REG ($0x0010AC)..................................................................................60SL_LBUS_TEST_REG ($0x0010B0-$0x0010CC) 8 x 32-bit.............................................................61QDR_CRC_ERROR_CNT_REG ($0x0010D0) reg52........................................................................61SL_ERROR_MON_REG $0x0010D4) reg53......................................................................................61THRO_CNT_REG4 ($0x0010D8) reg 54............................................................................................62TTC_PARITY_ERROR_CNT_REG ($0x0010DC) reg55..................................................................62

3.3 Common RAM blocks.............................................................................................62MEP_LOCATION_RAM (Address range: 0x100000 – 0x1001FF)...................................................62IPv4_HEADER_RAM (Address range: 0x102000 - 0x1020FF).........................................................63INTEL_MAC_LPB_TX_RAM (Address range: 0x104000 - 0x1043FF)...........................................65INTEL_MAC_LPB_RX_RAM (Address range: 0x106000 – 0x1063FF)...........................................65SEP_GEN_RAM (Address range: 0x200000 – 0x20FFFF).................................................................66

4. I2C bus address definition......................................................................66

8

I2C BUS 0 (mixed)..............................................................................................................................66I2C BUS 1 (FPGA bus)........................................................................................................................67I2C BUS 2 (A-Rx DAC bus)................................................................................................................67I2C BUS 3 (GBE Tx card bus).............................................................................................................67

Appendix: Example codes for C access........................................................68

1. Memory MAPBase address :SyncLink = 0x1000000; PP0 = 0x4000000 ; PP1 = 0x5000000; PP2 = 0x6000000; PP3 = 0x7000000

2. Registers and RAM for “PP”

2.1 Common RegistersThe common register region is divided into two parts as control registers part and monitor registers part. The former is used to provide external control/setting signals to the internal TELL1 logic, they are read/write. The latter is used to read out the TELL1 self-generated information like counters, error information, etc. They are read only.

PP_RESET_REG ($0x000000)Bit Name Description Type DefaultRegister Description: One cycle@40MHz after written, the register will return 0x00000000

9

to its default value. Used to generate pulses.

31- 8 N7 - 2 RESERVE0

1 BER_CNT_RESET

Clear all BER relative counters W 0

0 ADC_CLK_RESET

Re-initial all adc_clk phase W 0

R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

PP_CTRL_REG0 ($0x000004)Bit Name Description Type DefaultRegister Description: Provide common and basic control signals for PP process.

0xA0900204

31-24 PSEUDO_BIT_H_THR

High threshold for generate the pseudo header bits. ADC values higher than this value is treated as logic ‘1’.

R/W 0xA0

23-16 PSEUDO_BIT_L_THR

Low threshold for generate the pseudo header bits. ADC values lower than this value is treated as logic ‘0’.

R/W 0x90

15-12 READ_LINK_SEL

The monitor registers for each link share the same ECS address, this field is used to select a certain link’s register to read out.( 0-15 for ARX, 0-5 for ORX)

R/W 0

11 R_reorder Choose the R-sensor reordering for VELO 010 PHI_reorder Choose the Phi-sensor reordering for

VELO0

9 ZS_EN Enable/disable the zerosuppression suppression

1

8 LCMS_EN Linear CM suppression after re-ordering Enable/disable the common mode suppression

0

7 BER_EN Enable/Disable the Bit Error Rate test function ( For ORX only)

R/W 0

6 DATA_GEN_EN

Enable/Disable the internal data generator to replace the actually detector data

R/W 0

5 FIR_EN Enable/disable the FIR ( ARX only) R/W 04 REORDER_EN (VELO only) R/W 03 PEDESTAL_U

PDATE_ENEnable/Disable the pedestal auto update feather, with which the pedestal can follow up the base line shift.

R/W 0

2 PEDESTAL_EN

Enable/Disable the pedestal subtraction R/W 1

1-0 DATA_SCALE_MODE

After pedestal subtraction, determines how to scale the 11bit down to 8bit0: saturate to -128 to 127 (VELO only)1: bit(8..1) (LSB remove)2: bit(9..2) (2LSB remove)3: bit(10..3) (3LSB remove)

R/W 00

10


PP_CTRL_REG1 ($0x000008)Bit Name Description Type DefaultRegister Description: Provide common and basic control signals for PP process.

0x00000020

31-16 RESERVE0 /17 NZS_FOR_ERROR_ENAB

LEWhen set this bit to 1, NZS data will be sent if this PP finds error

R/W 0

16 Pseudo header polarity The bit of pseudo value when pseudo_header_value > PESUDO_BIT_H_THR is set by this bit.

R/W 0

15 pp_serious_err_throttle_en 1 = Enable PP serious err throttle. In this case, if a serous error (such as Fifo overflow&underflow errors, hardware errors) is detected on PP FPGA, a throttle will be sent to SL FPGA. SL FPGA will sum up all kinds of throttles to generate a true throttle signal. Since PP serious err throttle is considered as a throttle from PP FPGA, it can be enabled or disabled by configuration of Throttle_PPx_en bit in THRO_CTRL_REG on SL FPGA.

R/W 0

14 pp_lbus_test_data_gen If pp_lbus_test_en is set to ‘1’, a rising edge transition on this bit will cause lbus transmitting part on all PP FPGAs to send 8 lbus test words to SL FPGA at the same time. The lbus test data received by SL FPGA is stored in SL in fifos, from where the test data can be read out by ECS to check lbus.

R/W 0

13 pp_lbus_test_en It this bit is set to ‘1’, PP lbus test is enabled on PP FPGA. The normal data stream will be corrupted.Otherwise, PP lbus transmitting part (on PP FPGA) works in normal

R/W 0

11

mode.12 MCMS_enable Mean CM subtraction enable,

CM subtraction before re-ordering for the velo

R/W 0

11 Histogram_enable The histogram can only be read if this bit is set to ‘1’, it is not updated during the read operation, set back to ‘0’ to allow the processor to update it

R/W 0

10 PP_USED Bit to indicate that this PP-FPGA is used for DAQ, can be used to disable the chip to sent data to the SyncLink

R/W 1

9 force_info_disable Allows to disable the error bank at PP

R/W 0

8 force_info_enable Allows to force the error bank being created

R/W 0

7 header_correction_enable Enables the header correction for the CMS algorithm for Velo and ST

R/W 0

6-0 CLUS_DERAN_USE_THR Threshold for cluster de-randomizer(in events. VELO has max 128, OPT max 64)

R/W 0x20


ORX_CTRL REG ($0x00000C) Bit Name Description Type DefaultRegister Description: O-Rx control bits, bit error rate test mode 0x3F003F09

31 RESERVED2 0030 ENABLE_ALL

_ORX1=Enable all orx channels0=Disable all orx channels

R/W 0

29- 24 ORX_LCK_REF

Lock to reference output to TLK set 1 for normal operation

R/W 0x3F

23- 14 RESERVED1 000000000013- 8 ORX_LINK_DI

SABLEOne hot encoded disable signal for each optical link 1 = disable, 0 = enableSet 0 for normal operation

R/W 111111

7-6 RESERVE0 005 ORX_PRBS_E

N345Pseudo Random Bit Test Enable signal for Optical card channels: 3, 4, 5.0 = no pseudo random test1 = enable pseudo random test

R/W 0

4 ORX_LOOP_EN345

Internal loop-back enable signal for Optical card channels: 3, 4, 5.0 = disable loop-back, means standard

R/W 0

12

operation.1 = enable Optical card internal loop-back

3 ORX_EN345 Device Enable signal for Optical card channels: 3, 4, 5.1 = Enable these 3 optical channels0 = Puts relative circuit of Optical card in power down mode.

R/W 1

2 ORX_PRBS_EN012

Pseudo Random Bit Test Enable signal for Optical card channels: 0, 1, 2.0 = no pseudo random test1 = enable pseudo random test

R/W 0

1 ORX_LOOP_EN012

Internal loop-back enable signal for Optical card channels: 0, 1, 2.0 = disable loop-back, means standard operation.1 = enable Optical card internal loop-back

R/W 0

0 ORX_EN012 Device Enable signal for Optical card channels: 0, 1, 2.1 = Enable these 3 optical channels0 = Puts relative circuit of Optical card in power down mode.

R/W 1


PPTEST_REG ($0x000010)Bit Name Description Type DefaultRegister Description: To be used for local bus tests 0x1234ABC

D31..0 For test use, no functionality R/W 1234ABCD


2.2 Common Monitor registers

CONSTANT_REG ($0x001000)Bit Name Description Type DefaultRegister Description: Constant informations Note31-24 Reserved R \7-4 DETECTOR_I

Dused to distinguish different synchronizer designs. Use 0x1 for Velo, 0x2 for ST, 0x3 for OT, 0x4 for Cal, 0x5 for

Muon, 0x6 L0MUON, 0x7 for L0DU, 0x8 L0PUS, 0x9 RICH

R \

3 RESERVE0 \2-0 CHIPADDR Hard-wired chip address. R \

R = Read Only; W = Write; R/W = Read/Write; N = Not exist;Note: depends on the version settings in common_TELL1_library and user_TELL1_library

13

EVT_ASSEM_CNT_REG ($0x001004)Bit Name Description Type DefaultRegister Description: 0x00000000

31- 16 Evnt_sync_error_cnt

ORX: Is the number of incomplete received events eg one link enabled missing data no optical data input R \ARX: event in count The number of actual events sent from detector. ( the number of FEM_dv )

15-0 EVT_OUT_CNT

The number of events assembled in the Rx part. R \


PP_TRIGGER_CNT_REG ($0x001008)Bit Name Description Type DefaultRegister Description: the number of trigger request and trigger get 0x00000000

31- 16 TRIGGER_REQ_CNT

The number of trigger request sent from this PP-FPGA to SL-FPGA R \

15-0 TRIGGER_IN_CNT

The number of trigger information sent from SL-FPGA to this PP-FPGA R \


PP_BANK_CNT_REG0 ($0x00100C)Bit Name Description Type DefaultRegister Description: the number of each bank assembled in this PP-FPGA 0x00000000

31- 16 INFO_BANK_CNT The number of information bank R \

15-0 CLUS_BANK_CNT The number of cluster bank R \


PP_BANK_CNT_REG1 ($0x001010)Bit Name Description Type DefaultRegister Description: the number of each bank assembled in this PP-FPGA 0x00000000

31- 16 ADC_BANK_CNT The number of adc value bank R \

15-8 PEDE_BANK_CNT The number of pedestal bank R \

7-0 RAW_BANK_CNT The number of raw bank R \


PP_EVENT_CNT_REG ($0x001014)Bit Name Description Type DefaultRegister Description: the number of events assembled in this PP-FPGA 0x00000000

31- 0 EVENT_CNT The number of event sent from PP to SL R \


14

BER_ERROR_CNT_REG ($0x001018)Bit Name Description Type DefaultRegister Description: Bit Error Rate test, the number of error detected.For each OPT link there is a corresponding register, use the read_link_sel field in the PP_ctrl_reg to select.

31-24 BER_WORD_JUMP_CNT

BER errors caused by the counter shift \

23-0 BER_BIT_JUMP_CNT

Ber errors caused by the counter mismatch

R \


BER_RCV_CNT_H_REG ($0x00101C)Bit Name Description Type DefaultRegister Description: Bit Error Rate test, the bit63-32 of the number of received words.For each OPT link there is a corresponding register, use the read_link_sel field in the PP_ctrl_reg to select.

31-0 BER_RCV_CNT_H

( b63-b32) R \


BER_ RCV_CNT_L_REG ($0x001020)Bit Name Description Type DefaultRegister Description: Bit Error Rate test, the bit31-0 of the number of received words.For each OPT link there is a corresponding register, use the read_link_sel field in the PP_ctrl_reg to select.

31-0 BER_RCV_CNT_L

( b31-b0) R \


INFO_PARITY_ERROR_CNT_REG ($0x001024) reg9Bit Name Description Type DefaultRegister Description: Counter for the number of parity errors on the trigger info bus driven by SL and received by pp fpgas

31

SL_fifo_almost_full

The current value of SL_fifo_almost_full signal on PP FPGA, which is monitored here to check if the hardware connection of this signal on PCB is correct or not, just as a part of lbus test.

R

30..8 reserved7..0 Error cnt 8-bit parity error cnt R \


PP_ERROR_MON_REG ($0x001028) Bit Name Description Type DefaultRegister Description: Counter for the number of parity errors on the trigger info bus driven by SL and received by pp fpgas

15

31 Fifo_7 Overflow info R30 Fifo_7 Underflow info R…. … …17 Fifo_0 Overflow info R16 Fifo_0 Underflow info R

15..1 reserved R

0Info_parity_error

Bus data transmission error, used for EvID,BCnt (trig infor) transmission from SL to PPs

R \


PP_ECS_ERROR_CNT_REG ($0x00102C)Bit Name Description Type DefaultRegister Description: the ECS access error count 0x0000000031- 8 RESERVE0 N7-0 ECS_ERROR_

CNTR \


PP_DATE_REG ($0x001034)Bit Name Description Type DefaultRegister Description: Automatically generated compilation date of the firmware.

\

31-0 DATE ddmmyyyy R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

PP_TIME_REG ($0x001038)Bit Name Description Type DefaultRegister Description: Automatically generated compilation time of the firmware.

\

31-16 Not used R \15-0 TIME hhmm R \


PP_VERSION_REG ($0x00103C)Bit Name Description Type DefaultRegister Description: Frimware release version. \31-16 Reserved \23-16 USER_LOGIC_VERSION Firmware version R \15-8 PP_LOGIC_VERSION Firmware version R \7-0 SL_LOGIC_VERSION Firmware version R \


ORX_PROBE_REG ($0x001040)Bit Name Description Type Defa

ultRegister Description: OPT beetle information ( not event based information)

16

For optical links there is a correspond register, use the read_link_sel field in the PP_ctrl_reg to select. Note that each OPT beetle are divided into 4 8bits data stream each correspond to one beetle analog link. Then the 4 8b data stream are separated into even/odd groups.31-24 RESERVE1 0x00

23 OPT_LINK_DISABLE

this link is disabled

22 OPT_CLK_DEAD The opt_clk of this link is not active

21 OPT_EVT_LONGIf there is an event longer than the set event size (eg 35 words), this bit will set and stick.

R

20 OPT_EVT_SHORTIf there is an event shorter than the set event size (eg 35 words), this bit will set and stick.

R

19 SYNCRAM_O_OFLOW

Once there are more than 4 events stored in the syncRAM, this bit is set and stick

18 SYNCRAM_O_UFLOW

Once read event from empty syncRAM, this bit is set and stick

R

17 SYNCRAM_E_OFLOW

Once there are more than 4 events stored in the syncRAM, this bit is set and stick

R

16 SYNCRAM_E_UFLOW

Once read event from empty syncRAM, this bit is set and stick

R

15 TLK_LOS_FLG TLK loss-of-signal flag. (one situation of error)

R

14 TLK_IDLE_FLG TLK receiver idle flag R

13 TLK_CC_FLG TLK carrier extend flag (indicates error at Tx side)

12 TLK_NORMAL_FLG TLK receiver normal flag11 TLK_ERROR_FLG TLK error flag

10-9 RESERVE0 008-0 SYNCRAM_M_USE The maximum used words of the SyncRAM R


ORX_ SYNC_REG ($0x001044) REALTIMEBit Name Description Type DefaultRegister Description: Optical receiver information (event based information)For each OPT link there is a corresponding register, use the read_link_sel field in the PP_ctrl_reg to select. These counters are used to monitor the length and number of events written and read from the input synchronization RAM.Note that there are two RAM (EVEN and ODD) for the ST but only One (EVEN) for the Simple optical receiver (SiORx)

31-28 EVT_SHORT_CNT

The number of events shorter than 35, this counter is not realtime!

R /

27-24 EVT_LONG_CNT

The number of events longer than 35, this counter is not realtime!

R /

23-16 SYNCRAM_EVT_W_CNT

The number of Events writen into syncRAM

R /

15-8 SYNCRAM_E The number of Events read from odd R /

17

VT_O_R_CNT syncRAM (only for ST)(not used for Muon,..)

7-0 SYNCRAM_EVT_E_R_CNT

The number of Events read from even syncRAM (for all others but ST this is the only RAM used)

R /


ORX_ LINK_DISABLE_REG ($0x001048) Bit Name Description Type DefaultRegister Description: Allows a fast access for all optical link disable bits (one read access only) PVSS might like this

31-6 Reserved R 0x000000 &”00”

5-0 Opt_link_disable

Link disable bits set in optical control registers

R “000000”


R = Read Only; W = Write; R/W = Read/Write; N = Not exist;8-0 Max usage Max usage in word R \

R = Read Only; W = Write; R/W = Read/Write; N = Not exist;14 Underflow_log If the fifo is read when empty

13..9 Reserved 000008-0 Max usage Max usage in word R \


FIFO_STATUS_REG ($0x00104C-($0x00104C…0x00104C +11*4) (description see under the detector specific monitor registers)There are maximal 12 of these registers supported

18

2.3 User Specific Register VELO (starts from 0x002000)

VELO_ADCCLK_PHY_DLY_REGH ($0x002000)Bit Name Description Type DefaultRegister Description: For each ADC channel, an independent phase-adjustable ADC sample clock needs to be generated from the corresponding PP_FPGA. With this register, we can set the detailed Phase Delay for the highest 8 ADC clocks. The phase adjust step is 1/16 of a 40MHz clock and the possible setting value is from 0 to 15.

0x00000000

31- 28 PHY_DLY_7 Set the Phase Delay for ADCClk(15) R/W 0x027- 24 PHY_DLY_6 Set the Phase Delay for ADCClk(14) R/W 0x023- 20 PHY_DLY_5 Set the Phase Delay for ADCClk(13) R/W 0x019- 16 PHY_DLY_4 Set the Phase Delay for ADCClk(12) R/W 0x015- 12 PHY_DLY_3 Set the Phase Delay for ADCClk(11) R/W 0x011- 8 PHY_DLY_2 Set the Phase Delay for ADCClk(10) R/W 0x07- 4 PHY_DLY_1 Set the Phase Delay for ADCClk(9) R/W 0x03- 0 PHY_DLY_0 Set the Phase Delay for ADCClk(8) R/W 0x0


VELO_ADCCLK_PHY_DLY_REGL ($0x002004)Bit Name Description Type DefaultRegister Description: For each ADC channel, an independent phase-adjustable ADC sample clock needs to be generated from the corresponding PP_FPGA. With this register, we can set the detailed Phase Delay for the lowest 8 ADC clocks. The phase adjust step is 1/16 of a 40MHz clock and the possible setting value is from 0 to 15.

0x00000000

31- 28 PHY_DLY_7 Set the Phase Delay for ADCClk(7) R/W 0x027- 24 PHY_DLY_6 Set the Phase Delay for ADCClk(6) R/W 0x023- 20 PHY_DLY_5 Set the Phase Delay for ADCClk(5) R/W 0x019- 16 PHY_DLY_4 Set the Phase Delay for ADCClk(4) R/W 0x0

19

15- 12 PHY_DLY_3 Set the Phase Delay for ADCClk(3) R/W 0x011- 8 PHY_DLY_2 Set the Phase Delay for ADCClk(2) R/W 0x07- 4 PHY_DLY_1 Set the Phase Delay for ADCClk(1) R/W 0x03- 0 PHY_DLY_0 Set the Phase Delay for ADCClk(0) R/W 0x0


VELO_ADCCLK_CYC_DLY_REG ($0x002008)Bit Name Description Type DefaultRegister Description: With this register, the Clock Delay can be set for each ADC sample clock. Two bits are used for each channel, and the valid Clock Delay is from 0 to 2 clocks. If the Clock Delay is set to 3, the corresponding channel will be disabled!

0x00000000

31- 30 CYC_DLY_15 Set the Clock Delay for ADCClk(15) R/W 0029- 28 CYC_DLY_14 Set the Clock Delay for ADCClk(14) R/W 00

… … … … …3 – 2 CYC_DLY_1 Set the Clock Delay for ADCClk(1) R/W 001 – 0 CYC_DLY_0 Set the Clock Delay for ADCClk(0) R/W 00


9 CLUS_PARA_REG ($0x00200C, $0x002010 …$0x00202C)Bit Name Description Type DefaultRegister Description: The cluster algorithm needs low threshold and sum threshold for each channel. The ORx has 12 channels thus 12 registers are provided, the ARx will use only 9 of them

0x00004020

31-27 RESERVE026-16 CH_START_S

TRIPThe start strip number of this link(11 bits for velo)

0x00

15-8 STRIP_SUM_THR

Sum threshold R/W 0x40

7-0 Reserved R/W 00R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

ADC_LINK_PROBE_REG ($0x002030)Bit Name Description Type DefaultRegister Description: ADC link information ( not event based information)For each ADC link there is a correspond register, use the read_link_sel field in the PP_ctrl_reg to select.

31 RESERVE2

30-24 SYNCFIFO_M_USE

The maximum FIFO used word of the SyncFIFO

23-22 RESERVE1 R

21 ADC_EVT_LONG

If there is an event longer than 36 words, this bit will set and stick.

R

20 ADC_EVT_SHORT

If there is an event shorter than 36 words, this bit will set and stick.

R

19-18 RESERVE0 R

17 SYNCFIFO_OFLOW

Once the ADC Rx SyncFIFO overflows, this bit is set and stick

R

16 SYNCFIFO_UF Once the ADC Rx SyncFIFO underflows, R

20

LOW this bit is set and stick

15-14 ADC_CYC_DLY

Refer to adcclk_cycle_dly_reg R

13-10 ADC_PHY_DLY

Refer to adcclk_phi_dly_reg R

9-0 ADC_PIN_VALUE

Direct adc value read from external pins R


ADC_LINK_SYNC_REG ($0x002034)Bit Name Description Type DefaultRegister Description: ADC link information (event based information)For each ADC link there is a correspond register, use the read_link_sel field in the PP_ctrl_reg to select.

31-28 EVT_LONG_CNT

The number of event longer than 36 R

27-24 EVT_SHORT_CNT

The number of event shorter than 36 R

23-16 SYNCFIFO_EVT_W_CNT

The number of Event write into syncFIFO R

15-8 RESERVE0 R

7-0 SYNCFIFO_EVT_R_CNT

The number of Event read from syncFIFO R


VELO_PHI_REORDER_STRIP_CNT_REG ($0x002038)Bit Name Description Type DefaultRegister Description: The reordering needs some initial values to distinguish between PPs. These values are very difficult to obtain and should be changed only after careful considerations.

0x155AAAD6

31-30 Reserved R/W 0x0

29-24 Constant(4) Number of outer strips in O_RAM(6) for proc(4)

R/W 0x15

23-18 Constant(3) Number of outer strips in O_RAM(6) for proc(3)

R/W 0x16

17-12 Constant(2) Number of outer strips in O_RAM(7) R/W 0x2a

11-6 Constant(1) Sum of the number of inner strips in I_RAM(6) + I_RAM(7)

R/W 0x2b

5-0 Constant(0) Number of inner strips in I_RAM(7) R/W 0x16R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

VELO_HEADER_CORR_THRESHOLD_REG ($0x00203C)Bit Name Description Type DefaultRegister Description: Correction constants for strip 0 that is transmitted just after the Beetle header.

0x00000000

31-20 reserved R/W 0x000019-10 One threshold Set the threshold to accept header as one R/W 0x0009-0 Zero_threshold Set the threshold to accept header as zero R/W 0x000


21

VELO_CLUSTER_NUMBER_MAX_REG ($0x002044)Bit Name Description Type DefaultRegister Description: 0x0000008031-8 RESERVED 0x000000

7-0 Cluster_number_max

Maximum number of clusters sent out from one pp_fpga.

R/W 0x80


VELO_FIR_COEFFICIENT_REG ($0x002048 …($0x002064 )

8 Registers Bit Name Description Type DefaultRegister Description: The FIR filter for the Velo uses 4 filter coefficients that are used for the multiplication of the two left and two right neighbouring strips. The correction is calculated with an adapted scale in order to enable corrections at the percent level. The correction is using the scale 512 (9-bit) shift. Coefficients per processing channel

0x00000080

31-24 K_2r Filter coefficient for the right most strip R/W 0x00

23-16 K_1r Filter coefficient for the strip one to the right

R/W 0x00

15-8 K_1l Filter coefficient for the strip one to the left

R/W 0x00

7-0 K_2l Filter coefficient for the left most strip R/W 0x00R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

VELO_HEADER_CORR_VALUE_REG ($0x002068-$0x002084) 8 registers

8 Registers last is register 34

Bit Name Description Type DefaultRegister Description: One register per processing channel, stores the header correction for two analog beetle links, one and zero correction for each link

0x00000000

31-24 One_corr_value One correction for link 1 R/W 0x0023-16 Zero_corr_value Zero correction for link 1 R/W 0x0015-8 One_corr_value One correction for link 0 R/W 0x007-0 Zero_corr_value Zero correction for link 0 R/W 0x00


VELO_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: VELO specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation

Example for a fifo with 9-bit usedw width31..25 Reserved R 000000024..16 usedw Current used word count R 00000000

22

15 Overflow Logged R 014 Underflow Logged R 0

13..9 Reserved R 000008..0 Max_usedw Logged R 00000000

Fifo Ecs_addr Usedw width0 12-bit Derandomizer (used for nZS)

1 7-bit nZS bank data Fifo2 10-bit ZS event info Fifo before clustering3 12-bit ZS data derandomizer RAM (only used word)4 8-bit Cluster data Fifo after clusterization and linking5 9-bit ADC data Fifo after clusterization and linking6

7 7-bit ZS bank length fifo (stores adc and cluster bank length)

2.4 User Specific Register ST (starts from 0x003000)

ST_ARX_LINK_CTRL_REG ($0x003000)Bit Name Description Type DefaultRegister Description: Used to disable or enable 24 arx links per PP. Notice: 4 arx links per bettle.

0x00000000

31-27 Reserved R/W 0x000026-24 Pcn_select Select which PCN is used to be put in the

ZS header, one out of 6 (0..5)R/W 000

23-0 Arx_link_disable

1=Disable the corresponding arx link.0=Enable the corresponding arx link.For example: bit 3 .. 0 are corresponding to bettle 0. bit 3 is the arx link 3 of bettle 0.

R/W 0x00


12 CLUS_PARA_REG ($0x003004, $0x003008 …$0x003030)Bit Name Description Type DefaultRegister Description: The cluster algorithm needs low threshold and sum threshold for each channel.

0x00000000

31-28 RESERVE0 0x027-16 CH_START_STRIP The start strip number of this

link(12 bits for ST)0x000

15-8 Spill_over_threshold Spill over threshold to generate the spill over bit in the cluster

R/W 0x00

7-0 Confirmation_threshold To confirm the cluster with its sum

R/W 0x00


23

Removed register for optical links, they are common registers now !

ST_HEADER_CORR_THRESHOLD_REG ($0x00303C)Bit Name Description Type DefaultRegister Description: Correction constants for strip 0 that is transmitted just after the Beetle header.

0x00000000

31-16 reserved R/W 0x000015-8 One threshold Set the threshold to accept header as one R/W 0x007-0 Zero_threshold Set the threshold to accept header as zero R/W 0x70


ST_CLUSTER_NUMBER_MAX_REG ($0x003044)Bit Name Description Type DefaultRegister Description: 0x0000008031-8 RESERVED 0x000000

7-0 Cluster_number_max

Maximum number of clusters sent out from one pp_fpga.

R/W 0x80


ST_HEADER_CORR_VALUE_LINK0_REG ($0x003048-$0x003074) 12 registersBit Name Description Type DefaultRegister Description: One analog link requires now 4 correction values, since one processor contains two analog links, there was a second set (link0 and link1) of registers needed

0x00000000

31-24 “11” corr_value “11” correction R/W 0x0023-16 “10” corr_value “10” correction R/W 0x0015-8 “01” corr_value “01” correction R/W 0x007-0 “00” corr_value “00” correction R/W 0x00


ST_HEADER_CORR_VALUE_LINK1_REG ($0x003078-$0x0030A4) 12 registersBit Name Description Type DefaultRegister Description: One analog link requires now 4 correction values, since one processor contains two analog links, there was a second set (link0 and link1) of registers needed

0x00000000

31-24 “11” corr_value “11” correction R/W 0x0023-16 “10” corr_value “10” correction R/W 0x0015-8 “01” corr_value “01” correction R/W 0x007-0 “00” corr_value “00” correction R/W 0x00


ST_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: ST specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the

24

correct size in this documentationExample for a fifo with 9-bit usedw width

31..25 Reserved R 000000024..16 usedw Current used word count R 00000000




1 7-bit nZS bank data Fifo2 10-bit ZS event info Fifo before clustering3 12-bit ZS data derandomizer RAM (only used word)4 8-bit Cluster data Fifo after clusterization and linking5 9-bit ADC data Fifo after clusterization and linking6

7 7-bit ZS bank length fifo (stores adc and cluster bank length)

2.5 User Specific Register OT (starts from 0x004000)

6 OT_OTIS_CTRL_REG ($0x004000 ~ $0x004014)Bit Name Description Type DefaultRegister Description: OTIS control 0x1409000031-20 Reset Deadtime n link disabled for n rx_clocks after reset R/W 0x140

19 Data type 1 for zero uppressed mode, 0 for hitmap R/W 118 Non zero mode R/W 017 OTIS Comma 1 used, 0 not used R/W 016 autofind ID mode R/W 115 OTIS0 disable R/W 014 OTIS1 disable R/W 013 OTIS2 disable R/W 012 OTIS3 disable R/W 0

11-0 OTIS-ID OTIS0 R/W 0x000R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

OT_OTIS_STATUS_AB_REG ($0x004018)Bit Name Description Type DefaultRegister Description: Synchronization monitoring (read_link_select) 0x00000000

31 OTIS-ID locked R 030 OTIS1 masked autofind ID mode only R 029 OTIS1 ID not found 1 if ID = 0x000 R 028 OTIS1 ID error R 027 ‘0’ R 026 OTIS0 masked autofind ID mode only R 0

25

25 OTIS0 ID not found 1 if ID = 0x000 R 024 OTIS0 ID error R 0

23-12 OTIS-ID OTIS1 R 0x00011-0 OTIS-ID OTIS0 R 0x000


OT_OTIS_STATUS_CD_REG ($0x00401C) Bit Name Description Type DefaultRegister Description: Synchronization monitoring (read_link_select) 0x00000000

31 OTIS-ID locked R 030 OTIS3 masked autofind ID mode only R 029 OTIS3 ID not found 1 if ID = 0x000 R 028 OTIS3 ID error R 027 ‘0’ R 026 OTIS2 masked autofind ID mode only R 025 OTIS2 ID not found 1 if ID = 0x000 R 024 OTIS2 ID error R 0

23-12 OTIS-ID OTIS3 R 0x00011-0 OTIS-ID OTIS2 R 0x000


OT_ZS_LINKER_ERROR_V_REG($0x004024)Bit Name Description Type DefaultRegister Description: FIFO over/under flow error checking register 0x0000000031-19 RESERVED

18 zs_bank_length_fifo_overflow_log R 017 zs_bank_length_fifo_underflow_log R 016 sync_info_fifo_overflow_log R 015 sync_info_fifo_underflow_log R 014 event_ctrl_fifo_overflow_log R 013 event_ctrl_fifo_underflow_log R 012 gol_header_fifo_overflow_log R 011 gol_header_fifo_underflow_log R 010 bank_data_fifos_overflow_log R 09 LinkerI2II_fifo_overflow_log R 08 LinkerI2II_fifo_underflow_log R 07 LinkerI_infifo_overflow_log R 06 LinkerI_infifo_underflow_log R 05 zs_fifo_overflow_log R 04 zs_fifo_underflow_log R 03 adc_fifo_overflow_log R 02 adc_fifo_underflow_log R 01 info_fifo_overflow_log R 00 info_fifo_underflow_log R 0


26

OT_SYNC_CTRL_REG ($0x004028) Bit Name Description Type DefaultRegister Description: Synchronization control 0xE4A0000331-30 OTIS3 ID(1..0) R/W ‘11’29-28 OTIS2 ID(1..0) R/W ‘10’27-26 OTIS1 ID(1..0) R/W ‘01’25-24 OTIS0 ID(1..0) R/W ‘00’23-16 OTIS header(19..12) expected OTIS Status bits R/W 0xA0

15-0 ID lock cyclessame OTIS-ID has to be found n times to get locked (autofind ID mode only)

R/W 0x3


OT_OTIS_EVID_MON_REG ($0x00402C) Bit Name Description Type DefaultRegister Description: OTIS header L0-EvID error counter (read_link_select) 0x0000000031-24 OTIS3 L0-EvID error counter R 0x0023-16 OTIS2 L0-EvID error counter R 0x0015-8 OTIS1 L0-EvID error counter R 0x007-0 OTIS0 L0-EvID error counter R 0x00


OT_OTIS_BXID_MON_REG ($0x004030) Bit Name Description Type DefaultRegister Description: OTIS header Bunch ID error counter (read_link_select) 0x0000000031-24 OTIS3 BXID error counter R 0x0023-16 OTIS2 BXID error counter R 0x0015-8 OTIS1 BXID error counter R 0x007-0 OTIS0 BXID error counter R 0x00


OT_OTIS_ID_MON_REG ($0x004034) Bit Name Description Type DefaultRegister Description: OTIS header OTIS-ID error counter (read_link_select) 0x0000000031-24 OTIS3 OTIS-ID error counter R 0x0023-16 OTIS2 OTIS-ID error counter R 0x0015-8 OTIS1 OTIS-ID error counter R 0x007-0 OTIS0 OTIS-ID error counter R 0x00


OT_OTIS_CNTSTAT_MON_REG ($0x004038) Bit Name Description Type DefaultRegister Description: Error counter status 0x0000000031-18 RESERVED R 0

17 OTIS ID error link 5 R 016 Bunch ID error link 5 Error counter status link 5 R 015 L0 Event ID error link 5 R 0

14-12 Error counter status link 4 Error counter status link 4 R 0

27

11-9 Error counter status link 3 Error counter status link 3 R 08-6 Error counter status link 2 Error counter status link 2 R 05-3 Error counter status link 1 Error counter status link 1 R 02-0 Error counter status link 0 Error counter status link 0 R 0


OT_HIST_CTRL_REG ($0x00403C) Bit Name Description Type DefaultRegister Description: DriftTime histogram control 0x0000000031-10 RESERVED R/W 09-7 link number (possible values: 0-5) R/W 06-5 OTIS number (possible values: 0-3) R/W 04-0 channel number (possible values: 0-31) R/W 0


OT_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: OT specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation. FIFO STATUS 10 has a special content!

Example for a fifo with 9-bit usedw width31..25 Reserved R 0000000

24..16 usedw Current used word count R 00000000


13..9 Reserved R 00000

8..0 Max_usedw Logged R 00000000

Fifo Ecs_addr Usedw width0 $0x00104C 12-bit RAW data Derandomizer (nZS data)1 $0x001050 7-bit RAW bank data Fifo2 $0x001054 11-bit ZS event info Fifo before zero suppression3 $0x001058 7-bit ZS data Derandomizer RAM (only used word)4 $0x00105C 10-bit ZS bank Fifo after zero suppression and linking5 $0x001060 6-bit ZS event control data Fifo before zero suppression6 $0x001064 6-bit ZS gol header data Fifo before zero suppression7 $0x001068 7-bit ZS bank length fifo8 $0x00106C 9-bit ZS event info bank Fifo

Bit10 $0x001074 31-16 ZS Derandomizer event counter IN

15-0 ZS Derandomizer event counter OUT

28

2.6 User Specific Register MUON (starts from 0x006000)

6 MUON_TU_TYPE_REG ($0x006000 ~ $0x006014)Bit Name Description Type DefaultRegister Description: TU type definition register. 0x0000000031-28 TU_type TU type of the corresponding optical link R/W 0

27-16 ODE_HIT_offset_addr

The offset address of the HIT process of the corresponding optical link

R/W 0

15-0 ODE_PAD_offset_addr

The offset address of the PAD process of the corresponding optical link

R/W 0


MUON_HIT_PAD_PROC_CTRL_REG ($0x006018)Bit Name Description Type DefaultRegister Description: ZS process control register. 0x0000000031-6 RESERVE

5 PAD_process_disable5

Bit to disable the PAD process for Optical link 5.

R/W 0



R/W 0



R/W 0



R/W 0



R/W 0



R/W 0


MUON_ODE_ID_REG1 ($0x00601C)Bit Name Description Type DefaultRegister Description: ODE ID access register. By using this register, user can set ODE ID by ECS. Then PP FPGA will compare it with the ODE ID decoded from Orx data, called Orx ODE ID. User is also allowed to read back the Orx ODE ID.

0x00000000

31-24 orx _ODE_ID1 ODE ID of optical link 1 decoded from Orx data.

R 0


R 0

15-8 ecs_ODE_ID1 ODE ID of optical link 1 set by ECS R/W 07-0 ecs_ODE_ID0 ODE ID of optical link 0 set by ECS R/W 0


MUON_ODE_ID_REG2 ($0x006020)Bit Name Description Type Default

29

Register Description: ODE ID access register. By using this register, user can set ODE ID by ECS. Then PP FPGA will compare it with the ODE ID decoded from Orx data, called Orx ODE ID. User is also allowed to read back the Orx ODE ID.

0x00000000


R 0


R 0



MUON_ODE_ID_REG3 ($0x006024)Bit Name Description Type DefaultRegister Description: ODE ID access register. By using this register, user can set ODE ID by ECS. Then PP FPGA will compare it with the ODE ID decoded from Orx data, called Orx ODE ID. User is also allowed to read back the Orx ODE ID.

0x00000000


R 0


R 0



MUON_PAD_MAX_NUM_REG ($0x006028)Bit Name Description Type DefaultRegister Description: Register to set the maximum number of PAD per ODE and PP.

0x00008040

31-18 RESERVE

17-8 PP_PAD_max_num

The maximum number of PAD per PP R/W 128

7-0 ODE_PAD_max_num

The maximum number of PAD per ODE R/W 64


MUON_HIT_MAX_NUM_REG ($0x00602C)Bit Name Description Type DefaultRegister Description: Register to set the maximum number of HIT per ODE and PP.

0x00008040

31-18 RESERVE

17-8 PP_HIT_max_num

The maximum number of HIT per PP R/W 128

7-0 ODE_HIT_max_num

The maximum number of HIT per ODE R/W 64


30

MUON_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: MUON specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation





1 7-bit nZS bank data Fifo2 9-bit ZS event info Fifo before clustering3 12-bit ZS data derandomizer FIFO 4 5-bit HIT cnt FIFO5 9-bit HIT adc data FIFO6 7-bit Info Fifo after ZS7 7-bit ZS bank length FIFO8 5-bit PAD cnt FIFO9 9-bit PAD adc data FIFO

2.6’ User Specific Register L0MUON (starts from 0x00C000)

PP_L0MUON_CTRL_REG ($0x00C000)Bit Name Description Type DefaultRegister Description: L0Muon control register 0x0000000031-3 Reserved R/W 02-1 ZS_mode Define compression mode R/W 00

0 Orx_conectivity _test_enable

Sets the receiver part into a special test mode defined for the L0MUON only

R/W 0


6 ORX_CONNECTIVITY_TEST_DATA_REG ($0x00C018 ~ $0x00C02C)Bit Name Description Type DefaultRegister Description: Connectivity data register 0x00000000

31-0 Orx_conectivity_test_data

Data output from the connectivity test (special test mode for L0Muon)

R /


31

2.7 User Specific Register EHCAL (starts from 0x005000)

CAL_CTRL_REG ($0x005000)Bit Name Description Type DefaultRegister Description: EHCAL parameter register 0x0000000031-22 Reserved R/W 0

21-16 PIN Card Enable

Enable PIN Card R/W 00

15-8 Opt_mux_channel_sel

Opt-link mux channel select, select 4 from 6 opt-links

R/W 00

7-4 Trigger_ZS_en Trigger Zero-Suppress Enable R/W 00

3-0 ADC_ZS_enable

ADC Zero-Suppress Enable R/W 00


EHCAL_FIFO_STATUS_REG (access via common monitor registers) 13 registersRegister Description: EHCAL specific fifo monitoring, all fifos used on the PP-

FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw,

max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation




Fifo Usedw width0 12-bit Derandomizer (used for ZS and nZS)1

7-bit Linking Fifo for the ZS data path2345 11-bit Event Info FIFO for the ZS data path6 9-bit ZS data output FIFO7 7-bit ZS data bank length FIFO8

9-bit Linking Fifo for the nZS data path9101112 9-bit nZS data output FIFO

32

2.7’User Specific Register L0CAL (starts from 0x00A000)

PP_L0CAL_PARA_REG ($0x00A000)Bit Name Description Type DefaultRegister Description: L0CAL parameter register 0x0000000031-8 Reserved R/W 0

7-0 Et Threshold Et threshold used to suppress possible noise

R/W 00


L0CAL_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: L0CAL specific fifo monitoring, all fifos used on the PP-

FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw,

max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation




Fifo Usedw width0 12-bit Derandomizer (used for ZS and nZS)1 9-bit Info FIFO for the nZS data path2

9-bit Linking FIFO for the nZS data path345 9-bit Data bank FIFO for the nZS data path6 9-bit Event Info for the ZS data path7

9-bit Input FIFO for the ZS data path89

10 9-bit ZS data bank FIFO11 8-bit ZS data length FIFO

2.8 User Specific Register RICH (starts from 0x009000)

RICH_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: RICH specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation

Example for a fifo with 9-bit usedw width

33




Fifo Ecs_addr Usedw width0 11-bit Derandomizer FIFO 0

1 11-bit Derandomizer FIFO 12 11-bit Derandomizer FIFO 23 11-bit Derandomizer FIFO 34 11-bit Derandomizer FIFO 45 11-bit Derandomizer FIFO 56 11-bit Event Info In FIFO7 8-bit Data out FIFO8 8-bit Event Info out FIFO9 8-bit Data length FIFO

2.9 User Specific Register L0PUS (starts from 0x008000)

L0PUS_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: L0PUS specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation




Fifo Ecs_addr Usedw width0 11-bit ZS Derandomizer FIFO 0

1 11-bit ZS Derandomizer FIFO 12 11-bit ZS Derandomizer FIFO 23 11-bit ZS Derandomizer FIFO 34 11-bit ZS Derandomizer FIFO 45 11-bit ZS Derandomizer FIFO 56 11-bit Event Info In FIFO7 8-bit ZS Data out FIFO

34

8 8-bit Event Info out FIFO9 8-bit ZS Data length FIFO10 12-bit NZS Derandomizer FIFO 011 12-bit NZS Derandomizer FIFO 112 8-bit NZS Data out FIFO

L0PUS_PROC_ID_REG ($0x008000)Bit Name Description Type DefaultRegister Description: L0PUS Proc ID register. The L0PUS PROC ID set in this register will be compared with the PROC ID received in each enabled link.

0x00000000

31-24 Reserved R/W 023-20 PROC_ID5 PROC ID of optical link 5 set by ECS R/W 019-16 PROC_ID4 PROC ID of optical link 4 set by ECS R/W 015-12 PROC_ID3 PROC ID of optical link 3 set by ECS R/W 011-8 PROC_ID2 PROC ID of optical link 2 set by ECS R/W 07-4 PROC_ID1 PROC ID of optical link 1 set by ECS R/W 03-0 PROC_ID0 PROC ID of optical link 0 set by ECS R/W 0


2.10 User Specific Register BCM (starts from 0x00C000)

BCM_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: BCM specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation




Fifo Ecs_addr Usedw width0 11-bit Derandomizer FIFO 0

1 11-bit Derandomizer FIFO 12 11-bit Derandomizer FIFO 23 11-bit Derandomizer FIFO 34 11-bit Derandomizer FIFO 45 11-bit Derandomizer FIFO 56 11-bit Event Info In FIFO7 8-bit Data out FIFO

35

8 8-bit Event Info out FIFO9 8-bit Data length FIFO

2.11 User Specific Register L0DU (starts from 0x007000)

L0DU_DAPIN_SPY_REG ($0x007000)Bit Name Description Type DefaultRegister Description: Input data spy register. It is used to readout the instant value of 32-bit input data.

0x00000000

31-0 opt_syncdata_d The instant value of 32-bit input data R 0R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

L0DU_SYNC_EVT_CNT_REG ($0x007004)Bit Name Description Type DefaultRegister Description: Read/write Event count register. 0x00000000

31-16 event_wr_cnt The number of events that have been written into RX sync RAM.

R 0

15-0 event_rd_cnt The number of events that have been read out from RX sync RAM.

R 0


L0DU_FIFO_STATUS_REG (access via common monitor registers) 12 registersRegister Description: L0DU specific fifo monitoring, all fifos used on the PP-FPGA should be added to this set of monitoring registers in order to debug the system in case of buffer overflows, each FIFO has 4 monitored values, usedw, max_usedw, overflow and underflow. The usedw registers can have different size, please add the correct size in this documentation




Fifo Ecs_addr Usedw width0 8-bit Event Info FIFO1 8-bit Cluster bank FIFO

36

2.12 Common RAM blocks

DATA_GEN_RAM SectionA (Address range: 0x100000 – 0x1001FF)Word Name Description Type DefaultRAM Description: For ST: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.For VELO: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.

E:\hdl\vhdl_sim_data\memory_ini\data_gen_ini.hex

0- 35 GEN_DATA event data(for ST, it is (0-71)) R/W36-127

Reserved Reserved (for ST, it is (72-127)) R/W


DATA_GEN_RAM SectionB (Address range: 0x102000 – 0x1021FF)Word Name Description Type DefaultRAM Description: For ST: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.For VELO: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.





DATA_GEN_RAM SectionC (Address range: 0x104000 – 0x1041FF)Word Name Description Type DefaultRAM Description: For ST: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.For VELO: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.





37

DATA_GEN_RAM SectionD (Address range: 0x106000 – 0x1061FF)Word Name Description Type DefaultRAM Description: For ST: This RAM is reservedFor VELO: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.


0- 35 GEN_DATA event data R/W36-127

Reserved Reserved R/W


DATA_GEN_RAM SectionE (Address range: 0x108000 – 0x1081FF)Word Name Description Type DefaultRAM Description: For ST: This RAM is reservedFor VELO: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.





DATA_GEN_RAM SectionF (Address range: 0x10A000 – 0x10A1FF)Word Name Description Type DefaultRAM Description: For ST: This RAM is reservedFor VELO: On chip data generator RAM located in the input synchronizer, 32-bit wide and 128-word depth.





38

The three sections of data generator RAM are capable of generating a whole event. They are organized the same way as un-zero suppressed data format. Here below the organization for the ST and VELO data generator RAM blocks.

TRIGGER_INFO_TEST_RAM (Address range: 0x10C000 – 0x10C1FF)Word Name Description Type DefaultRAM Description: To store the trigger info test data received from SL FPGA for the purpose of testing trigger info bus hardware connection.0-15word

Trigger info test data

One word one valid trigger_info_en signal. The bit definition of one word of test data is listed as below:Bit 25: FEM_datavalidBit 24: L1AEvID_dataBit 23~16: Trigger infoBit 15~0: test data count.

R/W


2.13 User Specific RAM blocks VELO (starts from 0x200000)

8 PEDESTAL RAM (Address range: 0x200000 – 0x2000FF, 0x202000-0x2020FF,….,, 0x20E000 - 0x20E0FF)

Word Name Description Type DefaultRAM Description: To set the PEDESTAL value for pedestal sum RAM block, only PEDESTAL(19:10) is significant which will be subtracted from the INPUT DATA (an option to automatically update the pedestal values is given in auto_pedesal_update. A running average over 10-bit is calculated.

pedestal_sum_ram_init.hex

39

This RAM block is 32-bit wide and 64-word depth.0-63 Pedestal_Sum Corresponding with 64 detector channels

0-31 correspond to the even channels, 32 to 63 to the links

R/W


9 THRESHOLD RAM (Address range: 0x210000–0x2100FF, 0x212000-0x2120FF, … , 0x220000-0x2200FF)

Word Name Description Type DefaultRAM Description: In cluster algorithm, for each strip a hit threshold and a low threshold is provided from an 16 bit wide RAM.

Empty_16x64_ini.hex

31..16 Reserved 16-bit R/W 0x000015..8 low_Threshold 8-bit signed, 64 words R/W 0x007..0 hit_Threshold 8-bit signed, 64 words R/W 0x00


VELO_AVERAGE_HISTOGRAM (Address range: 0x234000–0x237FFF) ram26Word Name Description Type DefaultRAM Description: Histogram of the first iteration average in LCMS algorithm, for each 32 strip cms one histogram space of 64 words is reserved64x18word

Histo Counters Average histogram R/W


VELO_SLOPE_HISTOGRAM (Address range: 0x238000–0x23BFFF) –ram28Word Name Description Type DefaultRAM Description: Histogram of the first iteration slope in LCMS algorithm, for each 32 strip cms one histogram space of 64 words is reserved64x18word

Histo Counters Slope histogram R/W


8 VELO_REORDER_RAM (Address range: 0x23C000–0x23C0FF, … , 0x24A000–0x24A0FF) reserve

Word Name Description Type Default

40

RAM Description: Reorder definition for VELO R and PHI sensors. 8 RAMs are needed, one for each incoming processor channel

RAM_adc_reorder_0_ini.hex

64 word

Reorder ram value

8 Reorder Ram with each 64 words, only 8-bit large implemented

R/W 0x00


2.14 User Specific RAM blocks ST (starts from 0x300000)

12 PEDESTAL RAM (Address range: 0x300000 – 0x3000FF, 0x302000-0x3020FF,….,, 0x316000 - 0x3160FF)

Word Name Description Type DefaultRAM Description: To set the PEDESTAL value for pedestal sum RAM block, only PEDESTAL(17:10) is significant which will be subtracted from the INPUT DATA (an option to automatically update the pedestal values is given in auto_pedesal_update. A running average over 10-bit is calculated. This RAM block is 32-bit wide and 64-word depth.

pedestal_sum_ram_init.hex

0-63 Pedestal_Sum Corresponding with 64 detector channels 0-31 correspond to the even channels, 32 to 63 to the odd links

R/W


12 HIT_THRESHOLD RAM (Address range: 0x318000 – 0x3180FF, 0x31A000-0x31A0FF,….,, 0x32E000 - 0x32E0FF)

Word Name Description Type DefaultRAM Description: In cluster algorithm, for each strip a hit threshold should be provided from an 8bit RAM.

hit_threshold_ini.hex

0-63 Hit_Threshold Corresponding with 64 detector strips R/WR = Read Only; W = Write; R/W = Read/Write; N = Not exist;

12 CMS_THRESHOLD RAM (Address range: 0x330000 – 0x3300FF, 0x332000-0x3320FF,….,, 0x346000 - 0x3460FF)

Word Name Description Type DefaultRAM Description: In LCMS algorithm, for each strip a cms threshold should be provided from an 8bit RAM.

hit_threshold_ini.hex

41

0-63 Threshold Corresponding with 64 detector strips R/WR = Read Only; W = Write; R/W = Read/Write; N = Not exist;

1 ST_AVERAGE_HISTOGRAM (Address range: 0x348000– 0x349800) –ram36Word Name Description Type DefaultRAM Description: Histogram of the first iteration average in LCMS algorithm, for each 32 strip cms one histogram space of 64 words is reserved64x24word

Histo Counters Average histogramSize is 1536 word = 6144 byte

R/W


1 ST_SLOPE_HISTOGRAM (Address range: 0x34C000–0x34D800) –ram38Word Name Description Type DefaultRAM Description: Histogram of the second iteration slope in LCMS algorithm, for each 32 strip cms one histogram space of 64 words is reserved64x24word

Histo Counters Slope histogramSize is 1536 word = 6144 byte

R/W


2.15 User Specific RAM blocks OT (starts from 0x400000)

12 OT_HITNUM_HISTOGRAM (Address range: 0x400000–0x4160FC) Address Bit Description Type DefaultRAM Description: Histogram of the hit number for each OTIS channel, OTIS0/1, OTIS2/3 share one RAM block.

0x400000 31-0 Hitmap bin 0 link 0 R/W0x400004 31-0 Hitmap bin 1 link 0 R/W

: : : :0x4000FC 31-0 Hitmap bin 63 link 0 R/W0x402000 31-0 Hitmap bin 64 link 0 R/W

: : : :0x4020FC 31-0 Hitmap bin 127 link 0 R/W

0x404000 – 0x4040FC 31-0 Hitmap bin 0-63 link 1 R/W0x406000 – 0x4060FC 31-0 Hitmap bin 64-127 link 1 R/W0x408000 – 0x4080FC 31-0 Hitmap bin 0-63 link 2 R/W0x40A000 – 0x40A0FC 31-0 Hitmap bin 64-127 link 2 R/W0x40C000 – 0x40C0FC 31-0 Hitmap bin 0-63 link 3 R/W0x40E000 – 0x40E0FC 31-0 Hitmap bin 64-127 link 3 R/W0x410000 – 0x4100FC 31-0 Hitmap bin 0-63 link 4 R/W0x412000 – 0x4120FC 31-0 Hitmap bin 64-127 link 4 R/W0x414000 – 0x4140FC 31-0 Hitmap bin 0-63 link 5 R/W0x416000 – 0x4160FC 31-0 Hitmap bin 64-127 link 5 R/W


OT_DT_HISTOGRAM (Address range: 0x418000–0x4183FC) Address Bit Description Type DefaultRAM Description: Histogram of the drift times for a certain OTIS channel

42

(given in the OT_HIST_CTRL_REG). 0x418000 31-0 DT Histogram bin 0 R/W0x418004 31-0 DT Histogram bin 1 R/W

: : : :0x4183FC 31-0 DT Histogram bin 255 R/W


2.16 User Specific RAM blocks L0DU (starts from 0x700000)

L0DU_SYNC_SPY_RAM (Address range: 0x700000–0x700400) Word Name Description Type DefaultRAM Description: This ram is a mirror of RX Sync RAM and is used to spy the input data.

256word

opt_syncdata_d (32bit wide)

32-bit input data. R


3. Registers and RAM for “SyncLink”

3.1 Common control registers

SL_RESET_REG ($0x000000)Bit Name Description Type DefaultRegister Description: Register Description One cycle@40MHz after written, the register will return to its default value. Used to generate pulses

0x00000000

31- 16 N15-13 RESERVE1

12 ECS_TRIGGER_START

1 = Start the ecs trigger sequence programmed by the register ECS_ TRIGGER_NUMBEr _REG and ECS_TRIGGER_SCHEDULE_REG. ECS trigger!

W 0

11 ECS_MEP_FLUSH

Flush the current mep

10 ECS_EVCNT_RESET

Reset the event coutner

9 ECS_BCNT_RESET

Reset the bunch counter

8 ECS_L0FE_RESET

1 = Sent FE reset by ECS W 0

7-4 03 ECS_CNT_FRE

EZEPulse to freeze registers that are marked REALTIME. This command can also be set via readout supervisor.

W 0

2 MAC_LB_PKT_GEN

1 = Trigger SPI3 TX module to transmit only 1 test frame for Intel MAC loopback

W 0

43

1 TTC_CHIP_RESET

1 = Reset TTCrx chip W 0

0 RESIGTER_RESET

1 = Reset all the components in all FPGA including PP-FPGA except for this register itself.

W 0


SL_CTRL_REG0 ($0x000004)Bit Name Description Type DefaultRegister Description: 0x00000000

31 Reserved30 FE_data_cheen

enable0=Don’t check if there is FE data or not.1=Check FE data. If no FE data is received on all 4 PP FPGAs, an empty event is generated for each ECS/TTC trigger.

29 trigger_info_test_data_gen

If trigger_info_bus_test_en is set to ‘1’, a rising edge transition on this bit will cause trigger info transmitting part on SL FPGA to send 8 trigger info test words to all PP FPGAs. The test data received by PP FPGAs is stored in trigger info test RAM, from where the test data can be read out by ECS to check trigger info bus.

R/W 0

28 trigger_info_bus_test_en

It this bit is set to ‘1’, trigger info bus test is enabled. The normal data stream will be corrupted!Otherwise, trigger info bus works in normal mode.

R/W 0

27 pp_lbus_test_en It this bit is set to ‘1’, PP lbus test is enabled. The normal data stream will be corrupted!Otherwise, PP lbus receive part (on SL FPGA) works in normal mode.

R/W 0

26 Detector_Specific_Bank_Header_Enable

Allows to add one word of detector specific bank header which is used for Velo,ST,OT and Muon

RW 0

25 Tell1ini The TELL1 DAQ operation can be continued without ECS access (rboot of CCPC without stopping DAQ). This bit can be set after the parameter setup in order to indicate that the board has undergone already the initialization

RW 0

24 Ccpc_interrupt Set the interrupt bit of the CCPC to the value of this bit

RW 0

23 EXT_TRIG Enable external Trigger signal on LEMO1 connector, acts like an ECS trigger

RW 0

22 TTC_DEST_IP_AVAILABLE

If the TTC is able to provide IP destination information, set to 1. otherwise set to 0 and the TELL1 will try to generate

RW 0

44

the information by itself21 TTC_TRIGGE

R_TYPE_AVAILABLE

If the TTC is able to provide trig_type information, set to 1. otherwise set to 0 and the TELL1 will try to generate the trig type information by itself

RW 0

20 TTC_INFO_EN 1 = enables the information sent from TTC (trigger, trigger_type and dest_IP)0 = used the information from ECS_simu

RW 0

19 GBE_ID_WP Write protect for GBE ID PROM18-16 CCPC_PROCE

SS_CTRLTo pause/run/kill DAQ processes via console or a new running DAQ process1 -- IDLE2 – Running3 – Pause4 -- Kill

RW

15 SL_INIT_DONE

Comes from a pin of SyncLink FPGA that indicates this FPGA has been initialized.

R \

14 PP3_INIT_DONE

Comes from a pin of PP0 FPGA that indicates this FPGA has been initialized.

R \

13 PP2_INIT_DONE


R \

12 PP1_INIT_DONE


R \

11 PP0_INIT_DONE


R \

10 Error_bank_disable

Set to 1 in order to suppress the error bank RW 0

9-8 READ_PP_SEL

The monitor registers for each PP_FPGA share the same ECS address; this field is used to select a certain PP’s register to read out. (0-3)

RW 0

7 SEP_GEN_EN Use the SL internal Single_Event_Package generator to provide event instead of the actual data from all PP_FPGAs

RW 0

6 FEM_REVERT Invert the FEM data polarity (not) since there is an inversion in hardware on the FEM 1.3 observed

RW 0

5 Watchdog_bit This bit can be read and write in order to check the correct functioning of the local bus access by a watchdog process

RW 0

4 TA_TPULSE_EN

Enable the trigger adapter card to send out test-pulse for beetles

RW 0

3 FEM_EN 1 = Use the FEM to generate the data_valid signal 0 = Use the FEM model to generate the data_valid signal

RW 0

2 GBE_RESET Sys_Reset for the GBE card RW 01 – 0 ModeProc For setting “00” the ECS access to

memory is allowed, for others only RW 00

45

concurrent accessible memories can be accessed, eg Pedestals, Histograms, …


SL_CTRL_REG1 ($0x000008)Bit Name Description Type DefaultRegister Description: In this register, the swap_page can be set, which will be distributed to PP-FPGA.

0x00100F00

31-24 Expected firmware version

Expected firmware version is used for PVSS to store the desired version, because PVSS recepies depend on the firmware version this is one of the values to check before applying the recepies, v.4MSBs . 4LSBs = v.1.5

R/W 00

23 MEP_buffer_stop_write

If this bit is set, the MEP buffer is not written anymore by the processing data, this allows to spy on the data in the buffer via ECS, this can cause throttles !!!

R/W 0

22 Reserved R/W 021-17 DET_CABLE_

DLYDelay to compensate the delay the data has after 60m cable transmission, range 1 to 32

R/W 8

16- 8 TA_TP_LATANCY

The latency between test pulse and trigger send from the Trigger Adapter (in half clock cycles). The fine delay is set via PLL reconfiguration settings (reg ST_TP_REG)9-bit!

R/W 0xF

7- 0 Swap_page Swap page for accessing external memories.

R/W 0x00


SL_SIMU_CTRL_REG ($0x00000C)Bit Name Description Type DefaultRegister Description: the configuration for the TELL1 supported simulation mode like: trigger adapter control, ECS trigger information.

0x00006440

31-22 RESERVED 0000000021-20 L0-EvCnt(1..0) Two LSBs of L0-EvCnt R/W 0x019-8 RESERVED 0x0007- 3 ECS_MEP_FA

CTORThe number of SEP in each MEP If using the trigger information from ECS.

R/W 4

2- 0 ECS_TRIGGER_TYPE

The type of ecs trigger R/W 0


SPI3_TX_CTRL_REG ($0x000010)Bit Name Description Type DefaultRegister Description: This register is used to control the behavior of SPI3 TX 0x30140222

46

module. The lowest 12 bits are used to select GBE port for now 2 kinds of data flow: HLT and Intel MAC loopback. Among these 12 bits, every 4 bits are corresponding with 1 data flow. If more than 1 GBE port is selected for HLT data flow, the GBE port will be changed automatically after sending one Ethernet Packet. If more than 1 GBE port is selected for Intel MAC loopback, the GBE port will be changed automatically after sending one test frame.Notice: The port selection for SPI3 loopback is illustrated in the document: L1-board testing frame format specifications (Prepared by: Benjamin Gaidioz, Manfred Muecke)

31 MAC_LB_DP_EN

Enable Intel MAC loopback data flow

30 SPI3_LB_DP_EN

Enable SPI3 loopback data flow

29 HLT_DP_EN Enable HLT data flow28 Reserved Reserved R/W 0011

27- 25 Reserved Reserved R/W 00024 MAC_LB_PKT

_GENcontinuously generate Intel MAC loopback test frames forNotice: The MAC_LB_PKT_GEN in SL_RESET_REG can generate a single test frame

R/W 0

23- 16 MAC_LB_PKT_SIZE

These 8 bits set the number (in words) of data in a test frame that will be sent for Intel MAC loopback.

R/W 0x14

15- 12 RESERVE0 Reserved R/W 000011- 8 MAC_LB_GBE

_PORTBit 11: 1 = Port 3 is enabled. 0 = Port 3 is disabled.Bit 10: 1 = Port 2 is enabled. 0 = Port 2 is disabled.Bit 9: 1 = Port 1 is enabled. 0 = Port 1 is disabled.Bit 8: 1 = Port 0 is enabled. 0 = Port 0 is disabled.

R/W 0010

7- 4 HLT_GBE_PORT

Bit 7: 1 = Port 3 is enabled. 0 = Port 3 is disabled.Bit 6: 1 = Port 2 is enabled. 0 = Port 2 is disabled.Bit 5: 1 = Port 1 is enabled. 0 = Port 1 is disabled.Bit 4: 1 = Port 0 is enabled. 0 = Port 0 is disabled.

R/W 0010

3- 0 Reserved Reserved R/W 0010R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SPI3_RX_CTRL_REG ($0x000014)Bit Name Description Type DefaultRegister Description: This register is used to control the behavior of SPI3 RX module.

0x00000004

31-16 GBE forced For each 1000 valid words sent to GBE, a R/W 0x0000

47

stop cycle forced idle period will be inserted for flow control. The restrict BW = (120MHz*32bit) * (1000/(1000+wait_time))

15-8 RESERVE0 Reserved N \7- 0 LB_PKT_PRO

TOCOLThese 8 bits are used to check whether the received frame is a GBE test frame or not. If not, the received frame will be ignored.

R/W 0x04


THRO_CTRL_REG ($0x000018)Bit Name Description Type DefaultRegister Description: This is L0 board throttle control & status register. It will process 4 PPx_L0_throttle signals coming from 4 PP-FPGA to generate a final L0_throttle signal.

0x700007F

31 Reserved R 030-12 MEP_USE_THR Threshold for MEP buffer R/W 0x70000

11 Reserved R 010 SL_serious_err_thro

ttle_enEnable for SL serious err throttle R/W 0

9 Throttle_cnt_clr To clear throttle counters R/W 08 fake_throttle Set a faked throttle R/W 07 Reserved R 0

6-3 Throttle_PPx_en Enable for each PP throttle R/W 0xF2 Throttle_MEP_buffe

r_enEnable for MEP buffer throttle source R/W 1

1 trigger_info_throttle_en

Enable for trigger info throttle source R/W 1

0 throttle_en Overall throttle enable R/W 1R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SLTEST_REG ($0x00001C)Bit Name Description Type DefaultRegister Description: To be used for local bus tests 0x1234ABC

D31..0 For test use, no functionality R/W 1234ABCD


MEP_PID_REG ($0x000020)Bit Name Description Type DefaultRegister Description: the partition ID to be set in the MEP header. 0x

EDED1D1D31- 0 MEP_PID MEP Partition ID R/W 0x

EDED1D1DR = Read Only; W = Write; R/W = Read/Write; N = Not exist;

48

ECS_SIMU_TRIG_NUM_REG ($0x000024)Bit Name Description Type DefaultRegister Description: defines the number of ECS triggers to send. The frequency of trigger sent out is defined in the SCHEDULER register. The serial of triggers starts by setting the ecs_trigger_start bit in the auto_reset_sl register

0x00000100

31- 24 N23- 0 SIMU_TRIG_NU

MNumber of trigger to be sent, consecutive triggers count as one only

R/W 0x000100


ECS_SIMU_TRIG_SCHE_REG ($0x000028)Bit Name Description Type DefaultRegister Description: The scheduler waits a certain amount of 40MHz clock cycles before sending the next trigger. For consecutive triggers, the wait_cycle should be enlarged accordingly.

0x00010030

31- 21 RESERVE0 Reserved N \20 SCHE_BUSY Indicates ongoing l0accept sequence R \

19-16 CONSECU_NUM Number of consecutive triggers to sent. R/W 0x115- 0 WAIT_CYC Number of cycles to wait between

triggersR/W 0x30


SEP_MSB4_REG ($0x00002C)Bit Name Description Typ

eDefault

Register Description: For the Single Event Package generator, another 4 control bits are used to indicate the boundary of different SEPs thus the valid width of SEP buffer is 36bits. The extra 4MSB are set and read via this register.

0x0000000A

31- 43- 2 SEP_MSB4 Not defined yet R “10”

1 SEP_BUF_REWIND

Rewind the SEP buffer R 1

0 SEP_END The end of one SEP R 0R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

PEDESTAL_BANK_SCHEDULE_CTRL_REG ($0x000030)Bit Name Description Type DefaultRegister Description: the number of events 0x0000000831- 0 Wait_events 0: disable the pedestal bank

1: Pedestal bank will always accompany RAW bank (also known as NZS bank). It means if RAW bank is enabled by setting trigger_type as 5, Pedestal bank will be enabled as well, otherwise disabled.N (Other than 0 and 1): Pedestal bank will be generated every N events.

R/W 0x00000008


49

BANK_HEADER2_REG ($0x000034)Bit Name Description Type DefaultRegister Description: set the bit fields to be used in Bank header word 2. 0x1E1E1E1E31- 16 Source_ID R/W \15-8 Version R/W7-0 Type The actual type is generated from the

VHDL code, not the value set hereR = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SL_TP_REG ($0x000038)Bit Name Description Type DefaultRegister Description: set PLL_reconfig module to adjust testpulse delay phase.

0x00000000

31-20 RESERVED \19 READ_PARA Cmd to read data out W18 WRITE_PARA Cmd to write data for phase reconfig W17 RECONFIG Cmd to reconfig PLL W16 Reserved W15 Reserved \

14-12 CNT_PARA PLL counter selection to reconfig W11-8 CNT_TYPE PLL counter type to reconfig W7-0 DATA_ IO Data interface for configuration W

R = Read Only; W = Write; R/W = Read/Write; N = Notexist;

50

MTU_SIZE_REG ($0x00003C)Bit Name Description Type DefaultRegister Description: The value set in this register doesn’t exactly correspond to the MTU size. It is in fact the IP payload size which is (MTU-20 byte) and is 1480 for standard Ethernet. The value set in this register must be a multiple of 8. Change this value to achieve Jumbo frames.

0x000005C8

31- 16 Reserved R/W 0x000015-0 MTU_size Maximum Ethernet packet size R/W 0x05C8


BANK_CLASS_REG ($0x000040)Bit Name Description Type DefaultRegister Description: The allows to set the bank class (sometimes also called bank type) for each bank. Four different banks are supported and therefore 4 x 8-bit are required.

0x04030201

31- 24 Error class Bank class value for Error bank R/W 0x0423- 16 Pedestal class Bank class value for Pedestal bank R/W 0x0315- 8 nZS class Bank class value for non-zero

suppressed bankR/W 0x02

7- 0 ZS class Bank class value for zero-suppressed bank

R/W 0x01


NZS_BANK_SCHEDULE_CTRL_REG0 ($0x000044)Bit Name Description Type DefaultRegister Description: The NZS bank schedule is working parallel with the nzs trigger type.

To understand those two control registers, see the following example: Period factor is set to 1000, offset is set to 19, Then the nzs bank will be sent for event 1019,2019,3019,4019….

Note that:If NZS bank period factor is set to 0, nzs scheduler is disabled, If NZS bank period factor is set to 1, ALL events have NZS,The period factor MUST be bigger than offset!

0x00000000

31-0 NZS_bank_period_factor

NZS bank period factor R/W 0x00000000


NZS_BANK_SCHEDULE_CTRL_REG1 ($0x000048)Bit Name Description Type DefaultRegister Description:

This register is used to set the NZS bank offset, which is 9-bit parameter and has a valid range from 0 to 511. To avoid simultaneous NZS banks are generated on all tell1 boards, it is recommended to set NZS_bank_offset to one unique value for each tell1 board.

0x00000000

51

31-9 Reserved R/W 0x000000008-0 NZS_bank_offset NZS bank offset R/W 0x000


FE_DATA_CHECK_CTRL_REG ($0x00004C)Bit Name Description Type DefaultRegister Description: Keep the default value! Only modified by experts.

0x002400C8

31-16 OTHER_CHECK_CYCLE_N

R/W 0x24( 36 )

15-0 FIRST_CHECK_CYCLE_N

R/W 0xC8 ( 200 )


3.2 Common monitor registers

SL_PP_PROB_REG ($0x001000) Bit Name Description Type DefaultRegister Description: Probe register for each PP_FPGA, Use the read_pp_sle field to choose from 4 PP_FPGAs.

\

31-11 BANK_CNT The number of banks received from correspond PP_FPGA

10-0 SYNCFIFO_M_USE

The maximum usage of the input FIFO for the correspond PP_FPGA

R \


SL_EVT_CNT_REG ($0x001004)Bit Name Description Type DefaultRegister Description: the number of events received from each PP_FPGA. Use the read_pp_sle field to choose from 4 PP_FPGAs.

\

31-0 EVT_IN_CNT Event number from each PP_FPGA R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SL_EVT_OUT_CNT_REG ($0x001008)Bit Name Description Type DefaultRegister Description: the number of events assembled in SyncLink_FPGA \31-0 EVT_OUT_CNT Event assembled in SyncLink R \


LLINK_PARITY_ERROR_CNT_REG($0x00100C)Bit Name Description Type DefaultRegister Description: the number of parity bit errors on the LLINK transmission

\

31-24 PP3_CNT Parity bit error cnt pp3 (8-bit) R \23-16 PP2_CNT Parity bit error cnt pp2 (8-bit) R \

52

15-8 PP1_CNT Parity bit error cnt pp1 (8-bit) R \7-0 PP0_CNT Parity bit error cnt pp0 (8-bit) R \


SPI3_TX_MEP_CNT_REG ($0x001010)Bit Name Description Type DefaultRegister Description: This is a counter that counts the number of MEPs transmitted to the GBE TX interface. It is a 32-bit counter and used for debugging purpose.

\

31-0 TX_MEP_CNT SPI MEP counter R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SPI3_TX_WORD_CNT_REG ($0x001014)Bit Name Description Type DefaultRegister Description: This is a counter that counts the number of words in the last MEP transmitted to the GBE TX interface. It is reset up on a new MEP is transmitted. It is a 16-bit counter and used for debugging purpose.

\

31-16 Reserved Reserved R 0x000015-0 TX_WORD_CNT SPI MEP word counter R \


SPI3_TX_SOP_CNT_REG ($0x001018)Bit Name Description Type DefaultRegister Description: This is a counter that counts the number of Start Of Packets (SOP) sent to the GBE TX interface. It is a 32-bit counter and used for debugging purpose.

\

31-0 TX_SOP_CNT SPI SOP counter R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SPI3_TX_EOP_CNT_REG ($0x00101C)Bit Name Description Type DefaultRegister Description: This is a counter that counts the number of End Of Packets (EOP) sent to the GBE TX interface. It is a 32-bit counter and used for debugging purpose.

\

31-0 TX_EOP_CNT SPI EOP counter R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

TTC_TRIG_CNT_REG ($0x001020) REALTIMEBit Name Description Type DefaultRegister Description: The number of TTC triggers \31-0 TRIG_CNT TTC trigger number R \


TTC_TRIG_TYPE_CNT_REG ($0x001024) REALTIMEBit Name Description Type DefaultRegister Description: The number of TTC triggers types sent \31-0 TRIG_TYPE_CN

TThe number of TTC trigger types sent via TTC system

R \

53


TTC_DEST_IP_CNT_REG ($0x001028) REALTIMEBit Name Description Type DefaultRegister Description: The number of Destination IP address send via TTC \31-0 DEST_IP_CNT Number of TTC Dest IP R \


TTC_RESET_SIG_CNT_REG ($0x00102C) REALTIMEBit Name Description Type DefaultRegister Description: The number of all kinds of reset signals send via TTC \31-24 MEP_FLUSH_C

NT number of mep_flush send from TTC R

23-16 L0FE_RESET_CNT

Number of l0fe_reset send from TTC R

15-8 EVCNT_RESET_CNT

Number of event count reset from TTC R

7-0 BCNT_RESET_CNT

Number of bunch count reset from TTC R \


SL_TRIG_CNT_REG ($0x001030) REALTIMEBit Name Description Type DefaultRegister Description: The number of triggers. ( include TTC and ECS triggers) \31-0 TRIG_CNT Number of triggers R \


TRIG_INFO_TX_CNT_REG ($0x001034) REALTIMEBit Name Description Type DefaultRegister Description: The number of trigger information send from SyncLink \31-0 TRIG_INFO_TX_

CNTR \


TRIG_INFO_REQ_CNT_REG ($0x001038) REALTIMEBit Name Description Type DefaultRegister Description: The number of trigger information request from each PP_FPGA. The four PP_FPGA share the same register, use the read_pp_sel to select. Any request from any PP will activate a trigger_info broadcast and requests from other PPs during this period is blocked thus the req_cnt between PPs can be different. On the other hand there is possibility that when the request arrives the TTC trigger type is not arrive yet, and then the request will be omitted. Thus the info_req_cnt can be different from the info_tx_cnt.

\

31-0 TRIG_INFO_REQ_CNT

R \


54

TRIG_INFO_FIFO_MON_REG0 ($0x00103C) REALTIMEBit Name Description Type DefaultRegister Description: The trigger information has 5 parts: trigger_type, trigger_info(bcnt,evcnt..) pcn_cnt, dest_ip and mep_end. They are stored into separated FIFOs. Two registers provide the information about these FIFOs.

\

31-24 PCN_M_USE The maximum used number of the pcn_fifo

R

23-16 EVT_INFO_M_USE

The maximum used number of the event_info_fifo

R

15-8 TRIG_TYPE_M_USE

The maximum used number of the trigger_type_fifo

R \

7-6 Reserved5 PCN_OFLOW Once the pcn_fifo overflows, this bit is

set and stickR

4 PCN_UFLOW Once the pcn_fifo underflows, this bit is set and stick

3 EVT_INFO_OFLOW

Once the Event_info_fifo overflows, this bit is set a stick

2 EVT_INFO_UFLOW

Once the Event_info_fifo underflows, this bit is set and stick

1 TRIG_TYPE_OFLOW

Once the Trigger_type_fifo overflows, this bit is set and stick

R

0 TRIG_TYPE_UFLOW

Once the Trigger_type_fifo underflows, this bit is set and stick

R

7-0 \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

TRIG_INFO_FIFO_MON_REG1 ($0x001040) REALTIMEBit Name Description Type DefaultRegister Description: The trigger information has 5 parts: trigger_type, trigger_info(bcnt,evcnt..) pcn_cnt, dest_ip and mep_end. They are stored into separated FIFOs. Two registers provide the information about these FIFOs.

\

31-24 DEST_IP_M_USE

The maximum used number of the dest_ip_fifo

R

23-16 MEP_END_M_USE

The maximum used number of the mep_end_fifo

R

15-43 DEST_IP_OFLO

WOnce the Dest_ip_fifo overflows, this bit is set and stick

2 DEST_IP_UFLOW

Once the Dest_ip_fifo underflows, this bit is set and stick

R

1 MEP_END_OFLOW

Once the mep_end_fifo overflows, this bit is set and stick

R

0 MEP_END_UFLOW

Once the mep_end_fifo underflows, this bit is set and stick

R


MEP_WRITE_CNT_REG ($0x001044) Bit Name Description Type Default

55

Register Description: The number of MEPs written into buffer \31-0 MEP_WRITE_C

NTR \


MEP_READ_CNT_REG ($0x001048)Bit Name Description Type DefaultRegister Description: The number of MEPs read out from buffer \31-0 MEP_READ_CN

TR \


MEP_MAX_USAGE_REG ($0x00104C)Bit Name Description Type DefaultRegister Description: The number of MEPs read out from buffer \31-19 Reserve18-0 MEP_MAX_USA

GER \


SL_ERR_LOG_REG ($0x001050)Bit Name Description Type DefaultRegister Description: This is a log register to monitor the flow information of FIFOs used in SL-FPGA, which should be 0 normally.

\

31- 30 Reserved R \29 LEN_FIFO_O_FL

OW_ERROverflow log of LEN fifo used in packet framer of SL

R 0

28 LEN_FIFO_U_FLOW_ERR

Underflow log of LEN fifo used in packet framer of SL

R 0

27 HEADER_FIFO_O_FLOW_ERR

Overflow log of HEADER fifo used in packet framer of SL

R 0

26 HEADER_FIFO_U_FLOW_ERR

Underflow log of HEADER fifo used in packet framer of SL

R 0

25 DATA_FIFO_O_FLOW_ERR

Overflow log of DATA fifo used in packet framer of SL

R 0

24 DATA_FIFO_U_FLOW_ERR

Underflow log of DATA fifo used in packet framer of SL

R 0

23 MEP_INFO_FIFO_O_FLOW_ERR

Overflow log of MEP info fifo used in SL

R 0

22 MEP_INFO_FIFO_U_FLOW_ERR

Underflow log of MEP info fifo used in SL

R 0

21 SEP_LEN_FIFO_O_FLOW_ERR

Overflow log of LEN fifo used in MEP generator of SL

R 0

20 SEP_LEN_FIFO_U_FLOW_ERR

Underflow log of LEN fifo used in MEP generator of SL

R 0

19 SEP_DATA_FIFO_O_FLOW_ERR

Overflow log of DATA fifo used in MEP generator of SL

R 0

56

18 SEP_DATA_FIFO_U_FLOW_ERR

Underflow log of DATA fifo used in MEP generator of SL

R 0

17 WRITE_EN_WHILE_END_OUT_ERR

Monitor of write activity in the Linker of SL

R 0

16 NORMAL_ERR_BANK_COLLIS_ERR

Monitor of bank assemble activity in the Linker of SL

R 0

15 ERR_INFO_3_FIFO_O_FLOW_ERR

Overflow log of ERROR info fifo 3 used in Linker of SL

R 0

14 ERR_INFO_3_FIFO_U_FLOW_ERR

Underflow log of ERROR info fifo 3 used in Linker of SL

R 0



R 0



R 0



R 0



R 0



R 0



R 0

7 PP3_DATA_FIFO_O_FLOW_ERR

Overflow log of PP3 data fifo used in Linker of SL

R 0

6 PP3_DATA_FIFO_U_FLOW_ERR

Underflow log of PP3 data fifo used in Linker of SL

R 0



R 0



R 0



R 0



R 0



R 0



R 0


57

SL_MAX_USE_REG ($0x001054)Bit Name Description Type DefaultRegister Description: the maximum FIFO usage of SyncLink internal FIFO buffers used by SEP linker.

\

31 Reserved R \30-24 SEP_LEN_FIFO_

M_USE R

23-10 SEP_DATA_FIFO_M_USE

R

9- 0 MEP_HEADER_FIFO_M_USE

R \


FROZEN_EVID_REG ($0x001058) REALTIMEBit Name Description Type DefaultRegister Description: when ECS_forzen is set, the L0EvID is latched into this register.

\

31- 0 L0EvID mirror R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

FROZEN_BCNT_REG ($0x00105C) REALTIMEBit Name Description Type DefaultRegister Description: when ECS_forzen is set, the BCnt is latched into this register.accesses to the SL-FPGA.

\

31- 12 Reserved R \11- 0 BCnt mirror Counter value R \


FRAMER_MAX_USE_REG ($0x001060)Bit Name Description Type DefaultRegister Description: the number of MEPs that are bigger than 64K bytes, and the Maximum usage of the FIFOs used by packet framer

\

31-20 Reserved 00019-12 FRAG_DATA_FI

FO_MAX_USE11-5 FRAG_HEADER

_FIFO_MAX_USE

4- 0 FRAG_LEN_FIFO_MAX_USE

R \


REAL_RATE_REG0 ($0x001064)Bit Name Description Type DefaultRegister Description: the data rate statistic for GBE SPI3 interface. \31- 20 PP0_RATE The number of valid words from PP0 in

2^12 cycles@120MHz periodR \

19- 0 TRIGGER_RATE The actual trigger number is 2^20 R \

58

cycles@40MHz period R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

REAL_RATE_REG1 ($0x001068)Bit Name Description Type DefaultRegister Description: The actual rate statistic. \31- 20 PP1_RATE The number of valid words from PP1 in


19- 0 SL_LINK_EVENT_RATE

The number of events from SL Linker in 2^20 cycles@120MHz period

R \


REAL_RATE_REG2 ($0x00106C)Bit Name Description Type DefaultRegister Description: The actual rate statistic. \31- 20 PP2_RATE The number of valid words from PP2 in


19- 0 MEP_IN_RATE The number of MEPs written into QDR buffer in 2^20 cycles@120MHz period

R \


REAL_RATE_REG3 ($0x001070)Bit Name Description Type DefaultRegister Description: The actual rate statistic. \31- 20 PP3_RATE The number of valid words from PP3 in


19- 0 MEP_OUT_RATE

The number of MEPs read out from QDR buffer in 2^20 cycles@120MHz period

R \


REAL_RATE_REG4 ($0x001074)Bit Name Description Type DefaultRegister Description: The actual rate statistic. \31- 16 SL_LINK_RATE The number of words from SL Linker in

65536 cycles@120MHz periodR \

15- 0 SPI3_ RATE The number of words feed into SPI3 interface in 65536 cycles@120MHz period

R \


SL_FLOWCTRL_MONITOR_REG ($0x001078)Bit Name Description Type DefaultRegister Description: This register gives the current and logged(in the past 2us) status of SL flow control signals

0x00000000

31-24 RESERVE23..16 Ecs_error_cnt Number of ecs access that failed to have

an acknowledgeR 0

59

15 SL_INFIFO_ALMOST_FULL3_LOG14 SL_INFIFO_ALMOST_FULL2_LOG13 SL_INFIFO_ALMOST_FULL1_LOG12 SL_INFIFO_ALMOST_FULL0_LOG11 SEP_FIFO_ALMOST_FULL_LOG10 FRAG_DATA_FIFO_ALMOST_FULL_

LOG9 FRAG_HEADER_FIFO_ALMOST_FUL

L_LOG8 RESERVE17 SL_INFIFO_ALMOST_FULL36 SL_INFIFO_ALMOST_FULL25 SL_INFIFO_ALMOST_FULL14 SL_INFIFO_ALMOST_FULL03 SEP_FIFO_ALMOST_FULL2 FRAG_DATA_FIFO_ALMOST_FULL1 FRAG_HEADER_FIFO_ALMOST_FUL

L0 RESERVE0


MEP_GT_16K_CNT_REG ($0x00107C)Bit Name Description Type DefaultRegister Description: Counter of the MEPs that are bigger than 64kbyte (16kword) and therefore are sent out as empty MEPs

\

31-0 mep_16K_word_cnt 32-bit counter R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SL_DATE_REG ($0x001080)Bit Name Description Type DefaultRegister Description: Automatically generated compilation date of the firmware.

\

31-0 DATE ddmmyyyy R \R = Read Only; W = Write; R/W = Read/Write; N = Not exist;

SL_TIME_REG ($0x001084)Bit Name Description Type DefaultRegister Description: Automatically generated compilation time of the firmware.

\

31-16 Not used R \15-0 TIME hhmm R \


SL_VERSION_REG ($0x001088)Bit Name Description Type DefaultRegister Description: Frimware release version. \31-24 Built version number Automatically generated built R \

60

number, each recompilation this number is increased

23-16 Reserved15-8 PP_LOGIC_VERSION Firmware version R \7-0 SL_LOGIC_VERSION Firmware version R \


SL_TRIGGER_FIFO_USED_REG0 ($0x00108C)Bit Name Description Type DefaultRegister Description: Frimware release version. \31-24 dest_IP_rdusedw Destination fifo used R \23-16 trigger_type_usedw Trigger type fifo used R \15-8 Pcn_usedw Pcn fifo used R \7-0 Event_info_usedw Event fifo used R \


SL_TRIGGER_FIFO_USED_REG1 ($0x001090)Bit Name Description Type DefaultRegister Description: Frimware release version. \31-8 Reserved R \7-0 Mep_end_rdusedw Mep end fifo used R \


SL_FEM_DV_CNT_REG ($0x001094) REALTIMEBit Name Description Type DefaultRegister Description: Frimware release version. \31-0 Fem_dv_count Counter for FEM events R \


SL_DEST_IP_L0_EVID_LSB_ERROR_CNT_REG ($0x001098)Bit Name Description Type DefaultRegister Description: Frimware release version. \

31-16 Ip_dest_error Counts the number of TTC destinations that are different from the one set by ECS

R \

15-0 l0evid_lsb_error Counter for errors detected on wrong evid LSBs transmitted with the TTC long broadcast command used to set the destination ip. This counter will be full for ECS triggers !

R \


THRO_CNT_REG0 ($0x00109C) –REG39Bit Name Description Type DefaultRegister Description: Current value of L0_Board_Throttle Counter, whose behavior can be controlled by L0_BOARD_THROTTLE_CTRL_REG. When

\

61

the counter is in running mode (L0_BOARD_THROTTLE_CTRL_REG has its defaulted value), asserted l0_board_throttle_int will make the counter increase at the frequency of 40Mhz. Remark that the counter is saturating (no overflow), 31- 0 THRO_CNT The value of L0_BOARD_throttle

CounterR \


THRO_CNT_REG1 ($0x0010A0)Bit Name Description Type DefaultRegister Description: PP1 & PP0 throttle counter for throttle set by PP0 and PP1 in 40MHz clock cycles, 16-bit counters with saturating (no overflow),

\

31- 16 PP0_throttle_cnt Counter for PP1 R \15- 0 PP0_throttle_cnt Counter for PP0 R \


THRO_CNT_REG2 ($0x0010A4)Bit Name Description Type DefaultRegister Description: PP3 & PP2 throttle counter for throttle set by PP3 and PP3 in 40MHz clock cycles, 16-bit counters with saturating (no overflow),

\

31- 16 PP3_throttle_cnt Counter for PP3 R \15- 0 PP2_throttle_cnt Counter for PP2 R \


THRO_CNT_REG3 ($0x0010A8)Bit Name Description Type DefaultRegister Description: SL throttle counter for throttle set by SL in 40MHz clock cycles, 16-bit counters with saturating (no overflow),

\

31- 16 trigger_info_throttle_cnt

Counter for trigger info throttle R \

15- 0 throttle_MEP_buffer_cnt

Counter for MEP buffer throttle R \


SL_TTC_LAST_DEST_IP_REG ($0x0010AC)Bit Name Description Type DefaultRegister Description: Dest_IP with TTC (the value received on the TTC system contains 14 bits, 12 bit IP Dest and 2 bit LSBs of L0EvCnt

\

31- 14 Reserved R \13- 12 LSBs LSBs of the L0EvCnt) R \11- 0 Last sent Dest-IP

by ttcLast Dest-IP sent by ttc (this doesn’t correspond directly to the IP address set in the RS, it is encoded.

R \


SL_LBUS_TEST_REG ($0x0010B0-$0x0010CC) 8 x 32-bitBit Name Description Type DefaultRegister Description: for test use only \31- 0 Link test result Should be all one or all zero R \

62


QDR_CRC_ERROR_CNT_REG ($0x0010D0) reg52Bit Name Description Type DefaultRegister Description: for test use only \31-27 Reserved R

26 QDR_CRC_fifo_underflow

1=QDR CRC check FIFO is underflow R

25 QDR_CRC_fifo_overflow

1=QDR CRC check FIFO is overflow R

24- 16 QDR_CRC_fifo_max_use

Max word usage of QDR CRC check FIFO

R \

15- 0 QDR parity error cnt

Count for QDR CRC check error R \


SL_ERROR_MON_REG $0x0010D4) reg53Bit Name Description Type DefaultRegister Description: for test use only \

31..23 Reserved R22 Pp3_llink_parity_error R21 Pp2_llink_parity_error R20 Pp1_llink_parity_error R19 pp0_llink_parity_error PP-SL data bus check R18 qdr_parity_error QDR parity check R17 mep_info_fifo_underflow Mep length buf R16 mep_info_fifo_overflow Mep length buf R

15..10 Reserved R9 mep_end_fifo_overflow_log Ttc fifo R8 mep_end_fifo_underflow_log .. R7 dest_IP_fifo_overflow_log .. R6 dest_IP_fifo_underflow_log .. R5 trigger_type_fifo_overflow_log .. R4 trigger_type_fifo_underflow_log .. R3 pcn_fifo_overflow_log .. R2 pcn_fifo_underflow_log .. R1 event_info_fifo_overflow_log .. R0 event_info_fifo_underflow_log Ttc fifo R


63

THRO_CNT_REG4 ($0x0010D8) reg 54Bit Name Description Type DefaultRegister Description: SL serious error throttle counter in 40MHz clock cycles, 32-bit counters with saturating (no overflow)

\

31- 0 sl_serious_err_throttle_cnt

Counter for SL serious error throttle R \


TTC_PARITY_ERROR_CNT_REG ($0x0010DC) reg55Bit Name Description Type DefaultRegister Description: for test use only \31- 8 Reserved R \7-0 ttc_parity_error_c

ntTTC dest IP parity error count R


REAL_RATE_REG5 ($0x0010E0) reg56Bit Name Description Type DefaultRegister Description: the data rate statistic for GBE SPI3 interface. \31- 16 reserved R 0x000015- 0 ALLOWED_RAT

E The actual GBE rate restricted after forced_gbe_idle_cycles.

R \


3.3 Common RAM blocks

MEP_LOCATION_RAM (Address range: 0x100000 – 0x1001FF) Word Name Description Type DefaultRAM Description: Since the MEP size is variable, it is difficult to distinguish the boundary of MEP if look at the contents of the MEP buffer. The wraparound and overwritten makes it even worse that you can’t start to trace the MEP from the beginning of the MEP buffer. This MEP_location_RAM is a special RAM block used to record the start address of each MEP. When written a MEP into the buffer, the corresponding start address is written into this RAM block. After 128 MEPs, this RAM is overwritten from the beginning thus it can always keep the information of the last 128 MEPs. The 19 LSB is the actual start address of the MEP, the 13 MSB is the MEP id that can be used to verify if it is a valid and correspond MEP at that location.

0-127 Bit 31-19 MEP_ID

The MEP ID R

Bit 18-0MEP_SADDR

The start address of MEP. It is calculated in words. Need to shift 2 bits left and plus the base address of MEP buffer to get the ECS address of that location.

R \

64


IPv4_HEADER_RAM (Address range: 0x102000 - 0x1020FF) Blue: The fields marked in blue are set via ECS and are constant during operation. Purple: The fields in purple are set by the framer individually for each Ethernet frame.Yellow: The only difference needed for different GBE ports. SA[7:0] is set to the port number [0,1,2,3].

bit word 31 24 23 16 15

8 7 0

Settings for Port 00 DA[47:16]

1 DA[15:0] SA[47:32]

2 SA[31:8] SA[7:0]

3 TYPE VSERSION/IHL Type of Service

4 TOTAL_LEN[15:0] IDENTIFICATION[15:0]

5 FLAG[2:0] FRAGMENTOFFSET[12:0] TTL PROTOCOL

6 HEADER_CHECKSUM[15:0] IP-SA[31:16]

7 IP-SA[15:0] IP-DA[31:16]

8 IP_DA[15:0] Reserved

9- 15 Reserved for port 0

16-31 Same as for Port 0 but settings for Port 1



Word Name Description Type DefaultRAM Description: In this RAM blocks, we can set the IP packet header information. This RAM is 32-bit width and 64-word deep.0 DA[47:0] Ethernet destination address:

R/W1

1 SA[47:0] Ethernet source address, the last byte is set equal to the Port number [0,1,2,3]

R/W2

3TYPE Ethernet type R/WVSERSION/ Version: 4-bit IP version number.

65

IHL IHL: 4-bit Internet Header Length in 32-bit words.

Type of Service

Indication of desired service for this packet.

4 TOTAL_LEN Total length of this packet: set by TELL1 IP packet framer and must be all set to ‘0’ in the header RAM block

R/W

Identification Assembly aid, set by TELL1 IP packet. The MSB (Bit 15) must be set to 1 for L1 and to 0 for HLT. The least significant 15 must be set to all ‘0’ in the header RAM block.

5 FLAG Bit 0: always 0 Bit 1: (DF) 0 = may fragment, 1 = don’t fragment. Must always be set to 0. Bit 2: (MF) 0 = Last fragment, 1 = more fragments. Set by TELL1 IP packet framer and must be set to ‘0’ in the header RAM block.

R/W

Fragment offset

This measures where the fragment belongs in the packet. Set by TELL1 IP packet framer and must be set to all ‘0’ in the header RAM block.

Time to live Time in seconds for the packet to stay in the net: set by ECS.

Protocol Indicates the next level protocol, set by ECS; differs for L1 and HLT.

6 Header checksum

The checksum is on the header only: It is the 16 bit one’s complement of the one’s complement sum of all 16 bit words in the IP header. These are the 10 16 bit words starting at the Version / Type of Service field up and including to the IP Destination Address (those fields inside the red box). It is important that for the purpose of this calculation the 16 bit words are assumed to get the most significant byte (of the two bytes) from the lower address (assuming that the bytes are addressed linearly – this is sometimes referred to as big-endian byte ordering). For the calculation of the checksum the checksum field is assumed to be 0. This field in the header RAM block should be set as the pre-calculated sum of the 10 16-bit words with all proper initial value.

R/W

6 IP SA IP source address. Set by ECS R/W77 IP DA IP destination address. The higher 4 bytes are

assigned by the ECS. The least two bytes are set via IP destination assignment, note that each of the two bytes have a restricted range of (0..63) only.

R/W8

66

9-31 Reserved Reserved R/WR = Read Only; W = Write; R/W = Read/Write; N = Not exist;

INTEL_MAC_LPB_TX_RAM (Address range: 0x104000 - 0x1043FF)

bit word 31 24 23 16 15 8 7 0

0 DA[47:16]

1 DA[15:0] SA[47:32]

2 SA[31:0]

3 TYPE VSERSION/IHL Type of Service

4 TOTAL_LEN[15:0] IDENTIFICATION[15:0]

5 FLAG[2:0] FRAGMENTOFFSET[12:0] TTL PROTOCOL

6 HEADER_CHECKSUM[15:0] IP-SA[31:16]

7 IP-SA[15:0] IP-DA[31:16]

8 IP_DA[15:0] Test_ID[15:0]

9 Recv_ports Send_ports DATA

10 - 255 DATA

Word Name Description Type DefaultRAM Description: When SPI3 TX module is triggered to send test frame for Intel MAC loopback, it will read the test frame data from this RAM. So the test frame for Intel MAC loopback is defined in this RAM as the above table.In the above table, the read part is Ethernet header, the green part is IP header and the yellow part is test frame header. In order to define a valid test frame for Intel MAC loopback, TYPE must be equal to 0x0800; PROTOCOL must be equal to IPV4_Protocal_for_LPB (defined in SPI3_RX_CTRL_REG); Test_ID must be equal to 0x0003.This RAM is 32-bit width, 256-word depth.

\

0-511 Test Frame Definition

Define test frame for Intel MAC loopback R/W \


INTEL_MAC_LPB_RX_RAM (Address range: 0x106000 – 0x1063FF)Word Name Description Type DefaultRAM Description: When SPI3 RX module receives one test frame from Intel MAC loopback, it will write the test frame into this RAM.This RAM is 32-bit width, 256-word depth. \0-511 Received test

frameSaves the last valid received frame from Intel MAC loopback.

R/W \


67

SEP_GEN_RAM (Address range: 0x200000 – 0x20FFFF)Word Name Description Type DefaultRAM Description: The Single Event Package Generator is used to generate a pre-defined SEP instead of the actual event linked from the PP_FPGA. It is 36bit wide and 16K words deep. The 4MSB is accessed via a register (SEP_MSB_4B_REG) and used as the control bits for separating SEP. The 32 LSB is the actual data of the SEP.

\

16K words

Bit 35-32 Access via SEP_MSB_4B registerBit 31- 0 SEP data R/W \


4. I2C bus address definition

I2C BUS 0 (mixed)Device ADDRESS

Description: Bus used for several devices.TELL1 board ID prom 0x50TTCrx base address 0x58FEM Beetle base address 0x70

The TELL1 board ID is defined to be the following sequence:

Byte 0 Sytem (DAQ) 0x01Byte 1 Type (TELL1) 0x01Byte 2 Revision (is equal to TELL1

version)Production is 0x04

0x04

Byte 3 MSBs of the serial number 0x00Byte 4 LSBs of the serial number 0xXXByte 5 VHDL-Detector ID 0xXXByte 6 DAQ-Detector ID 0xXXByte 7 Day 0xXXByte 8 Month 0xXXByte 9-10 Year 0xXXXXByte 11 Hour 0xXXByte 12 Minute 0xXXByte 13 Second 0xXXByte 14-31 Reserved 0x00Byte 32-… Production test information

Ascii code for TELL1 label information “40DLAUTL000DDD”DDD is the serial ID in decimal

68

VHDL-Detector ID see register Constant_reg in PP_FPGA:0x1 =VELO, 0x2 =ST, 0x3 =OT, 0x4=ECAL/HCAL, 0x5=MUON, 0x6=L0MUON, 0x7=L0DU0x8= L0PUS, 0x9= RICH, 0xA=PS/SPD, 0xB=L0CAL, 0xC=BCM

DAQ-Detector ID: 0x1=VELO, 0x2=PUS, 0x3=RICH1, 0x4=TT, 0x5=IT, 0x6=OT, 0x7=RICH2, 0x8=SPD,0x9=ECAL, 0xA=HCAL, 0xB=MUON, 0xC=L0DU, 0xD=L0PUS, 0xE=L0CAL, 0xF=L0MU

I2C BUS 1 (FPGA bus)Device ADDRESS

Description: This bus was foreseen to be used to access the FPGAs via I2C as long as there was no CCPC access to these chips. Now this is used for the trigger adapter to control a Beetle connected to the trigger adapter card.Trigger Adapter Beetel Base address eg Lausanne 0x3F

I2C BUS 2 (A-Rx DAC bus)Device ADDRESS

Description: Used to set the DACs on the A-Rx cards. Not connected when O-Rx cards are used.DAC PP0 0x54DAC PP1 0x55DAC PP2 0x56DAC PP3 0x57

I2C BUS 3 (GBE Tx card bus)Device ADDRESS

Description: Used for the GBE id prom and the temperature sensors on TELL1.GBE ID prom 0x57Temperature_sens_1 (FPGA PP0) 0x48Temperature_sens_2 (Under GBE card) 0x4A

69

Appendix: Example codes for C access

1: Register Read/Write

/* example code for read-modify-write ECS registers */ int rmw_ecs_register(void){ u_int32_t err; //Variable for the specific register, which knows the bit structure of this reg PP_CTRL_REG0 ctrl_reg0; //read the register first to have the original setting values err |= lb_read_word(PP_BADDR[0]+PP_CTRL_REG0_ADDR, &ctrl_reg0.All); //modify the bit fields ctrl_reg0.Sepe.DATA_SCALE_MODE = 2; ctrl_reg0.Sepe.DATA_GEN_EN = 1; ctrl_reg0.Sepe.READ_LINK_SEL = 12; ctrl_reg0.Sepe.PSEUDO_BIT_L_THR= 0x80; ctrl_reg0.Sepe.PSEUDO_BIT_H_THR= 0x90; //write back the modified value err |= lb_write_word(PP_BADDR[0]+PP_CTRL_REG0_ADDR, ctrl_reg0.All); return(err);}

70

ecs interface library user guide - laboratoire de...

Documents