ecen 248 lab4_report

8/10/2019 ECEN 248 Lab4_report

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Lab 4: Rudimentary Adder

Circuits

Deanna Sessions

ECEN 248-511TA: Priya Venkatas

Date: October 2, 2013


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Full Adder

Truth Table

Ci Xi Yi Ci+1 Si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Karnaugh Maps

S XiYi

Ci 00 01 11 10

0 0 1 0 1

1 1 0 1 0

Cout XiYi

Ci 00 01 11 10

0 0 0 1 0

1 0 1 1 1

Logic with XOR

S = XYCC = X * Y + X * C + Y * C

Logic without XORS = (X * Y * C) + (X * Y * C) + (X * Y * C) + (X * Y * C)

C = X * Y + X * C + Y * C

Schematic


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Two Bit Ripple Carry Adder

Truth Table (carry digit is the first digit of each sum column)

WhenCin = 0

WhenCin = 1

A0 B0 A1 B1 S0 S1 Cout S0 S1 Cout

0 0 0 0 0 0 0 1 0 00 0 0 1 0 1 0 1 1 0

0 0 1 0 0 1 0 1 1 0

0 0 1 1 0 0 1 1 0 1

0 1 0 0 1 0 0 0 1 0

0 1 0 1 1 1 0 0 0 1

0 1 1 0 1 1 0 0 0 1

0 1 1 1 1 0 1 0 1 1

1 0 0 0 1 0 0 0 1 0

1 0 0 1 1 1 0 0 0 1

1 0 1 0 1 1 0 0 0 11 0 1 1 1 0 1 0 1 1

1 1 0 0 0 1 1 1 1 0

1 1 0 1 0 0 1 1 0 1

1 1 1 0 0 0 1 1 0 1

1 1 1 1 0 1 1 1 1 1

Schematic

Results:This lab was focused more on testing our skills in reading schematics and building circuitswithout any real observations to be made other than building the circuit and testing that it gave

the right output based on the truth tables we had created prior to coming to lab. The pictures

below are the finished products of each of the three adders.


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The Half Adder

Full Adder


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Two Bit Ripple Carry Adder

Each particular circuit brought its own challenges in creating the proper configuration andfinding out the right spacing that made for the easiest and most efficient wiring job, but overall

the three adders ended up being simple after I had created a schematic and truth table for it.

Conclusion:This lab had no actual data to be taken, but was rather a test of skills. I learned even more abouthow to design efficient circuits after creating a truth table. I also learned that color-coding wiresis very useful because after a while all of them start looking alike. Particularly in the Two-Bit

Ripple Carry Adder where there are many wires coming from the same pin and the pins around

them. The wires are long and get to be very confusing if you dont keep track of what wire iswhere on the schematic and what has already been placed and what has been forgotten. This was

a major learning experience after having tried setting up the Ripple Carry Adder and realizing I

had forgotten an entire track of my circuit and I just ended ripping the whole thing out of the

board and starting over which is really the best thing that I could have done.


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Questions:

1. All of the design items can be found in the design section of this lab.

2. Worst case propagation delay for a full adder design. Each of the four colored paths

denoted below show the maximum delay path because each gate is a delay unit of 1 andeach of the four paths go through the maximum of three gates.

3. This diagram shows a ripple carry adder diagram using the concept of 4 half adders to

create the same circuit that is shown above in the design section.

Student Feedback:

1. I feel like a real engineer when I work with making my own designs and circuits. This lab

would have been easier if we had shorter wires or wire clippers.

2. Nothing about the lab manual was unclear this week.3. I really think having wire clippers or shorter wires in the lab would make it much easier

to learn because then we could see our circuits more clearly and actually see the paths

that the wires are taking.

ecen 248 lab4_report

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