ece201 verilog lecture 1

Basic Verilog with VCS- 1

What’s a Hardware Description Language?

Two things distinguish an HDL from, say, “C”:

• Concurrency– The ability to do several things simultaneously. – i.e. different code-blocks can run concurrently

• Timing– Ability to represent the passing of time and sequence events

accordingly

A powerful feature of the Verilog HDL is that we can use the same language for describing, testing and debugging our system


Simulation Environment

Simulator

INPUT OUTPUT

models.v

test vectors

libraries

Assembly/Microcode

Textual messages

Tabular output

Graphical waveform

Visual drawings

controlcommands

Feedback


What is Synthesis?

Translation(& syntax-check)

Verilog code:

always @ (A or B or C)begin case (1’b1) A: result = 2’b00; B: result = 2’b01; C: result = 2’b10; default: result = 2’b00; endcaseend

GenericBoolean(GTECH)

netlist

Optimization& Target Library

Mapping

TargetTechnology

NetlistSynopsys

HDL-synthesis Toolset

Constraints


Basic Modeling Structure

always @ (posedge clk)....

assign #3 out=(sel)?in0:in1;

BodyInstancesConcurrent blocks

Ports

Module gate, block, chip,board, system, ...

Pins, Interface

Levels ofabstractions

Multilevel


An Examplemodule test_incrementer;reg clk, inc;wire [11:0] value;

initial begin

clk =0;forever #20 clk = !clk; //clk gen

endincrementer DUT(inc, value,clk);

always @(value) $display ($time,,"value = %0h",value);

initial begin

#10 inc = 1; // start incrementing#500 inc = 0; // stop incrementing

endendmodule

port connections

module incrementer(go, out, clk);input go,clk;output [11:0] out;

reg [11:0] out;

initialout = 0;

always @ (posedge clk) if (go)

out = out +1;endmodule

declarations

concurrent blocks

Procedural blockinstance


Lexical Conventions


White SpaceWhite space is used to separate words and to enhance readability.

• Verilog is a free format language

• White space characters are space, tabs, carriage returns, etc.

• Verilog ignores these characters except when they separate

language tokens.module pound_one;reg [7:0] a,a$b,b,c; // register declarationsreg clk;

initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end

/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule

module pound_one;reg [7:0] a,a$b,b,c; // register declarationsreg clk;

initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end

/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule


CommentsSingle line comments:

• Begin with "//" and end with a carriage return

• May begin anywhere on the line.

Multiple line comments:

• Begin with "/*" and end with a "*/"

• May begin and end anywhere on the line

• Everything in between is commented out


initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule


initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule

Coding style tip - Use single

line comments for comments.

Reserve multi-line

comments for commenting

out a section of code.


Strings

• Strings are enclosed in double quotes and are

specified on one line.

• Verilog recognizes normal C escape Characters

(\t, \n, \\, \",%%). (prints: tab, new line, \ , “ , %)

"Scott's module is working just great!"

"This format is spaced with a tab \t followed with this"

"\n This puts a newline before this string"

"Address = %h at time %d"

Quick Reference pg. 26 - text formatting codes


IdentifiersIdentifiers are names assigned by the user to Verilog objects such as

modules, variables, tasks etc.

• Identifiers must begin with an alphabetical character (a-z A- Z _ )

• Identifiers may contain alphabetical characters, numerics,

underscores and dollar signs (a-z A- Z 0-9 _ $).

module pound_one;reg [7:0] a,a$b,b,c; // register declarationsreg clk;initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule

module pound_one;reg [7:0] a,a$b,b,c; // register declarationsreg clk;initial begin clk=0; // initialize the clock c = 1; forever #25 clk = !clk; end/* This section of code implements a pipeline */always @ (posedge clk) begin a = b; b = c; endendmodule

Identifiers in this module:

pound_one, a, a$b, b, c, clk,


Escaped IdentifiersThe use of escaped identifiers allow any character

to be used in an identifier.

• Escaped identifiers start with a backslash (\)

and end with white space.

• Gate level netlists generated by EDA tools

(like DC) often have escaped identifiers

Examples:

\ab#~*this=or=that

\5-6

\bus_a[0] // typical of a Synopsys netlist

\bus_a[1]


Case Sensitivity

Verilog is case sensitive (so are Synopsys synthesis tools)

• Identifiers that do not match in case are considered unique

• All Verilog key words are in lower case

Examples

module // keyword

Module // unique identifier but not keyword

MODULE // unique identifier but not keyword

Quick Reference pg. 1 - reserved keywords

module MoDule (mODULE, modulE); //horrible code, but legalinput …...endmodule

Silly example...


Logic values

Verilog has 4 logic Values:

0 zero, low, false, not asserted

1 one, high, true, asserted

z or Z high impedance

x or X unknown


Integers & Real Numbers• Verilog numbers may be integers or real numbers.

• Integers may be sized or unsized.

Syntax: <size>'<base><value>

where:

<size> is the number of bits<base is b or B (binary), o or O (octal), d or D (decimal), h or H (hex)

<value> is 0-9 a-f A-F x X z Z ? _

Examples: 2'b01, 6'o243, 78, 4'ha,

• Default radix is decimal

1 1'd1

• underscores ( _ ) are ignored (use them as you would commas).

836_234_408_566_343

• a "?" is interpreted as Z (high impedance)

2'b?? 2'bzz

• When <size> is less than <value> - the upper bits are truncated.

2'b101 2'b01, 4'hfcba 4'ha


Integers & Real Numbers -2• When <size> is greater than <value>, and the left-most bit of <value> is 0 or 1,

then zero's are extended to <size> bits.

4'b01 4'b0001, 16'h0 16'h0000

4'b11 4'b0011, 16'h1 16'h0001

• When <size> is greater than <value>, and the left-most bit of <value> is an x

then the x value is extended to <size> bits

4'bx1 4'bxxx1, 16'hx 16'hxxxx

• When <size> is greater than <value>, and the left-most bit of <value> is a z then

the z value is extended to <size> bits

4'bz1 4'bzzz1, 16'hz 16'hzzzz

• Real numbers may be either in decimal or scientific notation.

• Syntax: <value>.<value> or <mantissa>e<exp>

6.439 or 5.3e6


Integers & Real Numbers Examples

3.14 decimal notation

6.4e3 scientific notation for 6400.0

16'bz 16 bit z (z is extended to 16 bits)

83 unsized decimal

8'h0 8 bits with 0 extended to 8 bits

2'ha5 2 bits with upper 6 bits truncated (binary equivalent =

01)

2_000_000 2 million

16'h0x0z 16'b0000xxxx0000zzzz

Coding style tip - don't use " ? " in a number to indicate high impedance. It only

adds confusion. If you want high impedance use " z "!!


System tasks & functionsSpecific tasks and functions may be defined by EDA vendors and users to be used as part of the simulator.

• Begin with the dollar sign ( $ )

• The Verilog standard has a number of standard $ defined

• Users may define their own built in tasks using the

Programming Language Interface (PLI)

List of most commonly used built in tasks and functions:

$monitor Continuously monitors listed signals$display Prints message to the screen$time function that returns the current simulation time

(64-bits)$stime like above, but returns truncated lower 32-bits$stop Halts execution but does not exit$finish Halts execution and exits the simulation

Ignored Ignored

See quick-reference guide pg. 26+27 for examples/syntax


Compiler directives cause the Verilog compiler to take special actions

• Indicated by the grave accent character ( ` )

• Directive remains in effect until it is overridden or modified. It is

active across modules and files.

List of most commonly used compiler directives:

`define macro text_string text substitution of text_string for

macroìnclude “file_name” file inclusion. Another

source file is substituted here

ìfdef macro Conditional Compilation verilog sourceèlse verilog sourceèndif

Compiler directives Synthesizes Synthesizes

Quick Reference pg. 28+29 - compiler directives

`define tpd 5#`tpd c = f;designA.v DUT (...);. . .

test_designA.v designA.v

vcs test_designA.v designA.v

order is important because of `define

#`tpd a = 0;. . .


Time scales establish the delay time base and precision in Verilog models.

`timescale time_unit base / time_precision base

time_unit base: sets the time unit for 1 time step ie. What a delay of 1 means

time_precision base: sets the precision ie how to round delays

Example: `timescale 1 ns / 100 ps time unit is 1 ns and round to the nearest .1ns

`timescale Compiler directive

• By default a time step is unit-less.

• Once you set a time scale for any one module you must have a time

scale set for all modules

Specify a `timescale for each module in your design


QuizQ. Which of the following code fragments (if any) will compile. What is wrong in each case (assume any Verilog syntax we have not covered yet is correct)?

A:reg clk,

1a;integer fred;

B:a = 0; /* this is a ratherb = 0; simple comment */

C:include load_file; // reuse last-weeks code

Q. What value is put into register “a” by each of these assignments? Assume “a” is 32 bits wide and has a value of “unknown” before each assignment.

a = 32'b0;a = 64'haabbccddeeff0011; a = 16'h3x0;a = 24'b1;a = 16'bz;


Verilog Modulemodule name (port_names);

module port declarations

data type declarations

procedural blocks

continuous assignments

user defined tasks & functions

primitive instances

module instances

specify blocks

endmodule

module name (port_names);



procedural blocks



primitive instances

module instances

specify blocks

endmodule

• Modules contain

• declarations

• functionality

• timing

syntax:module module_name (signal, signal,... signal ) ;

endmodule

syntax:module module_name (signal, signal,... signal ) ;

endmodule


Module Port Declarations

input a, into_here, george; // scalar portsinput [7:0] in_bus, data; //vectored portsoutput [8:31] out_bus; //vectored portinout [maxsize-1:0] a_bus; //parameterized port

input a, into_here, george; // scalar portsinput [7:0] in_bus, data; //vectored portsoutput [8:31] out_bus; //vectored portinout [maxsize-1:0] a_bus; //parameterized port

Scalar (1bit) port declarations:port_direction port_name, port_name ... ;

Vector (Multiple bit) port declarations:port_direction [port_size] port_name, port_name ... ;

port_direction : input, inout (bi-directional) or outputport_name : legal identifierport_size : is a range from [msb:lsb]

big endian or little endian may be usedliteral integers or parameters may be used




procedural blocks



primitive instances

module instances

specify blocks

endmodule




procedural blocks



primitive instances

module instances

specify blocks

endmodule


Module Instances

syntax for instantiation with port order:module_name instance_name (signal, signal,...);

syntax for instantiation with port name:module_name instance_name (.port_name(signal), .port_name (signal),... );

syntax for instantiation with port order:module_name instance_name (signal, signal,...);

syntax for instantiation with port name:module_name instance_name (.port_name(signal), .port_name (signal),... );

• A module may be instantiated within another module.• There may be multiple instances of the same module.• Ports are either by order or by name.• Use by order unless there are lots of ports• Use by name for libraries and other peoples code (may change)• Can not mix the two syntax's in one instantiation

module example (a,b,c,d);input a,b;output c,d;. . . .endmodule

example ex_inst_1(in_1, in_2, w, z);example ex_inst_2(in_1, in_2, , z); // skip a portexample ex_inst_3 (.a(w), .d(x), .c(y), .b(z));

module example (a,b,c,d);input a,b;output c,d;. . . .endmodule

example ex_inst_1(in_1, in_2, w, z);example ex_inst_2(in_1, in_2, , z); // skip a portexample ex_inst_3 (.a(w), .d(x), .c(y), .b(z));

Synthesizes Synthesizes module name (port_names);



procedural blocks



primitive instances

module instances

specify blocks

endmodule




procedural blocks



primitive instances

module instances

specify blocks

endmodule


Module HierarchyA hierarchical path in Verilog is in form of: module_name.instance_name.instance_name

top.a.b.c is the path for the hierarchy below.

A hierarchical path in Verilog is in form of: module_name.instance_name.instance_name

top.a.b.c is the path for the hierarchy below.

top

a

cb

Synthesizes Synthesizes

module

instance


Quiz

What (if anything) is wrong with the following lines of code?

input parity, data_bus [7:0];

output bit, BIT;

inout [variable +2 : variable] port;

module top;

test test_inst_a(into,reg_a,.outof(outof));

test test_inst_b(into,,outof);


Data Types

Three data type classes:Nets

• Physical connections between devices

Registers• Storage devices, variables.

Parameters• Constants

syntax:data_type identifier, identifier... ;

ordata_type [msb:lsb] identifier, identifier ... ;

syntax:data_type identifier, identifier... ;

ordata_type [msb:lsb] identifier, identifier ... ;




procedural blocks



primitive instances

module instances

specify blocks

endmodule




procedural blocks



primitive instances

module instances

specify blocks

endmodule


Nets

examples:wire a,b; // scalar wireswor [7:0] in_bus; // wired-OR buswand [8:31] out_bus; // wired and bus

examples:wire a,b; // scalar wireswor [7:0] in_bus; // wired-OR buswand [8:31] out_bus; // wired and bus

• Connect devices.• Are continuously driven by the device that drives them.• New values are propagated automatically when the

driver changes.

wire, tri standard basic interconnectwor, trior wired-OR outputswand, triand wired-AND outputstri0 pulls down when tri-statedtri1 pulls up when tri-statedtrireg stores last value when tri-statedsupply0, supply1 constant 0 or 1

wire, tri standard basic interconnectwor, trior wired-OR outputswand, triand wired-AND outputstri0 pulls down when tri-statedtri1 pulls up when tri-statedtrireg stores last value when tri-statedsupply0, supply1 constant 0 or 1






Coding style tip - Use "tri" instead of "wire" as a visual indicator for more than

one driver on a net.


Registers

reg unsigned variable of any sizeinteger signed 32-bit variabletime unsigned 64 bit variablereal signed floating point variable of double precision

reg unsigned variable of any sizeinteger signed 32-bit variabletime unsigned 64 bit variablereal signed floating point variable of double precision

reg a; // scalar reg variablereg [7:0] in_bus; // vectored reg variableinteger i, j; //32 bit signed variablestime t; // unsigned 64 bit variablereal b,c; // signed floating point variables

reg a; // scalar reg variablereg [7:0] in_bus; // vectored reg variableinteger i, j; //32 bit signed variablestime t; // unsigned 64 bit variablereal b,c; // signed floating point variables

• Storage device (may represent abstract or real).

• May be used as variables.



ece201 verilog lecture 1

Documents